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    • 1. 发明申请
    • High rate, continuous deposition of high quality amorphous, nanocrystalline, microcrystalline or polycrystalline materials
    • 高速率,连续沉积的高品质无定形,纳米晶体,微晶或多晶材料
    • US20080090022A1
    • 2008-04-17
    • US11546619
    • 2006-10-12
    • Stanford R. Ovshinsky
    • Stanford R. Ovshinsky
    • C23C16/00H05H1/24
    • C23C16/24C23C16/27C23C16/277C23C16/452C23C16/545
    • An apparatus and a method for high rate deposition of thin film materials. The method including the steps of (1) generating a supply of activated species from an energy transferring gas, through the use of a plasma; (2) separating the charged species from the non-charged species of the activated species (optionally through the use of an electrically biased screen or mesh), (3) transporting the non-charged species to a collision region (through the use of the substantial pressure differential and transonic velocity of the energy transferring gas); (4) introducing a precursor deposition feedstock gas into the collision region and; (5) producing large quantities of desirable deposition species within said collision region via the collision of non-charged species of said energy transferring gas with molecules within the precursor deposition feedstock gas; and (6) depositing, at a high deposition rate, quality thin film material onto a substrate which is adjacent to the collision. The apparatus will allow for the formation of a filtered, neutralized plasma from which non-single crystal semiconductors having fewer than 5.0×1014/cm3 subgap defects.
    • 一种用于薄膜材料高速沉积的装置和方法。 该方法包括以下步骤:(1)通过使用等离子体从能量转移气体产生活化物质的供应; (2)将带电物质与活性物质的非带电物质(任选地通过使用电偏压的筛网或筛网)分离,(3)将非带电物质运输到碰撞区域(通过使用 能量转移气体的实质压力差和跨音速); (4)将前体沉积原料气体引入碰撞区域; (5)通过所述能量转移气体的非带电物质与前体沉积原料气体内的分子的碰撞,在所述碰撞区域内产生大量所需的沉积物质; 和(6)以高沉积速率将优质的薄膜材料沉积到与碰撞相邻的衬底上。 该装置将允许形成具有少于5.0×10 14 / cm 3以下缺陷的非单晶半导体的经过滤的中和等离子体。
    • 2. 发明申请
    • Multi-functional electronic devices
    • 多功能电子设备
    • US20070267623A1
    • 2007-11-22
    • US11474546
    • 2006-06-26
    • Stanford R. Ovshinsky
    • Stanford R. Ovshinsky
    • H01L29/06
    • H01L29/0665B82Y10/00H01L29/0673H01L29/0676H01L29/1029H01L29/18H01L29/802H01L31/0324H01L31/08H01L45/06H01L45/10H01L45/1206H01L45/1233H01L45/141
    • Multi-functional electronic switching and current control devices comprising a material capable of supporting a space-charge. The devices include a load terminal, a reference terminal and a control terminal in contact with the space-charge material and a space-charge region is present at each of the multiple terminals, where each space-charge region includes an equilibrium distribution of spatially-separated charged species. Application of a control signal to the control terminal permits a perturbation of the equilibrium of charged species in the space-charge region of either or both of the load terminal and reference terminal. The space-charge perturbations will induce quantum interactions between the space-charge regions associated with the load and reference terminals that will contribute to modulation or inducement of gain, current control, or conductivity mechanism. The devices may be used as interconnection devices or signal providing devices in circuits and networks.
    • 多功能电子开关和电流控制装置包括能够支撑空间电荷的材料。 这些装置包括与空间电荷材料接触的负载端子,参考端子和控制端子,并且在多个端子中的每一个处存在空间电荷区域,其中每个空间电荷区域包括空间电荷材料的平衡分布, 分离带电物种。 将控制信号施加到控制端子允许在负载端子和参考端子中的任一个或两者的空间电荷区域中的带电物质的平衡的扰动。 空间电荷扰动将引起与负载和参考端子相关的空间电荷区域之间的量子相互作用,这将有助于增益,电流控制或导电机制的调制或诱导。 这些设备可以用作电路和网络中的互连设备或信号提供设备。
    • 3. 发明授权
    • Quantum limit catalysts and hydrogen storage materials
    • 量子极限催化剂和储氢材料
    • US07250386B2
    • 2007-07-31
    • US10733088
    • 2003-12-11
    • Stanford R. Ovshinsky
    • Stanford R. Ovshinsky
    • B01J23/02B01J23/00
    • B01J35/002B01J23/02B01J23/22B01J23/74B01J23/745B01J23/75B01J35/0013B01J35/006B01J37/086B01J37/343C01B3/0026C01B3/0031Y02E60/327
    • A quantum limit catalyst. The instant quantum limit catalyst is comprised of atomic aggregations whose dimensions correspond to the quantum limit. In the quantum limit, the atomic aggregations acquire structural configurations and electronic interactions not attainable in the macroscopic limit. The structural configurations possible in the quantum limit correspond to atomic aggregations having bond lengths, bond angles, topologies and coordination environments that differ from those found in the macroscopic limit. The electronic interactions possible in the quantum limit originate from wavefunction overlap and tunneling between atoms and lead to modifications in the magnitude and/or spatial distribution of electron density at catalytic sites to provide improved catalytic properties. Representative quantum limit catalysts include quantum scale atomic aggregations of metal atoms. Examples including catalysts derived from Fe, Mg, V and Co are disclosed. Catalytic properties are exemplified in the context of hydrogen storage.
    • 量子限制催化剂。 瞬时量子限制催化剂由尺寸对应于量子极限的原子聚集体组成。 在量子极限中,原子聚集获得宏观极限中不可获得的结构配置和电子相互作用。 量子限制中可能的结构配置对应于具有键长度,键角度,拓扑结构和协调环境的原子聚合,其不同于在宏观极限中发现的那些。 在量子限制中可能的电子相互作用起源于原子之间的波函数重叠和隧穿,并导致催化位点电子密度的大小和/或空间分布的修改,以提供改进的催化性能。 代表性的量子极限催化剂包括金属原子的量子尺度原子聚集。 公开了包括衍生自Fe,Mg,V和Co的催化剂的实例。 催化性质在氢存储的背景下是举例说明的。
    • 4. 发明授权
    • Multiple bit chalcogenide storage device
    • US07227170B2
    • 2007-06-05
    • US10657285
    • 2003-09-08
    • Stanford R. Ovshinsky
    • Stanford R. Ovshinsky
    • H01L47/00G11C11/00
    • G11C13/0004G11C11/56G11C11/5678H01L45/06H01L45/1206H01L45/1233H01L45/1246H01L45/144
    • Multi-terminal chalcogenide memory cells having multiple binary or non-binary bit storage capacity and methods of programming same. The memory cells include a pore region containing a chalcogenide material along with three or more electrical terminals in electrical communication therewith. The configuration of terminals delineates spatially distinct regions of chalcogenide material that may be selectively and independently programmed to provide multibit storage. The application of an electrical signal (e.g. electrical current or voltage pulse) between a pair of terminals effects a structural transformation in one of the spatially distinct portions of chalcogenide material. Application of electrical signals to different pairs of terminals within a chalcogenide device effects structural transformations in different portions of the chalcogenide material. The structural states produced by the structural transformations may be used for storage of information values in a binary or non-binary (e.g. multilevel) system. The selection of terminals provides for the selective programming of specific and distinct portions within a continuous volume of chalcogenide material, where each selectively programmed portion provides for the storage of a single binary or non-binary bit. In devices having three or more terminals, two or more selectively programmable portions are present within the volume of chalcogenide material occupying the pore region and multibit storage is accordingly realized. The instant invention further includes methods of programming chalcogenide memory cells having three or more terminals directed at the storage of multiple bits of information in binary or non-binary systems.
    • 5. 发明授权
    • Error reduction circuit for chalcogenide devices
    • 硫属化物装置的误差减少电路
    • US07186999B2
    • 2007-03-06
    • US11064637
    • 2005-02-24
    • Stanford R. OvshinskyMorrel H. Cohen
    • Stanford R. OvshinskyMorrel H. Cohen
    • H01L29/06
    • G11C13/0004
    • An error reduction circuit for use in arrays of chalcogenide memory and computing devices. The error reduction circuit reduces the error associated with the output response of chalcogenide devices. In a preferred embodiment, the output response is resistance and the error reduction circuit reduces errors or fluctuations in the resistance. The error reduction circuit includes a network of chalcogenide devices, each of which is nominally equivalent and each of which is programmed into the same state having the same nominal resistance. The inclusion of multiple devices in the network of the instant error reduction circuit provides for a reduction in the contributions of both dynamic fluctuations and manufacturing fluctuations to the error in the output response.
    • 用于硫族化物存储器和计算设备阵列的误差减少电路。 误差降低电路减少与硫族化物器件的输出响应相关的误差。 在优选实施例中,输出响应是电阻,并且误差减小电路减小电阻的误差或波动。 误差减小电路包括一个硫族化物器件网络,其中每个器件名义上是等效的,并且每个都被编程成具有相同标称电阻的相同状态。 在瞬时误差减少电路的网络中包含多个设备提供了动态波动和制造波动对输出响应误差的贡献的降低。
    • 7. 发明授权
    • Methods of factoring and modular arithmetic
    • 分解和模数运算方法
    • US06963893B2
    • 2005-11-08
    • US10726985
    • 2003-12-03
    • Stanford R. OvshinskyBoil Pashmakov
    • Stanford R. OvshinskyBoil Pashmakov
    • G06F7/49G11C11/56G11C16/02H01L27/105H01L29/04H01L45/00G06F7/50
    • G11C13/0004G06F7/49G11C11/56G11C11/5678G11C13/004
    • A method of factoring numbers in a non-binary computation scheme and more particularly, a method of factoring numbers utilizing a digital multistate phase change material. The method includes providing energy in an amount characteristic of the number to be factored to a phase change material programmed according to a potential factor of the number. The programming strategy provides for the setting of the phase change material once for each time a multiple of a potential factor is present in the number to be factored. By counting the number of multiples and assessing the state of the phase change material upon execution of the method, a determination of whether a potential factor is indeed a factor may be made. A given volume of phase change material may be reprogrammed for different factors or separate volumes of phase change material may be employed for different factors. Parallel factorization over several potential factors may be achieved by combining separate volumes of phase change material programmed according to different potential factors. Methods of addition and computing congruences in a modular arithmetic system are also included.
    • 一种在非二进制计算方案中分解数字的方法,更具体地说,涉及使用数字多态相变材料分解数字的方法。 该方法包括将根据该数量的潜在因素编程的相变材料的要素数量特征量的能量提供给该相变材料。 编程策略提供了相变材料的设置,每次在要考虑的数量中存在潜在因子的倍数。 通过计算倍数并在执行该方法时评估相变材料的状态,可以确定潜在因素是否确实是一个因素。 可以对于不同的因素对给定体积的相变材料进行重新编程,或者可以针对不同的因素采用单独体积的相变材料。 可以通过组合根据不同潜在因素编程的不同体积的相变材料来实现几个潜在因素的并行分解。 还包括在模块化算法系统中添加和计算一致性的方法。