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1. 发明授权

US08461009B2 Spacer and process to enhance the strain in the channel with stress liner 失效
标题翻译：间距和过程，以增强通道中应力衬里的应变
公开(公告)号：US08461009B2
公开(公告)日：2013-06-11
申请号：US11307928
申请日：2006-02-28
申请人： Atul C. Ajmera , Christopher V. Baiocco , Xiangdong Chen , Wenzhi Gao , Young Way Teh
发明人： Atul C. Ajmera , Christopher V. Baiocco , Xiangdong Chen , Wenzhi Gao , Young Way Teh
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of an first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide and second nitride layer is applied. Deep implanting of source and drain in the substrate occurs, and removal of the second nitride, second oxide, and first nitride layers.
摘要翻译：通过应力衬垫，间隔物，集成电路形成工艺和集成电路增强通道中的应变的方法。将由第一氧化物和第一氮化物层构成的第一间隔物施加到基板上的栅电极，并施加由第二氧化物和第二氮化物层构成的第二间隔物。在衬底中深入植入源极和漏极，并且去除第二氮化物，第二氧化物和第一氮化物层。

2. 发明申请

US20120074519A1 CRACK STOP STRUCTURE ENHANCEMENT OF THE INTEGRATED CIRCUIT SEAL RING 审中-公开
标题翻译：集成电路密封圈的断裂结构增强
公开(公告)号：US20120074519A1
公开(公告)日：2012-03-29
申请号：US13245554
申请日：2011-09-26
申请人： Alfred Yeo , Kai Chong Chan
发明人： Alfred Yeo , Kai Chong Chan
IPC分类号： H01L29/06
CPC分类号： H01L23/585 , H01L23/562 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： An improved crack stop structure (and method of forming) is provided within a die seal ring of an integrated circuit die to increase crack resistance during the dicing of a semiconductor wafer. The crack stop structure includes a stack layer (of alternating insulating and conductive layers) and an anchor system extending from the stack layer to a predetermined point below the surface of the substrate. A crack stop trench is formed in the substrate and filled with material having good crack resistance to anchor the stack layer to the substrate.
摘要翻译：在集成电路管芯的模具密封环内设置改进的裂纹结构（和成形方法），以在半导体晶片的切割期间提高抗裂性。裂纹停止结构包括堆叠层（交替的绝缘和导电层）和从堆叠层延伸到衬底表面下方的预定点的锚定系统。在衬底中形成裂纹停止沟槽，并且填充具有良好抗裂性的材料以将堆叠层锚固到衬底上。

3. 发明授权

US08138055B2 Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same 有权
标题翻译：具有pFET与SiGe栅极电极和嵌入式SiGe源极/漏极区域的半导体器件及其制造方法
公开(公告)号：US08138055B2
公开(公告)日：2012-03-20
申请号：US12850119
申请日：2010-08-04
申请人： Jin-Ping Han , Alois Gutmann , Roman Knoefler , Jiang Yan , Chris Stapelmann , Jingyu Lian , Yung Fu Chong
发明人： Jin-Ping Han , Alois Gutmann , Roman Knoefler , Jiang Yan , Chris Stapelmann , Jingyu Lian , Yung Fu Chong
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823864 , H01L29/66636 , H01L29/7843 , H01L29/7845 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.
摘要翻译：在制造半导体器件的方法中，在包括第一栅极电极材料的pFET区域的衬底上形成第一栅极堆叠。在pFET区域蚀刻衬底的源/漏区，并且在pFET区域蚀刻第一栅极堆叠的第一栅电极材料。蚀刻对蚀刻氧化物和/或氮化物材料至少部分选择性，使得nFET区域被氮化物层（和/或第一氧化物层）屏蔽，并且使得pFET区域的间隔结构至少部分保留。形成源极/漏极凹部，并且通过蚀刻去除第一栅电极材料的至少一部分，以在pFET区域形成栅电极凹部。 SiGe材料在源极/漏极凹槽中以及在pFET区域的栅极电极凹槽中外延生长。 SMT效应由相同的氮化物nFET掩模实现。

4. 发明申请

US20110169096A1 BALANCING NFET AND PFET PERFORMANCE USING STRAINING LAYERS 失效
标题翻译：使用应变层平衡NFET和PFET性能
公开(公告)号：US20110169096A1
公开(公告)日：2011-07-14
申请号：US12687374
申请日：2010-01-14
申请人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
发明人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
摘要翻译：集成电路结构包括衬底和衬底上或衬底中的至少一对互补晶体管。该对互补晶体管包括第一晶体管和第二晶体管。该结构还包括第一晶体管和第二晶体管上的第一应力产生层，以及在第一晶体管和第二晶体管上的第一应力产生层上的第二应力产生层。第一应力产生层在第一晶体管和第二晶体管上施加拉伸应变力。第二应力产生层对第一应力产生层，第一晶体管和第二晶体管施加压缩应变力。

5. 发明申请

US20110163356A1 HYBRID TRANSISTOR 有权
标题翻译：混合晶体管
公开(公告)号：US20110163356A1
公开(公告)日：2011-07-07
申请号：US12651487
申请日：2010-01-04
申请人： Ming ZHU , Chun Shan YIN , Elgin QUEK , Shyue Seng TAN
发明人： Ming ZHU , Chun Shan YIN , Elgin QUEK , Shyue Seng TAN
IPC分类号： H01L29/78 , H01L21/8239
CPC分类号： H01L29/7885 , H01L21/28273 , H01L29/66795 , H01L29/66825 , H01L29/785
摘要： A method of forming a device is disclosed. The method includes providing a substrate having an active area. A gate is formed on the substrate. First and second current paths through the gate are formed. The first current path serves a first purpose and the second current path serves a second purpose. The gate controls selection of the current paths.
摘要翻译：公开了一种形成装置的方法。该方法包括提供具有活性区域的基底。在基板上形成栅极。形成通过栅极的第一和第二电流路径。第一电流通路用于第一目的，第二电流通路用于第二目的。门控制当前路径的选择。

6. 发明授权

US07960283B2 Method for reducing silicide defects in integrated circuits 有权
标题翻译：降低集成电路中硅化物缺陷的方法
公开(公告)号：US07960283B2
公开(公告)日：2011-06-14
申请号：US12825325
申请日：2010-06-28
申请人： Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/28 , H01L21/311
CPC分类号： H01L29/665 , H01L21/31116 , H01L29/6653 , H01L29/78
摘要： A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
摘要翻译：描述了在集成电路（IC）中形成硅化物触点的方法。在水解过程期间进行间隔物拉回蚀刻以减少间隔物与间隔物底切下的源/漏硅化物接触之间的应力。这样可以防止表面缺陷进入衬底，从而使硅化物管缺陷的发生最小化。间隔物拉回蚀刻可以在第一退火步骤之后进行以形成硅化物接触。

7. 发明授权

US07955936B2 Semiconductor fabrication process including an SiGe rework method 有权
标题翻译：半导体制造工艺包括SiGe返工方法
公开(公告)号：US07955936B2
公开(公告)日：2011-06-07
申请号：US12172756
申请日：2008-07-14
申请人： Yong Siang Tan , Chung Woh Lai , Jin-Ping Han , Henry K. Utomo , Judson R. Holt , Eric Harley , Richard O. Henry , Richard J. Murphy
发明人： Yong Siang Tan , Chung Woh Lai , Jin-Ping Han , Henry K. Utomo , Judson R. Holt , Eric Harley , Richard O. Henry , Richard J. Murphy
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L21/30608 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C.
摘要翻译：一种制造半导体器件的方法包括形成SiGe区域。 SiGe区可以是嵌入式源极和漏极区域，或者是半导体器件内的压缩SiGe沟道层或其它SiGe区域。将SiGe区域暴露于SC1溶液，并且选择性地除去SiGe区域的多余表面部分。 SC1蚀刻工艺可以是返工方法的一部分，其中通过暴露SiGe和保持在升高的温度下的SC1溶液来选择性地除去SiGe的过度生长区域。进行蚀刻处理足以除去SiGe的多余表面部分的一段时间。 SC1蚀刻工艺可以在约25℃至约65℃的升高的温度下进行。

8. 发明授权

US07932152B2 Method of forming a gate stack structure 有权
标题翻译：形成栅极堆叠结构的方法
公开(公告)号：US07932152B2
公开(公告)日：2011-04-26
申请号：US12025789
申请日：2008-02-05
申请人： Will Wong , Lap Chan , Alan Lek
发明人： Will Wong , Lap Chan , Alan Lek
IPC分类号： H01L21/8234
CPC分类号： H01L21/28202 , H01L21/28035 , H01L21/823462 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method of forming an integrated circuit structure on a substrate, the substrate includes a primary region and a secondary region. A first layer of a first material of a first thickness is formed over the substrate. A portion of the first layer is removed over the primary region to expose the substrate. The structure is exposed to an oxidizing medium. This forms a second layer, for example, of an oxide material primary region of the substrate. The second layer has a second thickness. Additionally, at least a portion of said first layer is converted to a third layer, for example, of an oxynitride material. The third layer has a third thickness.
摘要翻译：一种在基板上形成集成电路结构的方法，所述基板包括主区域和次区域。在衬底上形成第一厚度的第一材料的第一层。第一层的一部分在主区域上被去除以暴露衬底。该结构暴露于氧化介质。这形成例如基板的氧化物材料主区域的第二层。第二层具有第二厚度。另外，所述第一层的至少一部分被转换成例如氮氧化物材料的第三层。第三层具有第三厚度。

9. 发明授权

US07926000B2 Integrated circuit system employing dipole multiple exposure 有权
标题翻译：采用偶极多重曝光的集成电路系统
公开(公告)号：US07926000B2
公开(公告)日：2011-04-12
申请号：US11683691
申请日：2007-03-08
申请人： Sia Kim Tan , Qunying Lin
发明人： Sia Kim Tan , Qunying Lin
IPC分类号： G06F17/50
CPC分类号： G03F7/70466 , G03F1/70
摘要： An integrated circuit system that includes: providing a first mask including a first feature; exposing the first mask to a radiation source to form an image of the first feature on a photoresist material that is larger than a structure to be formed, the photoresist material being formed over a substrate that includes the integrated circuit system; providing a second mask including a second feature; aligning the second mask over the image of the first mask to form an overlap region; and exposing the second mask to the radiation source to form an image of the second feature on the photoresist material that is larger than the structure to be formed.
摘要翻译：一种集成电路系统，包括：提供包括第一特征的第一掩模; 将所述第一掩模暴露于辐射源以在光致抗蚀剂材料上形成大于所形成的结构的所述第一特征的图像，所述光致抗蚀剂材料形成在包括所述集成电路系统的基板上; 提供包括第二特征的第二掩模; 将第二掩模对准第一掩模的图像以形成重叠区域; 以及将所述第二掩模暴露于所述辐射源以在所述光致抗蚀剂材料上形成大于所述待形成结构的第二特征的图像。

10. 发明申请

US20110034040A1 LOCALIZED ANNEAL 有权
标题翻译：本地化
公开(公告)号：US20110034040A1
公开(公告)日：2011-02-10
申请号：US12537268
申请日：2009-08-07
申请人： Dexter TAN , Chee Chong LIM , Sai Hooi YEONG , Chee Mang NG
发明人： Dexter TAN , Chee Chong LIM , Sai Hooi YEONG , Chee Mang NG
IPC分类号： H01L21/263 , F27B5/14 , A21B2/00
CPC分类号： F27B17/0025 , H01L21/2686 , H01L21/67115
摘要： A method of forming a device is presented. The method includes providing a wafer having an active surface and dividing the wafer into a plurality of portions. The wafer is selectively processed by localized heating of a first of the plurality of portions. The wafer is then repeatedly selectively processed by localized heating of a next of the plurality of portions until all plurality of portions have been selectively processed.
摘要翻译：提出了一种形成装置的方法。该方法包括提供具有活性表面并将晶片分成多个部分的晶片。通过对多个部分中的第一部分的局部加热选择性地处理晶片。然后通过对多个部分中的下一个的局部加热来重复地选择性地处理晶片，直到所有多个部分已被选择性地处理。

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