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1. 发明授权

US6075790A Asynchronous transfer mode system for, and method of, writing a cell payload between a control queue on one side of a system bus and a status queue on the other side of the system bus 失效
标题翻译：在系统总线一侧的控制队列与系统总线另一侧的状态队列之间写入单元有效负载的异步传输模式系统及其方法
公开(公告)号：US6075790A
公开(公告)日：2000-06-13
申请号：US764692
申请日：1996-12-11
申请人： Bradford C. Lincoln , David R. Meyer
发明人： Bradford C. Lincoln , David R. Meyer
IPC分类号： H04L12/56 , H04Q11/04 , H04L12/28
CPC分类号： H04Q11/0478 , H04L2012/5616 , H04L2012/5681
摘要： A status queue in a host and a control queue in a segmentation and reassembly (SAR) subsystem are on opposite sides of a host bus in a control plane. Buffer descriptors in the host and the SAR and buffers in the host are in a data plane. To transfer cell payloads to a first line interfacing the SAR, the host writes the SAR that it has such cell payloads. The host writes the host buffer descriptors into the control queue to obtain the transfer of the buffer payload to the first line. The SAR writes the status queue when the transfer has been completed. To transfer cell payloads to the host memory, the host writes into the control queue the address of the buffers to receive the payload from the SAR. The SAR then writes the buffer descriptors to the status queue to obtain the transfer of the cell payloads to the buffers. Each of the control and status queues may be respectively considered to constitute two (2) control queues and two (2) status queues. The SAR determines if either status queue is full by comparing the address written by the SAR into such status queue with the address written by the host periodically to the SAR where the host is in the status queue. The host determines if either control queue is full by comparing the address written by the host into such control queue with the address written by the SAR periodically to the host where the SAR is in the control queue.
摘要翻译：主机中的状态队列和分段和重组（SAR）子系统中的控制队列位于控制平面中的主机总线的相对侧。主机和SAR中的缓冲区描述符和主机中的缓冲区位于数据平面中。为了将信元有效载荷传送到与SAR相连接的第一行，主机写入SAR具有这样的信元有效载荷。主机将主机缓冲区描述符写入控制队列，以获得缓冲区有效载荷到第一行的传输。传输完成后，SAR写状态队列。为了将单元有效载荷传送到主机存储器，主机向控制队列写入从SAR接收有效负载的缓冲器的地址。然后，SAR将缓冲区描述符写入状态队列，以获得单元有效负载到缓冲区的传输。每个控制和状态队列可以分别被认为构成两（2）个控制队列和两个（2）状态队列。 SAR通过将由SAR写入的地址与这样的状态队列进行比较，由主机周期性地向主机处于状态队列的SAR写入地址，确定状态队列是否满。主机通过将由主机写入这样的控制队列的地址与由SAR所写入的地址周期性地向SAR控制队列中的主机进行比较来确定是否任一个控制队列满。

2. 发明授权

US5949781A Controller for ATM segmentation and reassembly 失效
标题翻译：控制器用于ATM分段和重组
公开(公告)号：US5949781A
公开(公告)日：1999-09-07
申请号：US467311
申请日：1995-06-06
申请人： Bradford C. Lincoln , Douglas M. Brady , David R. Meyer , Warner B. Andrews, Jr.
发明人： Bradford C. Lincoln , Douglas M. Brady , David R. Meyer , Warner B. Andrews, Jr.
IPC分类号： H04Q3/00 , H04L12/56 , H04Q11/04
CPC分类号： H04Q11/0478 , H04L12/5601 , H04L2012/561 , H04L2012/5616 , H04L2012/5649 , H04L2012/5651 , H04L2012/5652 , H04L2012/5679
摘要： A header and a payload in a cell are separated for transfer between a cell interface and a host memory. The header is transferred to a control memory. For transfer to the host memory, the control memory initially provides a host-memory region address and the region length. The payload is recorded in such region. The control memory also provides a second host-memory region address, and length, when the payload length exceeds the payload length in the first address region. For transfer from the host memory to the cell interface, the control memory provides a host memory region address and the header combines the header and the payload and passes the combination to the cell interface. Cells from different sources (i.e. terminals) are scheduled at table positions dependent upon their individual transfer rates. The cells at the scheduled positions are normally transferred in time slots corresponding to such positions. When more than one (1) cell is scheduled at the same position, one (1) cell is transferred on a preset priority basis to the corresponding time slot. The other cells are delayed for transfer subsequently in idle time slots (i.e. no cell normally scheduled) in the same or other priorities. The cell delays for each source are accumulated to a maximum preset value. When the cell delays accumulated for a source exceed the normal time spacing between cells from that source, a cell the source transfers a cell in an idle time slot prior to the normally scheduled time slot to compensate for such delay.
摘要翻译：单元格中的标题和有效负载被分离以在单元接口和主机存储器之间传送。标题被传送到控制存储器。为了传输到主机存储器，控制存储器最初提供主机 - 存储器区域地址和区域长度。有效载荷记录在这样的区域。当有效载荷长度超过第一地址区域中的有效载荷长度时，控制存储器还提供第二主机 - 存储器区域地址和长度。为了从主机存储器传送到单元接口，控制存储器提供主机存储器区域地址，并且报头组合报头和有效载荷，并将组合传递到单元接口。来自不同来源（即终端）的小区根据其个人传送速率被安排在表位置。预定位置处的单元通常在对应于这些位置的时隙中传送。当多于一个（1）小区被调度在相同位置时，一（1）个小区以预设的优先级被传送到相应的时隙。在相同或其他优先级中，其他小区被延迟以在空闲时隙（即，没有小区正常安排）中传送。每个源的单元延迟被累积到最大预设值。当来自源的单元延迟超过来自该源的单元之间的正常时间间隔时，源单元在正常调度的时隙之前的空闲时隙中传送单元以补偿这种延迟。

3. 发明授权

US5715437A System for, and method of, processing in hardware commands received from software without polling of the hardware by the software 失效
标题翻译：从软件接收的硬件命令的处理系统和方法，而不用软件轮询硬件
公开(公告)号：US5715437A
公开(公告)日：1998-02-03
申请号：US337939
申请日：1994-11-10
申请人： David C. Baker , Michael D. Asal
发明人： David C. Baker , Michael D. Asal
IPC分类号： G06F3/153 , G06F9/24 , G06F9/38 , G06T11/00 , G09G5/36 , G06T1/60 , G06F15/76
CPC分类号： G06F9/3814 , G06F9/24 , G06F9/3802 , G06F9/3879
摘要： A CPU introduces software commands to a first limited capacity memory (e.g. FIFO), on an integrated circuit chip. Data (e.g. graphics) from a first portion of a second memory (off chip) is processed in accordance with such commands. A second portion (e.g. FIFO) of the second memory may also store commands normally passing from the CPU through the first memory. When the first memory becomes full, the commands may pass from the CPU through the second portion of the second memory (which may have a storage capacity considerably greater than that of the first memory) and then through the first memory. The commands may continue to flow in this auxiliary path until the second portion of the second memory becomes empty. A third memory of a limited capacity on the chip may pass the commands from the CPU to the first memory in the normal operation or to the second portion of the second memory when the first memory becomes full. The CPU may also pass commands to other peripheral equipment while a ready line is high. When low, the ready line prevents commands from passing to the peripheral equipment while the third memory is full. However, a command may pass from the third memory to the first or second memory to make the ready line high. A counter indicates the number of commands in the first and third memories and the second portion of the second memory. Software occasionally interrogates the counter to update in the software the number of commands in the counter.
摘要翻译： CPU将集成电路芯片上的软件命令引入第一有限容量存储器（例如FIFO）。根据这样的命令来处理来自第二存储器（离线芯片）的第一部分的数据（例如图形）。第二存储器的第二部分（例如FIFO）也可以存储正常地从CPU通过第一存储器的命令。当第一存储器变满时，命令可以从CPU通过第二存储器的第二部分（其可能具有明显大于第一存储器的存储容量），然后通过第一存储器。这些命令可以在该辅助路径中继续流动，直到第二个存储器的第二部分变空。当第一存储器变满时，芯片上的有限容量的第三存储器可以在正常操作中将命令从CPU传送到第一存储器，或者在第一存储器变满时将其传递到第二存储器的第二部分。当准备好的线路高时，CPU也可以将命令传递给其他外围设备。当为低电平时，就绪线路防止命令在第三个存储器已满时传递到外围设备。然而，命令可以从第三存储器传递到第一或第二存储器，以使就绪行高。计数器指示第一和第三存储器和第二存储器的第二部分中的命令的数量。软件偶尔询问计数器，在软件中更新计数器中的命令数。

4. 发明授权

US5640162A Digital-to-analog converter with binary coded inputs to produce a plurality of outputs in the form of thermometer code 失效
标题翻译：具有二进制编码输入的数模转换器，以温度计代码的形式产生多个输出
公开(公告)号：US5640162A
公开(公告)日：1997-06-17
申请号：US317489
申请日：1994-10-04
申请人： Lanny L. Lewyn
发明人： Lanny L. Lewyn
IPC分类号： H03M1/68 , H03M1/80
CPC分类号： H03M1/687 , H03M1/806
摘要： Binary bits of least binary significance are converted to a corresponding analog output. Binary bits of increased binary significance are converted to a first plurality of thermometer outputs. A plurality of switching assemblies, each preferably recursive and preferably formed from a plurality of switches (e.g. transistors), process individual pairs of successive ones of such thermometer outputs. Each stage respectively produces first or second outputs or the analog output for first, second and third relationships between the thermometer outputs in such pair. The analog output has a variable value between the first and second outputs depending upon the value of the least significant binary bits. When the binary value is represented only by the binary bits of least and increased binary significance, the first, second and analog outputs are combined to produce an analog output representative of such binary bits. When the binary value additionally includes binary bits of even greater binary significance, an additional decoder decodes such binary bits to produce a second plurality of thermometer outputs. Second pluralities of switching assemblies, each plurality preferably having a construction corresponding to that of the first plurality, receive individual pairs of the thermometer outputs in the second plurality and produce the first or second outputs or an individual one of the outputs in the first plurality. These thermometer outputs are combined to produce an analog output representative of all of the binary bits. The second pluralities of switching assemblies comprise a number corresponding to the number of thermometer outputs in the second plurality.
摘要翻译：最小二进制有效性的二进制位被转换为相应的模拟输出。具有增加的二进制有效性的二进制位被转换为第一多个温度计输出。多个开关组件各自优选地递归并且优选地由多个开关（例如晶体管）形成，处理这些温度计输出中相继的单独对。每个阶段分别产生第一或第二输出或模拟输出，用于在这种对中的温度计输出之间的第一，第二和第三关系。根据最低有效二进制位的值，模拟输出在第一和第二输出之间具有可变值。当二进制值仅由具有最小和增加的二进制有效性的二进制位表示时，第一，第二和模拟输出被组合以产生表示这种二进制位的模拟输出。当二进制值另外包括二进制值更大的二进制位时，另外的解码器对这样的二进制位解码以产生第二多个温度计输出。第二多个切换组件优选地具有与第一多个结构相对应的结构，在第二多个中接收单独的温度计输出对，并产生第一或第二输出或第一多个输出中的单个输出。这些温度计输出被组合以产生代表所有二进制位的模拟输出。第二多个切换组件包括对应于第二多个温度计输出的数量的数字。

5. 发明授权

US5631593A Adjustable delay line 失效
标题翻译：可调延时线
公开(公告)号：US5631593A
公开(公告)日：1997-05-20
申请号：US670397
申请日：1996-06-25
申请人： Stuart B. Molin
发明人： Stuart B. Molin
IPC分类号： H03H11/26
CPC分类号： H03H11/265
摘要： A plurality of binary signals each having first and second logic levels respectively representing a binary "1" and a binary "0" and each indicating a binary digit of an individual binary significance cumulatively represent an adjustable delay to be provided by a plurality of delay elements. A first particular number of the binary signals of greatest binary significance are decoded to provide, in a thermometer code, a plurality of signals each having first and second amplitudes. The signals in the thermometer code control the operation of individual switches each having first and second operative relationships to provide respectively for a maximum delay or a minimum delay in an associated one of the delay elements. The binary signals of least binary significance are decoded to produce an analog signal variable between the first and second amplitudes. The analog signal is introduced, in a third operative relationship of an individual one of the switches, to the delay element associated with such switch to provide a delay variable between the minimum and maximum values in accordance with the amplitude of the analog signal. The selection of the individual one of the switches is dependent upon the pattern of the binary signals in the thermometer code, this pattern being a binary 10 in a successive pair of the decoded binary signals. The delay elements may be connected in series to provide a cumulative delay constituting the sum of the delays in the different delay elements and corresponding to the delay indicated by the binary signals.
摘要翻译：分别具有第一和第二逻辑电平的多个二进制信号分别表示二进制“1”和二进制“0”，并且每个二进制信号表示单个二进制显式的二进制数字累积地表示可由多个延迟元件提供的可调延迟。解码具有最大二值含义的二进制信号的第一特定数量，以在温度计代码中提供多个具有第一和第二幅度的信号。温度计代码中的信号控制各自具有第一和第二操作关系的各个开关的操作，以分别提供相关联的一个延迟元件中的最大延迟或最小延迟。对二进制有意义的二进制信号进行解码，以产生在第一和第二振幅之间的模拟信号变量。在开关中的单个开关的第三操作关系中引入模拟信号到与这种开关相关联的延迟元件，以根据模拟信号的幅度在最小值和最大值之间提供延迟变量。开关中的单个开关的选择取决于温度计代码中的二进制信号的模式，该模式是连续的解码二进制信号对中的二进制10。延迟元件可以串联连接以提供构成不同延迟元件中的延迟之和并对应于由二进制信号指示的延迟的累积延迟。

6. 发明授权

US5627885A System for, and method of, transmitting and receiving through telephone lines signals representing data 失效
标题翻译：通过电话线发送和接收表示数据的信号的系统和方法
公开(公告)号：US5627885A
公开(公告)日：1997-05-06
申请号：US195628
申请日：1994-02-14
申请人： Eric Paneth , Mordechai Segal , Boaz Rippin , Ehud H. Rokach
发明人： Eric Paneth , Mordechai Segal , Boaz Rippin , Ehud H. Rokach
IPC分类号： H03H21/00 , H04B3/23 , H04L7/04 , H04L7/06 , H04L7/10 , H04L25/00 , H04L25/03 , H04L25/48 , H04M11/00
CPC分类号： H04L25/00 , H04B3/23 , H04L25/03057 , H04L25/03866 , H04L7/043 , H04L7/06 , H04L7/10
摘要： Analog signals representing individual digital values (.+-.1, .+-.3) pass through a telephone line to a receiver. These signals may be first provided in a pseudo random sequence. A linear echo canceller and a first adder eliminate, to an extent, echo signals resulting from second analog signals transmitted on the same telephone line by the receiver. A non-linear echo canceller and a second adder further reduce the echo signals and specifically reduce non-linear components in the echo signals. Adjustable signal delays achieve optimal performance of the linear and non-linear echo cancellers. An equalizer containing four (4) different modules then compensates for signal distortions introduced by the telephone line and minimizes the effect of noise in the telephone line. The equalizer modules are a digital gain control element, a feed forward digital filter and two (2) feedback digital filters. A detector module produces in one of several different ways at the receiver an estimate of the digital data (.+-.1, .+-.3) transmitted at the other end of the telephone line. The detector either extracts the digital information based on peaks in the received (non-equalized) signal or by adding the equalized signals with preset threshold values. A scrambler-descrambler module locally generates a replica of the digital symbols transmitted in analog form at the other end of the telephone line, based on a limited number (e.g. 23) of correctly detected digital values. The scrambler-descrambler module may also operate as a descrambler to recover data scrambled by the transmitter at the other end.
摘要翻译：表示各个数字值（+/- 1，+/- 3）的模拟信号通过电话线路传送到接收器。这些信号可以首先以伪随机序列提供。线性回波消除器和第一加法器在一定程度上消除由接收器在相同电话线上发送的第二模拟信号产生的回波信号。非线性回波消除器和第二加法器进一步减少回波信号并且具体地减少回波信号中的非线性分量。可调节的信号延迟实现了线性和非线性回波消除器的最佳性能。包含四（4）个不同模块的均衡器然后补偿由电话线引入的信号失真，并最大限度地减少电话线路中噪声的影响。均衡器模块是数字增益控制元件，前馈数字滤波器和两（2）个反馈数字滤波器。检测器模块在接收机处以几种不同的方式之一产生在电话线的另一端传输的数字数据（+/- 1，+/- 3）的估计。检测器根据接收（非均衡）信号中的峰值提取数字信息，或通过将均衡信号与预设阈值相加。扰码解扰器模块基于有限数量（例如23个）正确检测的数字值本地生成在电话线的另一端以模拟形式传输的数字符号的副本。加扰器解扰器模块还可以作为解扰器来操作，以恢复另一端由发射机加扰的数据。

7. 发明授权

US5554950A Delay line providing an adjustable delay in response to binary input signals 失效
标题翻译：延迟线提供响应于二进制输入信号的可调延迟
公开(公告)号：US5554950A
公开(公告)日：1996-09-10
申请号：US382677
申请日：1995-02-02
申请人： Stuart B. Molin
发明人： Stuart B. Molin
IPC分类号： H03H11/26
CPC分类号： H03H11/265
摘要： A plurality of binary signals each having first and second logic levels respectively representing a binary "1" and a binary "0" and each indicating a binary digit of an individual binary significance cumulatively represent an adjustable delay to be provided by a plurality of delay elements. A first particular number of the binary signals of greatest binary significance are decoded to provide, in a thermometer code, a plurality of signals each having first and second amplitudes. The signals in the thermometer code control the operation of individual switches each having first and second operative relationships to provide respectively for a maximum delay or a minimum delay in an associated one of the delay elements. The binary signals of least binary significance are decoded to produce an analog signal variable between the first and second amplitudes. The analog signal is introduced, in a third operative relationship of an individual one of the switches, to the delay element associated with such switch to provide a delay variable between the minimum and maximum values in accordance with the amplitude of the analog signal. The selection of the individual one of the switches is dependent upon the pattern of the binary signals in the thermometer code, this pattern being a binary 10 in a successive pair of the decoded binary signals. The delay elements may be connected in series to provide a cumulative delay constituting the sum of the delays in the different delay elements and corresponding to the delay indicated by the binary signals.
摘要翻译：分别具有第一和第二逻辑电平的多个二进制信号分别表示二进制“1”和二进制“0”，并且每个二进制信号表示单个二进制显式的二进制数字累积地表示可由多个延迟元件提供的可调延迟。解码具有最大二值含义的二进制信号的第一特定数量，以在温度计代码中提供多个具有第一和第二幅度的信号。温度计代码中的信号控制各自具有第一和第二操作关系的各个开关的操作，以分别提供相关联的一个延迟元件中的最大延迟或最小延迟。对二进制有意义的二进制信号进行解码，以产生在第一和第二振幅之间的模拟信号变量。在开关中的单个开关的第三操作关系中引入模拟信号到与这种开关相关联的延迟元件，以根据模拟信号的幅度在最小值和最大值之间提供延迟变量。开关中的单个开关的选择取决于温度计代码中的二进制信号的模式，该模式是连续的解码二进制信号对中的二进制10。延迟元件可以串联连接以提供构成不同延迟元件中的延迟之和并对应于由二进制信号指示的延迟的累积延迟。

8. 发明授权

US5541598A Current cell for converting a binary value to an analog value 失效
标题翻译：用于将二进制值转换为模拟值的当前单元格
公开(公告)号：US5541598A
公开(公告)日：1996-07-30
申请号：US333973
申请日：1994-11-03
申请人： Behnam Malek-Khosravi
发明人： Behnam Malek-Khosravi
IPC分类号： H03M1/74 , H03K17/041 , H03K19/017 , H03K19/0175 , H03K19/0948 , H03M1/08 , H03M1/66
CPC分类号： H03K17/04106 , H03M1/0863 , H03M1/742
摘要： A digital value represented by binary signals is converted to a corresponding analog value by three (3) current cells, preferably C-MOS p-type, in a digital-to-analog converter (DAC). The three (3) transistors, preferably disposed on an integrated circuit chip, comprise (a) an input switch transistor receiving a digital input signal at its gate, (b) an output transistor providing an output current at its drain and (c) a current bias transistor. The switch and output transistor sources and the bias transistor drain are common. The output transistor gate is biased by a substantially constant voltage. The bias transistor source receives a supply voltage through a bonding pad on an integrated circuit chip and a bond wire extending from the pad to a pin on the chip package lead frame. At low frequencies (e.g. 100 MHz), the wave shape of the output transistor drain current is flat. At increased frequencies (e.g. 225 MHz), the output current has a spike from a supply voltage spike induced in the bond wire as a result of different magnitudes in the bias transistor current when the switch transistor responds to binary signals.
摘要翻译：由二进制信号表示的数字值在数模转换器（DAC）中被三（3）个当前单元，最好是C-MOS p型转换成相应的模拟值。优选地设置在集成电路芯片上的三（3）个晶体管包括（a）在其栅极处接收数字输入信号的输入开关晶体管，（b）在其漏极处提供输出电流的输出晶体管，以及（c）电流偏置晶体管。开关和输出晶体管源极和偏置晶体管漏极是常见的。输出晶体管栅极被基本恒定的电压偏置。偏置晶体管源通过集成电路芯片上的接合焊盘和从焊盘延伸到芯片封装引线框架上的引脚的接合线接收电源电压。在低频（例如100MHz）下，输出晶体管漏极电流的波形是平坦的。在增加的频率（例如225MHz）下，当开关晶体管响应二进制信号时，由于偏置晶体管电流的不同幅度，输出电流具有从接合线中引起的电源电压尖峰的尖峰。

9. 发明授权

US5379077A System for and method of, operating upon NTSC and PAL signals 失效
标题翻译：用于NTSC和PAL信号的系统和方法
公开(公告)号：US5379077A
公开(公告)日：1995-01-03
申请号：US164263
申请日：1993-12-09
申请人： Keith A. Jack , Douglas D. Moran , David J. Wicker
发明人： Keith A. Jack , Douglas D. Moran , David J. Wicker
IPC分类号： H04N5/46 , H04N9/65 , H04N11/14 , H04N11/16 , H04N9/64
CPC分类号： H04N9/65 , H04N11/143 , H04N11/162 , H04N5/46
摘要： A system converts PAL and NTSC pixel clock signals to signals (in a studio, digital or square pixel format) at a sub-carrier frequency individual to the PAL and NTSC formats. The system includes a first register for providing a particular increase in the register count upon each occurrence of a pixel clock signal. Any remainder in the first register upon the production of the output signal is introduced to the register upon the occurrence of the next pixel clock signal. The particular increase in the first register count is controlled by a value in a second register, this value being adjustable dependent upon the system format and mode. A sequence of registers may be substituted for the first register with each register receiving an output from the previous register in the sequence. The system also converts signals representing the primary colors to luminance and chrominance signals. The luminance and chrominance signals are processed to produce a control signal having characteristics dependent upon the cumulative intensity of the luminance and chrominance. The control signal is used to vary the amplitude of the chrominance signals so that the chrominance intensity does not increase above or decrease below a problematic level at any instant.
摘要翻译：系统将PAL和NTSC像素时钟信号以个别为PAL和NTSC格式的子载波频率转换成信号（以录音室，数字或正方形像素格式）。该系统包括第一寄存器，用于在每次出现像素时钟信号时提供寄存器计数的特定增加。在产生输出信号时，第一个寄存器中的任何余数在下一个像素时钟信号出现时被引入寄存器。第一寄存器计数的特定增加由第二寄存器中的值控制，该值可根据系统格式和模式进行调整。寄存器序列可以代替第一个寄存器，每个寄存器接收序列中先前寄存器的一个输出。该系统还将表示原色的信号转换为亮度和色度信号。处理亮度和色度信号以产生具有取决于亮度和色度的累积强度的特性的控制信号。控制信号用于改变色度信号的幅度，使得色度强度在任何时刻都不会高于或降低到有问题的水平以下。

10. 发明授权

US5274275A Comparator 失效
标题翻译：比较器
公开(公告)号：US5274275A
公开(公告)日：1993-12-28
申请号：US979803
申请日：1992-11-20
申请人： Joseph H. Colles
发明人： Joseph H. Colles
IPC分类号： H03K3/356 , H03K5/153 , H03K5/24
CPC分类号： H03K3/356034 , H03K3/35613
摘要： A comparator indicates the relative magnitudes of input and reference signals with improved immunity to noise signals. The comparator includes first and second transistors differentially connected to receive the input and reference signals. Third and fourth transistors connected in a latching relationship are responsive in first alternate half cycles of clock signals to the outputs from the first and second transistors to provide a regenerative action on these outputs. In first portions of the first alternate half cycles of the clock signals, a degenerative action is provided by fifth and sixth transistors respectively on the third and fourth transistors to prevent the third and fourth transistors from regenerating until the input difference voltage of these transistors has had time to increase relative to the input noise on these transistors. The fifth and sixth transistors may be provided with sizes corresponding to, or preferably sightly greater than, those of the third and fourth transistors. A seventh transistor connected to the fifth and sixth transistors provides current flow through the fifth and sixth transistors during the second alternative half cycles, and only during the first portion of the first alternate half cycles of the clock signals. An eighth transistor connected to the third and fourth transistors balances the operation of the third, fourth and eighth transistors with the operation of the fifth, sixth and seventh transistors. In the second alternate half cycles of the clock signals, a math transistor clamps the third and fourth transistors to a common voltage level.
摘要翻译：比较器指示输入和参考信号的相对幅度具有改善的对噪声信号的抗扰度。比较器包括差分连接以接收输入和参考信号的第一和第二晶体管。以锁存关系连接的第三和第四晶体管在时钟信号的第一交替半周期中响应于来自第一和第二晶体管的输出，以在这些输出上提供再生动作。在时钟信号的第一交替半周期的第一部分中，分别在第三和第四晶体管上分别由第五和第六晶体管提供退化动作，以防止第三和第四晶体管再生，直到这些晶体管的输入差分电压已经相对于这些晶体管上的输入噪声增加的时间。第五和第六晶体管可以具有与第三晶体管和第四晶体管相对应的尺寸，或者优选地大于第三晶体管和第四晶体管的尺寸。连接到第五和第六晶体管的第七晶体管在第二替代半周期期间提供电流流过第五和第六晶体管，并且仅在时钟信号的第一交替半周期的第一部分期间。连接到第三和第四晶体管的第八晶体管通过第五，第六和第七晶体管的操作来平衡第三，第四和第八晶体管的操作。在时钟信号的第二个半周期中，数学晶体管将第三和第四晶体管钳位到公共电压电平。

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