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1. 发明授权

US07865692B2 Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture 有权
标题翻译：用于自动生成缩写指令集和可配置处理器架构的方法和装置
公开(公告)号：US07865692B2
公开(公告)日：2011-01-04
申请号：US11340072
申请日：2006-01-26
申请人： Sergei Yurievich Larin , Gerald George Pechanek , Thomas M. Conte
发明人： Sergei Yurievich Larin , Gerald George Pechanek , Thomas M. Conte
IPC分类号： G06F12/00
CPC分类号： G06F9/30178 , G06F8/447 , G06F9/30156 , G06F9/30167
摘要： A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application. A hardware embodiment described herein allows application of the above mentioned high-entropy encoding technique in actual embedded processor using today's technology without posing significant strain on timing requirements.
摘要翻译：描述了嵌入式处理器中的指令获取机制和指令集架构的架构和设计的系统方法。这种系统的方法允许放松通常由固定大小的指令集架构（ISA）对嵌入式系统的设计和开发施加的某些限制。该方法还保证可用指令存储器的高效使用，该指令存储器仅由应用程序或其熵的实际信息内容限定。这种效率提高的结果是原始应用的指令段的存储要求或压缩的普遍降低。该系统的另一个特点是ISA与核心架构的完全解耦。这种去耦允许对任何大小的ISA使用可变长度编码，而不会影响物理指令存储器组织或布局和分支机制，以及将执行核心调整到应用程序。本文描述的硬件实施例允许在现有技术的实际嵌入式处理器中应用上述高熵编码技术，而不会对定时要求造成显着的压力。

2. 发明授权

US07836317B2 Methods and apparatus for power control in a scalable array of processor elements 有权
标题翻译：处理器元件可扩展阵列中功率控制的方法和装置
公开(公告)号：US07836317B2
公开(公告)日：2010-11-16
申请号：US12021538
申请日：2008-01-29
申请人： Patrick R. Marchand , Gerald George Pechanek , Edward A. Wolff
发明人： Patrick R. Marchand , Gerald George Pechanek , Edward A. Wolff
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/30036 , G06F9/30079 , G06F9/30083 , G06F9/3012 , G06F9/30141 , G06F9/3853 , G06F9/3885 , Y02D10/128 , Y02D10/171
摘要： Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.
摘要翻译：在可扩展数组间接VLIW处理器中提供低功耗架构特性和技术。这些特征和技术包括可重配置寄存器文件的功率控制，多周期操作的条件功率控制和间接VLIW利用，以及使用ManArray寄存器文件索引机制的基于VLIW的向量处理的功率控制。这些技术适用于所有处理元件（PE）和阵列控制器序列处理器（SP），以提供显着的功率节省。

3. 发明授权

US07631165B2 Processor organized in clusters of processing elements and cluster interconnections by a clustering process 失效
标题翻译：处理器通过集群过程组织在处理元件和集群互连的集群中
公开(公告)号：US07631165B2
公开(公告)日：2009-12-08
申请号：US11682948
申请日：2007-03-07
申请人： Gerald George Pechanek , Charles W. Kurak, Jr.
发明人： Gerald George Pechanek , Charles W. Kurak, Jr.
IPC分类号： G06F15/80
CPC分类号： G06F15/17381 , G06F9/30076 , G06F15/17337 , G06F15/8023
摘要： An array processor includes processing elements (00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 23, 30, 31, 32, 33) arranged in clusters (e.g., 44, 46, 48, 50) to form a rectangular array (40). Inter-cluster communication paths (88) are mutually exclusive. Due to the mutual exclusivity of the data paths, communications between the processing elements of each cluster may be combined in a single inter-cluster path, thus eliminating half the wiring required for the path. The length of the longest communication path is not directly determined by the overall dimension of the array, as in conventional torus arrays. Rather, the longest communications path is limited by the inter-cluster spacing. Transpose elements of an N×N torts may be combined in clusters and communicate with one another through intra-cluster communications paths. Transpose operation latency is eliminated in this approach. Each PE may have a single transmit port (35) and a single receive port (37). Thus, the individual PEs are decoupled from the array topology.
摘要翻译：阵列处理器包括以簇（例如，44,46,48,50）排列的处理元件（00,01,02,03,10,11,12,13,20,21,23,30,31,32,33））以形成矩形阵列（40）。群集间通信路径（88）是互斥的。由于数据路径的相互独占性，每个集群的处理元件之间的通信可以组合在单个集群间路径中，从而消除路径所需的一半接线。最长通信路径的长度不直接取决于阵列的整体尺寸，如在常规环形阵列中。相反，最长的通信路径受群间间隔的限制。 NxN侵权的转置元素可以组合在一起并通过集群内通信路径相互通信。这种方法消除了转置操作延迟。每个PE可以具有单个发送端口（35）和单个接收端口（37）。因此，各个PE与阵列拓扑分离。

4. 发明授权

US1703103A Process for cracking emulsified petroleum oil 失效
标题翻译：乳化石油裂化工艺
公开(公告)号：US1703103A
公开(公告)日：1929-02-26
申请号：US40741120
申请日：1920-09-01
申请人： UNIVERSAL OIL PROD CO
发明人： GUSTAV EGLOFF , BENNER HARRY P
CPC分类号： C10G9/14

5. 发明授权

US07971036B2 Methods and apparatus for attaching application specific functions within an array processor 有权
标题翻译：将应用程序特定功能附加到阵列处理器内的方法和装置
公开(公告)号：US07971036B2
公开(公告)日：2011-06-28
申请号：US11736788
申请日：2007-04-18
申请人： Gerald George Pechanek , Mihailo M. Stojancic
发明人： Gerald George Pechanek , Mihailo M. Stojancic
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F15/80 , G06F9/30036 , G06F9/3824 , G06F9/3828 , G06F9/3851 , G06F9/3877 , G06F9/3885 , G06F9/3891
摘要： A multi-node video signal processor (VSPN) is describes that tightly couples multiple multi-cycle state machines (hardware assist units) to each processor and each memory in each node of an N node scalable array processor. VSPN memory hardware assist instructions are used to initiate multi-cycle state machine functions, to pass parameters to the multi-cycle state machines, to fetch operands from a node's memory, and to control the transfer of results from the multi-cycle state machines.
摘要翻译：描述了一种多节点视频信号处理器（VSPN），它将多个多周期状态机（硬件辅助单元）紧密耦合到N个节点可扩展阵列处理器的每个节点的每个处理器和每个存储器。 VSPN存储器硬件辅助指令用于启动多周期状态机功能，将参数传递到多周期状态机，从节点的存储器获取操作数，并控制多循环状态机的结果传输。

6. 发明授权

US06972593B1 Method and apparatus for protecting a circuit during a hot socket condition 失效
标题翻译：在热插座状态下保护电路的方法和装置
公开(公告)号：US06972593B1
公开(公告)日：2005-12-06
申请号：US10635625
申请日：2003-08-05
申请人： Xiaobao Wang , Khai Nguyen , Chiakang Sung , Bonnie Wang
发明人： Xiaobao Wang , Khai Nguyen , Chiakang Sung , Bonnie Wang
IPC分类号： H03K19/003 , H03K19/094
CPC分类号： H03K19/00315
摘要： The hot socket detect circuit of the present invention includes a well bias circuit and three hot socket detect blocks. If the output of any of the three hot socket detect blocks is a digital high signal then the output of the hot socket detect circuit is a digital high signal. The digital high signal indicates that a hot socket condition exists.
摘要翻译：本发明的热插座检测电路包括阱偏置电路和三个热插座检测块。如果三个热插座检测块中的任一个的输出是数字高信号，则热插座检测电路的输出是数字高电平信号。数字高电平信号表示存在热插座状况。

7. 发明授权

US5656528A Method of forming a dynamic random access memory 失效
标题翻译：形成动态随机存取存储器的方法
公开(公告)号：US5656528A
公开(公告)日：1997-08-12
申请号：US353788
申请日：1994-12-12
申请人： Sven E. Wahlstrom
发明人： Sven E. Wahlstrom
IPC分类号： G11C11/405 , G11C11/4074 , G11C11/4091 , G11C11/4096 , G11C11/4099 , H01L21/70
CPC分类号： G11C11/405 , G11C11/4074 , G11C11/4091 , G11C11/4096 , G11C11/4099
摘要： A dynamic random access memory. The memory includes a write transistor N3 and a read transistor N2. In a preferred embodiment the write transistor has a threshold level higher than the read transistor. A sense amplifier senses and amplifies a difference in voltage between a bit line and a sense node that is developed when the read transistor permits or does-not permit current to flow between ground an a bit line. Associated semiconductor device structures and fabrication techniques are also disclosed.
摘要翻译：动态随机存取存储器。存储器包括写晶体管N3和读晶体管N2。在优选实施例中，写入晶体管具有高于读取晶体管的阈值电平。读出放大器感测并放大当读取晶体管允许或不允许电流在位线之间流过地电位时产生的位线和感测节点之间的电压差。还公开了相关的半导体器件结构和制造技术。

8. 发明授权

US5525827A Unerasable electronic programmable read only memory (UPROM.TM.) 失效
标题翻译：不可擦除的电子可编程只读存储器（UPROM TM）
公开(公告)号：US5525827A
公开(公告)日：1996-06-11
申请号：US148059
申请日：1993-11-05
申请人： Kevin A. Norman
发明人： Kevin A. Norman
IPC分类号： G11C16/04 , G11C16/22 , G11C17/08 , H01L31/0232
CPC分类号： G11C16/0408 , G11C16/22 , G11C17/08
摘要： A shielded electronically programmable read only memory (UPROM.TM.) having memory cells enclosed in a shield structure which protects the content of the memory cells from erasure UV rays is described. In addition to protecting the memory cells, the UPROM provides for accessing the cells from all sides of the shield structure without compromising its protective function. In one embodiment of the present invention, a UPROM having a two dimensional array of EPROM cells is described.
摘要翻译：描述了一种屏蔽电子可编程只读存储器（UPROM TM），其具有封装在屏蔽结构中的存储器单元，其保护存储器单元的内容不被擦除紫外线。除了保护存储器单元之外，UPROM还提供从屏蔽结构的所有侧面访问单元，而不损害其保护功能。在本发明的一个实施例中，描述了具有EPROM单元的二维阵列的UPROM。

9. 再颁专利

USRE41703E1 Methods and apparatus for efficient synchronous MIMD operations with IVLIW PE-TO-PE communication 有权
标题翻译：用于IVLIW PE-TO-PE通信的高效同步MIMD操作的方法和装置
公开(公告)号：USRE41703E1
公开(公告)日：2010-09-14
申请号：US10872995
申请日：2004-06-21
申请人： Gerald George Pechanek , Thomas L. Drabenstott , Juan Guillermo Revilla , David Strube , Grayson Morris
发明人： Gerald George Pechanek , Thomas L. Drabenstott , Juan Guillermo Revilla , David Strube , Grayson Morris
IPC分类号： G06F15/16
CPC分类号： G06F9/30145 , G06F9/30167 , G06F9/3802 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： A SIMD machine employing a plurality of parallel processor (PEs) in which communications hazards are eliminated in an efficient manner. An indirect Very Long Instruction Word instruction memory (VIM) is employed along with execute and delimiter instructions. A masking mechanism may be employed to control which PEs have their VIMs loaded. Further, a receive model of operation is preferably employed. In one aspect, each PE operates to control a switch that selects from which PE it receives. The present invention addresses a better machine organization for execution of parallel algorithms that reduces hardware cost and complexity while maintaining the best characteristics of both SIMD and MIMD machines and minimizing communication latency. This invention brings a level of MIMD computational autonomy to SIMD indirect Very Long Instruction Word (iVLIW) processing elements while maintaining the single thread of control used in the SIMD machine organization. Consequently, the term Synchronous-MIMD (SMIMD) is used to describe the present approach.
摘要翻译：使用多个并行处理器（PE）的SIMD机器，其中以有效的方式消除通信危险。使用间接超长指令字指令存储器（VIM）以及执行和分隔符指令。可以使用掩蔽机制来控制哪些PE装载有VIM。此外，优选采用操作的接收模式。在一个方面，每个PE操作以控制从其接收的PE选择的交换机。本发明解决了用于执行并行算法的更好的机器组织，其降低硬件成本和复杂性，同时保持SIMD和MIMD机器的最佳特性并最小化通信延迟。本发明为SIMD间接超长指令字（iVLIW）处理元件提供了MIMD计算自主性水平，同时保持了SIMD机器组织中使用的单一线程控制。因此，术语Synchronous-MIMD（SMIMD）用于描述当前的方法。

10. 发明授权

US07038305B1 Package for integrated circuit die 失效
标题翻译：集成电路芯片封装
公开(公告)号：US07038305B1
公开(公告)日：2006-05-02
申请号：US10621255
申请日：2003-07-15
申请人： Tan Ping Chet , Allen Cheah Chong Leng
发明人： Tan Ping Chet , Allen Cheah Chong Leng
IPC分类号： H01L23/495 , H01L23/34 , H01L23/48 , H01L23/52 , H01L21/44
CPC分类号： H01L24/49 , H01L23/13 , H01L23/36 , H01L23/49527 , H01L23/49541 , H01L23/49568 , H01L24/45 , H01L24/48 , H01L2224/05554 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48095 , H01L2224/48247 , H01L2224/48253 , H01L2224/4911 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19107 , H01L2924/30105 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： An integrated circuit device package and method of assembling same is disclosed. The device package includes an interposer ring substrate having a hollowed out center mounted on a die attach pad, a die mounted substantially in the center of the die attach pad such that the die is encompassed by the hollowed out center. The package further includes a single-piece drop-in heat sink having a first and second disk shaped portions where the first disk shaped portion has a diameter that is different than the second disk shaped portion.
摘要翻译：公开了一种集成电路器件封装及其组装方法。器件封装包括具有安装在管芯附接焊盘上的中空的中心的插入器环形衬底，基本上安装在管芯附接垫的中心的管芯，使得管芯被中空的中心包围。该封装还包括具有第一和第二盘形部分的单件式散热器，其中第一盘形部分具有与第二盘形部分不同的直径。

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