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1. 发明授权

US09300958B2 Methods and apparatus for motion search refinement in a SIMD array processor 有权
标题翻译： SIMD阵列处理器中运动搜索精细化的方法和装置
公开(公告)号：US09300958B2
公开(公告)日：2016-03-29
申请号：US14187499
申请日：2014-02-24
申请人： Mihailo M. Stojancic , Gerald George Pechanek
发明人： Mihailo M. Stojancic , Gerald George Pechanek
IPC分类号： H04N7/12 , H04N19/433 , H04N19/61 , H04N19/186 , H04N19/43 , H04N19/436 , H04N19/523 , H04N19/57
CPC分类号： H04N19/433 , H04N19/186 , H04N19/43 , H04N19/436 , H04N19/523 , H04N19/57 , H04N19/61
摘要： Various approaches for motion search refinement in a processing element are discussed. A k/2+L+k/2 register stores an expanded row of an L×L macro block. A k-tap filter horizontally interpolates over the expanded row generating horizontal interpolation results. A transpose storage unit stores the interpolated results generated by the k-tap filter for k/2+L+k/2 entries, wherein rows or columns of data may be read out of the transpose storage unit in pipelined register stages. A k-tap filter vertically interpolates over the pipelined register stages generating vertical interpolation results.
摘要翻译：讨论了处理元件中运动搜索细化的各种方法。 A k / 2 + L + k / 2寄存器存储L×L宏块的扩展行。 k抽头滤波器在扩展的行上水平内插，产生水平插值结果。转置存储单元存储由k抽头滤波器为k / 2 + L + k / 2个条目生成的内插结果，其中数据行或列可以在流水线寄存器级中从转置存储单元中读出。 k抽头滤波器垂直内插在流水线寄存器级上，产生垂直插值结果。

2. 发明授权

US09060169B2 Methods and apparatus for providing a scalable deblocking filtering assist function within an array processor 有权
标题翻译：用于在阵列处理器内提供可扩展去块滤波辅助功能的方法和装置
公开(公告)号：US09060169B2
公开(公告)日：2015-06-16
申请号：US14011835
申请日：2013-08-28
申请人： Mihailo M. Stojancic , Gerald George Pechanek
发明人： Mihailo M. Stojancic , Gerald George Pechanek
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04 , H04N19/80 , H04N19/42 , H04N19/436 , H04N19/59
CPC分类号： H04N19/80 , H04N19/42 , H04N19/436 , H04N19/59
摘要： Apparatus and methods for scalable block pixel filtering are described. A block filtering instruction is issued to a processing element (PE) to initiate block pixel filtering hardware by causing at least one command and at least one parameter be sent to a command and control function associated with the PE. A block of pixels is fetched from a PE local memory to be stored in a register file of a hardware assist module. A sub-block of pixels is processed to generate sub-block parameters and the block of pixels is filtered in a horizontal/vertical edge filtering computation pipeline using the sub-block parameters.
摘要翻译：描述了可扩展块像素滤波的装置和方法。通过使至少一个命令和至少一个参数发送到与PE相关联的命令和控制功能，向处理元件（PE）发出块过滤指令以发起块像素过滤硬件。从PE本地存储器中取出一块像素以存储在硬件辅助模块的寄存器文件中。处理像素的子块以产生子块参数，并且使用子块参数在水平/垂直边缘滤波计算流水线中对像素块进行滤波。

3. 发明申请

US20140314152A1 Methods And Apparatus For Motion Search Refinement In A SIMD Array Processor 审中-公开
标题翻译：用于SIMD阵列处理器中运动搜索优化的方法和装置
公开(公告)号：US20140314152A1
公开(公告)日：2014-10-23
申请号：US14187499
申请日：2014-02-24
申请人： Mihailo M. Stojancic , Gerald George Pechanek
发明人： Mihailo M. Stojancic , Gerald George Pechanek
IPC分类号： H04N19/433 , H04N19/57
CPC分类号： H04N19/433 , H04N19/186 , H04N19/43 , H04N19/436 , H04N19/523 , H04N19/57 , H04N19/61
摘要： Various approaches for motion search refinement in a processing element are discussed. A k/2+L+k/2 register stores an expanded row of an L×L macro block. A k-tap filter horizontally interpolates over the expanded row generating horizontal interpolation results. A transpose storage unit stores the interpolated results generated by the k-tap filter for k/2+L+k/2 entries, wherein rows or columns of data may be read out of the transpose storage unit in pipelined register stages. A k-tap filter vertically interpolates over the pipelined register stages generating vertical interpolation results.
摘要翻译：讨论了处理元件中运动搜索细化的各种方法。 A k / 2 + L + k / 2寄存器存储L×L宏块的扩展行。 k抽头滤波器在扩展的行上水平内插，产生水平插值结果。转置存储单元存储由k抽头滤波器为k / 2 + L + k / 2个条目生成的内插结果，其中数据行或列可以在流水线寄存器级中从转置存储单元中读出。 k抽头滤波器垂直内插在流水线寄存器级上，产生垂直插值结果。

4. 发明授权

US08208553B2 Methods and apparatus for quarter-pel refinement in a SIMD array processor 有权
标题翻译： SIMD阵列处理器中四分之一像素细化的方法和装置
公开(公告)号：US08208553B2
公开(公告)日：2012-06-26
申请号：US11736849
申请日：2007-04-18
申请人： Mihailo M. Stojancic , Gerald George Pechanek
发明人： Mihailo M. Stojancic , Gerald George Pechanek
IPC分类号： H04N7/26
CPC分类号： H04N19/523 , H04N19/43 , H04N19/436
摘要： An apparatus and a method for quarter-pel motion compensated search are described in the context of an array processor with tightly coupled, multi-cycle hardware assist attached to each node. A quarter-pel motion compensated search (QPMCS) instruction initiates the quarter-pel motion compensated search pipeline operation. An instruction decode and instruction operation control unit generates a starting address for a 4×4 block of a current macro block search operation indicating where to fetch the pel values. An interpolation unit determines at least eight neighboring quarter-pels per pipeline stage based on the 4×4 block of pel values. An absolute value of difference function computes the absolute value of difference values between a current macro block pel and the at least eight neighboring quarter-pels per pipeline stage. An accumulator accumulates at least eight summation values for the 4×4 block at quarter-pel positions per pipeline stage.
摘要翻译：在具有连接到每个节点的紧密耦合的多周期硬件辅助的阵列处理器的上下文中描述了用于四分之一像素运动补偿搜索的装置和方法。四分之一像素运动补偿搜索（QPMCS）指令启动四分之一像素运动补偿搜索管道操作。指令解码和指令操作控制单元产生指示在哪里获取像素值的当前宏块搜索操作的4×4块的起始地址。内插单元基于像素值的4×4块来确定每个流水线阶段的至少八个相邻四分之一像素。差分函数的绝对值计算当前宏块和每个流水线阶段至少八个相邻四分之一像素之间的差值的绝对值。累加器在每个流水线阶段的四分之一像素位置累积至少八个累加值，用于4×4块。

5. 发明申请

US20110153998A1 Methods and Apparatus for Attaching Application Specific Functions Within an Array Processor 有权
标题翻译：在阵列处理器中附加应用程序特定功能的方法和装置
公开(公告)号：US20110153998A1
公开(公告)日：2011-06-23
申请号：US13037824
申请日：2011-03-01
申请人： Gerald George Pechanek , Mihailo M. Stojancic
发明人： Gerald George Pechanek , Mihailo M. Stojancic
IPC分类号： G06F9/30
CPC分类号： G06F15/80 , G06F9/30036 , G06F9/3824 , G06F9/3828 , G06F9/3851 , G06F9/3877 , G06F9/3885 , G06F9/3891
摘要： A multi-node video signal processor (VSPN) is describes that tightly couples multiple multi-cycle state machines (hardware assist units) to each processor and each memory in each node of an N node scalable array processor. VSPN memory hardware assist instructions are used to initiate multi-cycle state machine functions, to pass parameters to the multi-cycle state machines, to fetch operands from a node's memory, and to control the transfer of results from the multi-cycle state machines.
摘要翻译：描述了一种多节点视频信号处理器（VSPN），它将多个多周期状态机（硬件辅助单元）紧密耦合到N个节点可扩展阵列处理器的每个节点的每个处理器和每个存储器。 VSPN存储器硬件辅助指令用于启动多周期状态机功能，将参数传递到多周期状态机，从节点的存储器获取操作数，并控制多循环状态机的结果传输。

6. 发明授权

US08693548B2 Methods and apparatus for motion search refinement in a SIMD array processor 失效
标题翻译： SIMD阵列处理器中运动搜索精细化的方法和装置
公开(公告)号：US08693548B2
公开(公告)日：2014-04-08
申请号：US13747925
申请日：2013-01-23
申请人： Mihailo M. Stojancic , Gerald George Pechanek
发明人： Mihailo M. Stojancic , Gerald George Pechanek
IPC分类号： H04N7/12
CPC分类号： H04N19/433 , H04N19/186 , H04N19/43 , H04N19/436 , H04N19/523 , H04N19/57 , H04N19/61
摘要： Various approaches for motion search refinement in a processing element are discussed. A k/2+L+k/2 register stores an expanded row of an L×L macro block. A k-tap filter horizontally interpolates over the expanded row generating horizontal interpolation results. A transpose storage unit stores the interpolated results generated by the k-tap filter for k/2+L+k/2 entries, wherein rows or columns of data may be read out of the transpose storage unit in pipelined register stages. A k-tap filter vertically interpolates over the pipelined register stages generating vertical interpolation results.
摘要翻译：讨论了处理元件中运动搜索细化的各种方法。 A k / 2 + L + k / 2寄存器存储L×L宏块的扩展行。 k抽头滤波器在扩展的行上水平内插，产生水平插值结果。转置存储单元存储由k抽头滤波器为k / 2 + L + k / 2个条目生成的内插结果，其中数据行或列可以在流水线寄存器级中从转置存储单元中读出。 k抽头滤波器垂直内插在流水线寄存器级上，产生垂直插值结果。

7. 发明申请

US20130283007A1 Methods and Apparatus For Attaching Application Specific Functions Within An Array Processor 审中-公开
标题翻译：用于在阵列处理器中附加应用程序特定功能的方法和装置
公开(公告)号：US20130283007A1
公开(公告)日：2013-10-24
申请号：US13914687
申请日：2013-06-11
申请人： Gerald George Pechanek , Mihailo M. Stojancic
发明人： Gerald George Pechanek , Mihailo M. Stojancic
IPC分类号： G06F15/80
CPC分类号： G06F15/80 , G06F9/30036 , G06F9/3824 , G06F9/3828 , G06F9/3851 , G06F9/3877 , G06F9/3885 , G06F9/3891
摘要： A multi-node video signal processor (VSPN) is describes that tightly couples multiple multi-cycle state machines (hardware assist units) to each processor and each memory in each node of an N node scalable array processor. VSPN memory hardware assist instructions are used to initiate multi-cycle state machine functions, to pass parameters to the multi-cycle state machines, to fetch operands from a node's memory, and to control the transfer of results from the multi-cycle state machines.
摘要翻译：描述了一种多节点视频信号处理器（VSPN），它将多个多周期状态机（硬件辅助单元）紧密耦合到N个节点可扩展阵列处理器的每个节点的每个处理器和每个存储器。 VSPN存储器硬件辅助指令用于启动多周期状态机功能，将参数传递到多周期状态机，从节点的存储器获取操作数，并控制多循环状态机的结果传输。

8. 发明申请

US20130182771A1 Methods And Apparatus For Motion Search Refinement In A SIMD Array Processor 失效
标题翻译：用于SIMD阵列处理器中运动搜索优化的方法和装置
公开(公告)号：US20130182771A1
公开(公告)日：2013-07-18
申请号：US13747925
申请日：2013-01-23
申请人： Mihailo M. Stojancic , Gerald George Pechanek
发明人： Mihailo M. Stojancic , Gerald George Pechanek
IPC分类号： H04N7/26
CPC分类号： H04N19/433 , H04N19/186 , H04N19/43 , H04N19/436 , H04N19/523 , H04N19/57 , H04N19/61
摘要： Various approaches for motion search refinement in a processing element are discussed. A k/2+L+k/2 register stores an expanded row of an L×L macro block. A k-tap filter horizontally interpolates over the expanded row generating horizontal interpolation results. A transpose storage unit stores the interpolated results generated by the k-tap filter for k/2+L+k/2 entries, wherein rows or columns of data may be read out of the transpose storage unit in pipelined register stages. A k-tap filter vertically interpolates over the pipelined register stages generating vertical interpolation results.
摘要翻译：讨论了处理元件中运动搜索细化的各种方法。 A k / 2 + L + k / 2寄存器存储L×L宏块的扩展行。 k抽头滤波器在扩展的行上水平内插，产生水平插值结果。转置存储单元存储由k抽头滤波器为k / 2 + L + k / 2个条目生成的内插结果，其中数据行或列可以在流水线寄存器级中从转置存储单元中读出。 k抽头滤波器垂直内插在流水线寄存器级上，产生垂直插值结果。

9. 发明授权

US08358695B2 Methods and apparatus for providing a scalable motion estimation/compensation assist function within an array processor 有权
标题翻译：用于在阵列处理器内提供可伸缩的运动估计/补偿辅助功能的方法和装置
公开(公告)号：US08358695B2
公开(公告)日：2013-01-22
申请号：US11736837
申请日：2007-04-18
申请人： Mihailo M. Stojancic , Gerald George Pechanek
发明人： Mihailo M. Stojancic , Gerald George Pechanek
IPC分类号： H04N7/12 , H04N11/02 , H04N5/14 , G06K9/00 , G06K9/36 , G06F15/00 , H04N7/26 , H04N7/36 , G06T7/00 , G06T7/20
CPC分类号： G06F15/8053 , G09G5/363 , G09G5/393 , G09G2320/106 , G09G2340/02 , G09G2350/00 , G09G2360/06 , H04N19/433 , H04N19/436
摘要： An apparatus is described for attaching a motion search hardware assist unit to a processing element and its local memory. A current macro block storage unit is attached to a local memory interface unit for storage of a copy of a current macro block from the local memory. A search window reference storage unit having N rows is attached to a local memory interface unit for storage of a copy of N rows of pixels from a search window from the local memory. N independent arithmetic pipelines are attached to the current macro block storage unit and the search window reference storage. Each pipeline operates on one of the N rows of the search window reference storage unit and a corresponding row of the current macro block of the current macro block storage unit. An accumulator is attached to the N independent pipelines to accumulate results from the N arithmetic pipelines, to produce independent results for different organizations of macro blocks.
摘要翻译：描述了一种用于将运动搜索硬件辅助单元附加到处理元件及其本地存储器的装置。当前宏块存储单元附接到本地存储器接口单元，用于从本地存储器存储当前宏块的副本。具有N行的搜索窗口参考存储单元附加到本地存储器接口单元，用于从本地存储器从搜索窗口存储N行像素的副本。 N个独立的算术流水线附加到当前宏块存储单元和搜索窗口参考存储器。每个流水线在搜索窗口参考存储单元的N行之一和当前宏块存储单元的当前宏块的对应行中操作。累加器连接到N个独立的管线，以累积N个算术流水线的结果，为不同的宏块组织产生独立的结果。

10. 发明申请

US20080037650A1 Methods and Apparatus For Providing A Scalable Deblocking Filtering Assist Function Within An Array Processor 有权
标题翻译：用于在阵列处理器内提供可扩展去块滤波辅助功能的方法和装置
公开(公告)号：US20080037650A1
公开(公告)日：2008-02-14
申请号：US11737175
申请日：2007-04-19
申请人： Mihailo M. Stojancic , Gerald George Pechanek
发明人： Mihailo M. Stojancic , Gerald George Pechanek
IPC分类号： H04N11/04 , H04B1/66
CPC分类号： H04N19/80 , H04N19/42 , H04N19/436 , H04N19/59
摘要： Apparatus and methods for scalable block pixel filtering are described. A block filtering instruction is issued to a processing element (PE) to initiate block pixel filtering hardware by causing at least one command and at least one parameter be sent to a command and control function associated with the PE. A block of pixels is fetched from a PE local memory to be stored in a register file of a hardware assist module. A sub-block of pixels is processed to generate sub-block parameters and the block of pixels is filtered in a horizontal/vertical edge filtering computation pipeline using the sub-block parameters.
摘要翻译：描述了可扩展块像素滤波的装置和方法。通过使至少一个命令和至少一个参数发送到与PE相关联的命令和控制功能，向处理元件（PE）发出块过滤指令以发起块像素过滤硬件。从PE本地存储器中取出一块像素以存储在硬件辅助模块的寄存器文件中。处理像素的子块以产生子块参数，并且使用子块参数在水平/垂直边缘滤波计算流水线中对像素块进行滤波。

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