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1. 发明授权

US08957398B2 Via-configurable high-performance logic block involving transistor chains 有权
标题翻译：通过可配置的高性能逻辑块涉及晶体管链
公开(公告)号：US08957398B2
公开(公告)日：2015-02-17
申请号：US13649510
申请日：2012-10-11
申请人： eASIC Corporation
发明人： Alexander Andreev , Sergey Gribok , Ranko L. Scepanovic , Phey-Chuin Tan , Chee-Wei Kung
IPC分类号： H01L27/08 , H01L47/00 , H03K19/0948 , G06F17/50 , H03K19/177
CPC分类号： H03K19/0948 , G06F17/505 , H03K19/17728 , H03K19/17796
摘要： A via-configurable logic block architecture for a Structured ASIC has a plurality of MOSFET transistor chains connected to one another through vias. In one embodiment there are three chains and the first transistor chain is a NFET transistor chain, the second transistor chain is a PFET transistor chain, and the third transistor chain is a NFET transistor chain. The first, second and third transistor chains are formed into devices made of transistors that are selected from a voltage threshold group consisting of LVT, SVT and HVT devices, where the first and third transistor chains are formed into devices from a voltage threshold group that is different from one another. In another embodiment transistor drive strength may be varied in the transistor chains of the logic block. In yet another embodiment both voltage threshold and drive strength may be varied together in a symmetrical manner.
摘要翻译：用于结构化ASIC的通孔可配置逻辑块架构具有通过通孔彼此连接的多个MOSFET晶体管链。在一个实施例中，存在三条链，第一晶体管链是NFET晶体管链，第二晶体管链是PFET晶体管链，第三晶体管链是NFET晶体管链。第一，第二和第三晶体管链形成为由从由LVT，SVT和HVT器件组成的电压阈值组中选择的晶体管制成的器件，其中第一和第三晶体管链由电压阈值组形成器件，彼此不同在另一个实施例中，晶体管驱动强度可以在逻辑块的晶体管链中变化。在另一个实施例中，电压阈值和驱动强度可以以对称的方式一起变化。

2. 发明授权

US09024657B2 Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller 有权
标题翻译：在28 NM CMOS工艺光刻节点上制造的结构化ASIC的建筑平面图
公开(公告)号：US09024657B2
公开(公告)日：2015-05-05
申请号：US13649529
申请日：2012-10-11
申请人： eASIC Corporation
发明人： Alexander Andreev , Ranko L. Scepanovic , Ivan Pavisic , Alexander Yahontov , Mikhail Udovikhin , Igor Vikhliantsev , Chong-Teik Lim , Seow-Sung Lee , Chee-Wei Kung
IPC分类号： H03K19/177 , H03K19/0185 , G06F17/50
CPC分类号： H03K19/018585 , G06F17/505 , H01L2924/0002 , H01L2924/00
摘要： A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer.
摘要翻译：结构化ASIC芯片的平面图示出具有包含存储器的核心区域和由多个IO连接结构包围的VCLB逻辑单元，所述IO连接结构包括第一IO连接结构，该第一IO连接结构包括将芯片的核心连接到用于外部信号的引脚核心是沿着核心的东西垂直顶部布置的第一个高速布线布线，并将核心连接到诸如SerDes之类的高速IO; 网络感知连接架构将核心连接到微控制器，主要用于测试和修复内核中的内存; 并且第二高速布线布置在核心的南北垂直侧并与IO子库通信。 VCLB结构化ASIC芯片在28nm CMOS工艺光刻节点上制造，具有多个金属层，并且优选地在单个通孔层上编程。

3. 发明申请

US20140103959A1 Architectural Floorplan for a Structured ASIC Manufactured on a 28 NM CMOS Process Lithographic Node or Smaller 有权
标题翻译：在28 NM CMOS工艺光刻节点或更小的制造结构化ASIC的建筑平面布置图
公开(公告)号：US20140103959A1
公开(公告)日：2014-04-17
申请号：US13649529
申请日：2012-10-11
申请人： eASIC Corporation
发明人： Alexander Andreev , Ranko L. Scepanovic , Ivan Pavisic , Alexander Yahontov , Mikhail Udovikhin , Igor Vikhliantsev , Chong-Teik Lim , Seow-Sung Lee , Chee-Wei Kung
IPC分类号： H03K19/0185 , G06F17/50
CPC分类号： H03K19/018585 , G06F17/505 , H01L2924/0002 , H01L2924/00
摘要： A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer.
摘要翻译：结构化ASIC芯片的平面图示出具有包含存储器的核心区域和由多个IO连接结构包围的VCLB逻辑单元，所述IO连接结构包括第一IO连接结构，该第一IO连接结构包括将芯片的核心连接到用于外部信号的引脚核心是沿着核心的东西垂直顶部布置的第一个高速布线布线，并将核心连接到诸如SerDes之类的高速IO; 网络感知连接架构将核心连接到微控制器，主要用于测试和修复内核中的内存; 并且第二高速布线布置在核心的南北垂直侧并与IO子库通信。 VCLB结构化ASIC芯片在28nm CMOS工艺光刻节点上制造，具有多个金属层，并且优选地在单个通孔层上编程。

4. 发明申请

US20140028348A1 Via-Configurable High-Performance Logic Block Involving Transistor Chains 有权
标题翻译：通过可配置的高性能逻辑块涉及晶体管链
公开(公告)号：US20140028348A1
公开(公告)日：2014-01-30
申请号：US13649510
申请日：2012-10-11
申请人： EASIC CORPORATION
发明人： Alexander Andreev , Sergey Gribok , Ranko L. Scepanovic , Phey-Chuin Tan , Chee-Wei Kung
IPC分类号： H03K19/0948 , G06F17/50
CPC分类号： H03K19/0948 , G06F17/505 , H03K19/17728 , H03K19/17796
摘要： A via-configurable logic block architecture for a Structured ASIC has a plurality of MOSFET transistor chains connected to one another through vias. In one embodiment there are three chains and the first transistor chain is a NFET transistor chain, the second transistor chain is a PFET transistor chain, and the third transistor chain is a NFET transistor chain. The first, second and third transistor chains are formed into devices made of transistors that are selected from a voltage threshold group consisting of LVT, SVT and HVT devices, where the first and third transistor chains are formed into devices from a voltage threshold group that is different from one another. In another embodiment transistor drive strength may be varied in the transistor chains of the logic block. In yet another embodiment both voltage threshold and drive strength may be varied together in a symmetrical manner.
摘要翻译：用于结构化ASIC的通孔可配置逻辑块架构具有通过通孔彼此连接的多个MOSFET晶体管链。在一个实施例中，存在三条链，第一晶体管链是NFET晶体管链，第二晶体管链是PFET晶体管链，第三晶体管链是NFET晶体管链。第一，第二和第三晶体管链形成为由从由LVT，SVT和HVT器件组成的电压阈值组中选择的晶体管制成的器件，其中第一和第三晶体管链由电压阈值组形成器件，彼此不同在另一个实施例中，晶体管驱动强度可以在逻辑块的晶体管链中变化。在另一个实施例中，电压阈值和驱动强度可以以对称的方式一起变化。

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