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1. 发明申请

US20140103985A1 Digitally Controlled Delay Line for a Structured ASIC Having a Via Configurable Fabric for High-Speed Interface 审中-公开
标题翻译：具有用于高速接口的通过可配置结构的结构化ASIC的数字控制延迟线
公开(公告)号：US20140103985A1
公开(公告)日：2014-04-17
申请号：US13649584
申请日：2012-10-11
申请人： eASIC Corporation
发明人： Alexander Andreev , Sergey Gribok , Marian Serban , Massimo Verita , Kee-Wei Sim , Kok-Hin Lew
IPC分类号： H03H17/00
CPC分类号： H03H17/0009 , H03H11/265 , H03K5/131 , H03K2005/00065
摘要： A Digitally Controlled Delay Line (DCDL) for a Structured ASIC chip is used to delaying input or output signals into or out of core logic in a Structured ASIC. The DCDL has a multi-stage configuration that in a preferred embodiment comprises two fine delay stages for fine tuning the delay using sub-gate delay through an inverter whose delay can be adjusted with parallel CMOS transistors whose gates are biased with a voltage control signal that is thermometer coded. The fine-tune stages are followed by coarse delay stages that use gate-level delay. A DCDL controller outputs control signals that are Grey coded and converted to thermometer coded control signals by a Binary-to-Thermometer Decoder. The DCDL circuit block and accompanying Structured ASIC are manufactured on a 28 nm CMOS process lithographic node or smaller. A high speed routing fabric using a balanced binary tree is employed with the DCDL.
摘要翻译：用于结构化ASIC芯片的数字控制延迟线（DCDL）用于将结构化ASIC中的输入或输出信号延迟或退出核心逻辑。 DCDL具有多级配置，在优选实施例中，包括两个精细延迟级，用于使用子门延迟微调微调延迟，该逆变器的延迟可以用其栅极被电压控制信号偏置的并行CMOS晶体管来调节，是温度计编码。微调阶段之后是使用门级延迟的粗略延迟阶段。 DCDL控制器输出灰度编码的控制信号，并通过二进制到温度计解码器转换为温度计编码的控制信号。 DCDL电路块和附带的结构化ASIC是在28nm CMOS工艺光刻节点上制造的。 DCDL采用使用平衡二叉树的高速路由选择。

2. 发明授权

US08957398B2 Via-configurable high-performance logic block involving transistor chains 有权
标题翻译：通过可配置的高性能逻辑块涉及晶体管链
公开(公告)号：US08957398B2
公开(公告)日：2015-02-17
申请号：US13649510
申请日：2012-10-11
申请人： eASIC Corporation
发明人： Alexander Andreev , Sergey Gribok , Ranko L. Scepanovic , Phey-Chuin Tan , Chee-Wei Kung
IPC分类号： H01L27/08 , H01L47/00 , H03K19/0948 , G06F17/50 , H03K19/177
CPC分类号： H03K19/0948 , G06F17/505 , H03K19/17728 , H03K19/17796
摘要： A via-configurable logic block architecture for a Structured ASIC has a plurality of MOSFET transistor chains connected to one another through vias. In one embodiment there are three chains and the first transistor chain is a NFET transistor chain, the second transistor chain is a PFET transistor chain, and the third transistor chain is a NFET transistor chain. The first, second and third transistor chains are formed into devices made of transistors that are selected from a voltage threshold group consisting of LVT, SVT and HVT devices, where the first and third transistor chains are formed into devices from a voltage threshold group that is different from one another. In another embodiment transistor drive strength may be varied in the transistor chains of the logic block. In yet another embodiment both voltage threshold and drive strength may be varied together in a symmetrical manner.
摘要翻译：用于结构化ASIC的通孔可配置逻辑块架构具有通过通孔彼此连接的多个MOSFET晶体管链。在一个实施例中，存在三条链，第一晶体管链是NFET晶体管链，第二晶体管链是PFET晶体管链，第三晶体管链是NFET晶体管链。第一，第二和第三晶体管链形成为由从由LVT，SVT和HVT器件组成的电压阈值组中选择的晶体管制成的器件，其中第一和第三晶体管链由电压阈值组形成器件，彼此不同在另一个实施例中，晶体管驱动强度可以在逻辑块的晶体管链中变化。在另一个实施例中，电压阈值和驱动强度可以以对称的方式一起变化。

3. 发明申请

US20140028348A1 Via-Configurable High-Performance Logic Block Involving Transistor Chains 有权
标题翻译：通过可配置的高性能逻辑块涉及晶体管链
公开(公告)号：US20140028348A1
公开(公告)日：2014-01-30
申请号：US13649510
申请日：2012-10-11
申请人： EASIC CORPORATION
发明人： Alexander Andreev , Sergey Gribok , Ranko L. Scepanovic , Phey-Chuin Tan , Chee-Wei Kung
IPC分类号： H03K19/0948 , G06F17/50
CPC分类号： H03K19/0948 , G06F17/505 , H03K19/17728 , H03K19/17796
摘要： A via-configurable logic block architecture for a Structured ASIC has a plurality of MOSFET transistor chains connected to one another through vias. In one embodiment there are three chains and the first transistor chain is a NFET transistor chain, the second transistor chain is a PFET transistor chain, and the third transistor chain is a NFET transistor chain. The first, second and third transistor chains are formed into devices made of transistors that are selected from a voltage threshold group consisting of LVT, SVT and HVT devices, where the first and third transistor chains are formed into devices from a voltage threshold group that is different from one another. In another embodiment transistor drive strength may be varied in the transistor chains of the logic block. In yet another embodiment both voltage threshold and drive strength may be varied together in a symmetrical manner.
摘要翻译：用于结构化ASIC的通孔可配置逻辑块架构具有通过通孔彼此连接的多个MOSFET晶体管链。在一个实施例中，存在三条链，第一晶体管链是NFET晶体管链，第二晶体管链是PFET晶体管链，第三晶体管链是NFET晶体管链。第一，第二和第三晶体管链形成为由从由LVT，SVT和HVT器件组成的电压阈值组中选择的晶体管制成的器件，其中第一和第三晶体管链由电压阈值组形成器件，彼此不同在另一个实施例中，晶体管驱动强度可以在逻辑块的晶体管链中变化。在另一个实施例中，电压阈值和驱动强度可以以对称的方式一起变化。

4. 发明授权

US08629548B1 Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic node 有权
标题翻译：用于在28 NM CMOS工艺光刻节点上制造的结构化ASIC的时钟网络鱼骨架构
公开(公告)号：US08629548B1
公开(公告)日：2014-01-14
申请号：US13649547
申请日：2012-10-11
申请人： eASIC Corporation
发明人： Alexander Andreev , Andrey Nikishin , Sergey Gribok , Phey-Chuin Tan , Choon-Hun Choo
IPC分类号： H01L23/52
CPC分类号： G06F1/10 , H01L2924/0002 , H03K19/0013 , H03K19/0016 , H01L2924/00
摘要： A clock architecture for a Structured ASIC chip, manufactured using a CMOS process is shown. A via-configurable logic block (VCLB) architecture in the Structured ASIC has a core region containing memory and logic cells arranged in columns that are supplied by a clock network having a global clock network tree and a low-level clock mesh to distribute the global clock signal in a repeating pattern. The clock mesh has a fishbone configuration in outline and allows for scalable expansion of the clock network. In one embodiment 36 global clocks may be provided to the Structured ASIC, with four clocks per logic cell. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node, having several metal layers but preferably is programmable on a single via layer.
摘要翻译：显示了使用CMOS工艺制造的结构化ASIC芯片的时钟架构。结构化ASIC中的通孔可配置逻辑块（VCLB）架构具有核心区域，其包含以列形式布置的存储器和逻辑单元，列由具有全局时钟网络树和低级时钟网格的时钟网络提供，以分布全局时钟信号。时钟网格具有鱼骨配置，允许时钟网络的可扩展扩展。在一个实施例中，可以向结构化ASIC提供36个全局时钟，每个逻辑单元具有四个时钟。 VCLB结构化ASIC芯片在28nm CMOS工艺光刻节点上制造，具有多个金属层，但优选在单个通孔层上可编程。

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