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1. 发明申请

US20140105246A1 Temperature Controlled Structured ASIC Manufactured on a 28 NM CMOS Process Lithographic Node 审中-公开
标题翻译：在28 NM CMOS工艺光刻节点上制造的温度控制结构ASIC
公开(公告)号：US20140105246A1
公开(公告)日：2014-04-17
申请号：US13649563
申请日：2012-10-11
申请人： eASIC Corporation
发明人： Alexander Andreev , Massimo Verita
IPC分类号： G01K7/01
CPC分类号： G01K7/01 , G01K13/00 , G05D23/1919 , G06F1/206
摘要： A temperature control for a Structured ASIC chip, manufactured using a CMOS process is shown. A circuit employing temperature feedback using a microprocessor and active heating elements, that in a preferred embodiment uses decoupling cell capacitors, is employed to actively heat a die when the temperature of the die drops below a predetermined minimum temperature, in order to achieve timing closure in the chip.
摘要翻译：示出了使用CMOS工艺制造的结构化ASIC芯片的温度控制。采用微处理器和主动加热元件的温度反馈的电路，在优选实施例中使用去耦电容器，当芯片的温度下降到预定的最低温度以下时，主动加热芯片，以便实现定时闭合芯片。

2. 发明申请

US20140103985A1 Digitally Controlled Delay Line for a Structured ASIC Having a Via Configurable Fabric for High-Speed Interface 审中-公开
标题翻译：具有用于高速接口的通过可配置结构的结构化ASIC的数字控制延迟线
公开(公告)号：US20140103985A1
公开(公告)日：2014-04-17
申请号：US13649584
申请日：2012-10-11
申请人： eASIC Corporation
发明人： Alexander Andreev , Sergey Gribok , Marian Serban , Massimo Verita , Kee-Wei Sim , Kok-Hin Lew
IPC分类号： H03H17/00
CPC分类号： H03H17/0009 , H03H11/265 , H03K5/131 , H03K2005/00065
摘要： A Digitally Controlled Delay Line (DCDL) for a Structured ASIC chip is used to delaying input or output signals into or out of core logic in a Structured ASIC. The DCDL has a multi-stage configuration that in a preferred embodiment comprises two fine delay stages for fine tuning the delay using sub-gate delay through an inverter whose delay can be adjusted with parallel CMOS transistors whose gates are biased with a voltage control signal that is thermometer coded. The fine-tune stages are followed by coarse delay stages that use gate-level delay. A DCDL controller outputs control signals that are Grey coded and converted to thermometer coded control signals by a Binary-to-Thermometer Decoder. The DCDL circuit block and accompanying Structured ASIC are manufactured on a 28 nm CMOS process lithographic node or smaller. A high speed routing fabric using a balanced binary tree is employed with the DCDL.
摘要翻译：用于结构化ASIC芯片的数字控制延迟线（DCDL）用于将结构化ASIC中的输入或输出信号延迟或退出核心逻辑。 DCDL具有多级配置，在优选实施例中，包括两个精细延迟级，用于使用子门延迟微调微调延迟，该逆变器的延迟可以用其栅极被电压控制信号偏置的并行CMOS晶体管来调节，是温度计编码。微调阶段之后是使用门级延迟的粗略延迟阶段。 DCDL控制器输出灰度编码的控制信号，并通过二进制到温度计解码器转换为温度计编码的控制信号。 DCDL电路块和附带的结构化ASIC是在28nm CMOS工艺光刻节点上制造的。 DCDL采用使用平衡二叉树的高速路由选择。

3. 发明申请

US20040161878A1 Method for fabrication of semiconductor device 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20040161878A1
公开(公告)日：2004-08-19
申请号：US10730064
申请日：2003-12-09
申请人： eASIC Corporation
发明人： Zvi Or-Bach , Laurence Cooke , Adrian Apostol , Romeo Iacobut
IPC分类号： H01L021/44 , H01L023/34
CPC分类号： H01L23/525 , H01L2924/0002 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.
摘要翻译：提出了一种新颖的方法来为ASIC提供大幅降低的NRE和体积灵活性。本发明包括一种制造集成电路的方法，包括以下步骤：提供半导体衬底，形成包括多个区域I / O的无边界逻辑阵列，并且还包括形成再分配层以重新分配至少一些区域I / O用于设备包装。该制造可以利用直接写电子束进行定制。定制步骤可以包括制造与同一晶片不同体积的各种类型的装置。

4. 再颁专利

USRE46474E1 Multiple write during simultaneous memory access of a multi-port memory device 有权
公开(公告)号：USRE46474E1
公开(公告)日：2017-07-11
申请号：US14579337
申请日：2014-12-22
申请人： eASIC Corporation
发明人： Hui Hui Ngu , Bruce Gieseke
IPC分类号： G11C11/412 , G11C8/00 , G11C8/16 , G11C11/413
CPC分类号： G11C11/412 , G11C8/16 , G11C11/413
摘要： A memory system may provide for a successful write of a multi-port memory cell (e.g., dual-port 2WR SRAM cell) when it is simultaneously accessed by more than one port. This multi-port memory cell may include at least two independent accesses to the memory cell, where each access may be controlled by an independent wordline signal. Each port may have an independent pair of bitlines. Multiple write circuitry (e.g., double write circuitry) may enable the write driver to drive the input data to more than one pair of bitlines simultaneously.

5. 发明授权

US08957398B2 Via-configurable high-performance logic block involving transistor chains 有权
标题翻译：通过可配置的高性能逻辑块涉及晶体管链
公开(公告)号：US08957398B2
公开(公告)日：2015-02-17
申请号：US13649510
申请日：2012-10-11
申请人： eASIC Corporation
发明人： Alexander Andreev , Sergey Gribok , Ranko L. Scepanovic , Phey-Chuin Tan , Chee-Wei Kung
IPC分类号： H01L27/08 , H01L47/00 , H03K19/0948 , G06F17/50 , H03K19/177
CPC分类号： H03K19/0948 , G06F17/505 , H03K19/17728 , H03K19/17796
摘要： A via-configurable logic block architecture for a Structured ASIC has a plurality of MOSFET transistor chains connected to one another through vias. In one embodiment there are three chains and the first transistor chain is a NFET transistor chain, the second transistor chain is a PFET transistor chain, and the third transistor chain is a NFET transistor chain. The first, second and third transistor chains are formed into devices made of transistors that are selected from a voltage threshold group consisting of LVT, SVT and HVT devices, where the first and third transistor chains are formed into devices from a voltage threshold group that is different from one another. In another embodiment transistor drive strength may be varied in the transistor chains of the logic block. In yet another embodiment both voltage threshold and drive strength may be varied together in a symmetrical manner.
摘要翻译：用于结构化ASIC的通孔可配置逻辑块架构具有通过通孔彼此连接的多个MOSFET晶体管链。在一个实施例中，存在三条链，第一晶体管链是NFET晶体管链，第二晶体管链是PFET晶体管链，第三晶体管链是NFET晶体管链。第一，第二和第三晶体管链形成为由从由LVT，SVT和HVT器件组成的电压阈值组中选择的晶体管制成的器件，其中第一和第三晶体管链由电压阈值组形成器件，彼此不同在另一个实施例中，晶体管驱动强度可以在逻辑块的晶体管链中变化。在另一个实施例中，电压阈值和驱动强度可以以对称的方式一起变化。

6. 发明授权

US08677306B1 Microcontroller controlled or direct mode controlled network-fabric on a structured ASIC 有权
标题翻译：微控制器控制或直接模式控制的网络结构在结构化ASIC上
公开(公告)号：US08677306B1
公开(公告)日：2014-03-18
申请号：US13649551
申请日：2012-10-11
申请人： eASIC Corporation
发明人： Alexander Andreev , Andrey Nikitin , Marian Serbian , Massimo Verita
IPC分类号： G06F11/22 , G06F17/50
CPC分类号： G06F11/267
摘要： A network-fabric used for testing with an external or internal tester is shown for a Structured ASIC. In one embodiment, the Structured ASIC uses a microprocessor, network-aware IO routing fabric comprising network agents in a scalable novel configuration, with the network-aware IO having a plurality of blocks connected in series in a plurality of paths in the fabric leading to and from the microprocessor and memory and/or logic, the blocks acting as intelligent network agents under processor control to determine what state they can assume, whether to pass a data signal or not along these paths, comprising open loops and closed loops running to and from the microprocessor and memory and/or logic, primarily for testing and determining the state of the memory and logic. In another embodiment a JTAG controller may receive JTAG test commands from an external testing apparatus and set up to communicate along the fabric.
摘要翻译：结构化ASIC显示了用于外部或内部测试仪测试的网络结构。在一个实施例中，结构化ASIC使用包括可扩展新颖配置的网络代理的基于网络的IO路由选择结构，网络感知IO具有多个块，其中多个块在结构中的多个路径中串联连接，从而导致并且从微处理器和存储器和/或逻辑，这些块作为处理器控制下的智能网络代理，以确定它们可以承担什么状态，是否沿着这些路径传递数据信号，包括开环和运行到和从微处理器和存储器和/或逻辑，主要用于测试和确定存储器和逻辑的状态。在另一个实施例中，JTAG控制器可以从外部测试装置接收JTAG测试命令，并设置为沿着结构进行通信。

7. 发明申请

US20160124899A1 MULTI-CHIP PACKAGED FUNCTION INCLUDING A PROGRAMMABLE DEVICE AND A FIXED FUNCTION DIE AND USE FOR APPLICATION ACCELERATION 审中-公开
标题翻译：多芯片封装功能，包括可编程器件和固定功能模块，并用于应用程序加速
公开(公告)号：US20160124899A1
公开(公告)日：2016-05-05
申请号：US14719430
申请日：2015-05-22
申请人： eASIC Corporation
发明人： Ronnie VASISHTA , Ban P. WONG
IPC分类号： G06F15/78 , G06F9/38
CPC分类号： G06F15/7817 , G06F15/7807 , G06F15/7853 , G06F15/7889 , Y02D10/12 , Y02D10/13
摘要： One or more processing functions may be off-loaded from a general-purpose processing device to auxiliary processing devices. The auxiliary processing devices may include a programmable element and a fixed-function element that may be pre-configured to perform the one or more processing functions. The programmable element and the fixed-function element may be dies of a multi-chip module (MOM) in a common package that can contain the general-purpose processing device, or the general-purpose processing device may reside outside of the MOM.
摘要翻译：一个或多个处理功能可以从通用处理设备卸载到辅助处理设备。辅助处理装置可以包括可预先配置为执行一个或多个处理功能的可编程元件和固定功能元件。可编程元件和固定功能元件可以是可以容纳通用处理装置的通用封装中的多芯片模块（MOM）的裸片，或者通用处理装置可以驻留在MOM之外。

8. 发明申请

US20140103959A1 Architectural Floorplan for a Structured ASIC Manufactured on a 28 NM CMOS Process Lithographic Node or Smaller 有权
标题翻译：在28 NM CMOS工艺光刻节点或更小的制造结构化ASIC的建筑平面布置图
公开(公告)号：US20140103959A1
公开(公告)日：2014-04-17
申请号：US13649529
申请日：2012-10-11
申请人： eASIC Corporation
发明人： Alexander Andreev , Ranko L. Scepanovic , Ivan Pavisic , Alexander Yahontov , Mikhail Udovikhin , Igor Vikhliantsev , Chong-Teik Lim , Seow-Sung Lee , Chee-Wei Kung
IPC分类号： H03K19/0185 , G06F17/50
CPC分类号： H03K19/018585 , G06F17/505 , H01L2924/0002 , H01L2924/00
摘要： A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer.
摘要翻译：结构化ASIC芯片的平面图示出具有包含存储器的核心区域和由多个IO连接结构包围的VCLB逻辑单元，所述IO连接结构包括第一IO连接结构，该第一IO连接结构包括将芯片的核心连接到用于外部信号的引脚核心是沿着核心的东西垂直顶部布置的第一个高速布线布线，并将核心连接到诸如SerDes之类的高速IO; 网络感知连接架构将核心连接到微控制器，主要用于测试和修复内核中的内存; 并且第二高速布线布置在核心的南北垂直侧并与IO子库通信。 VCLB结构化ASIC芯片在28nm CMOS工艺光刻节点上制造，具有多个金属层，并且优选地在单个通孔层上编程。

9. 发明申请

US20140028348A1 Via-Configurable High-Performance Logic Block Involving Transistor Chains 有权
标题翻译：通过可配置的高性能逻辑块涉及晶体管链
公开(公告)号：US20140028348A1
公开(公告)日：2014-01-30
申请号：US13649510
申请日：2012-10-11
申请人： EASIC CORPORATION
发明人： Alexander Andreev , Sergey Gribok , Ranko L. Scepanovic , Phey-Chuin Tan , Chee-Wei Kung
IPC分类号： H03K19/0948 , G06F17/50
CPC分类号： H03K19/0948 , G06F17/505 , H03K19/17728 , H03K19/17796
摘要： A via-configurable logic block architecture for a Structured ASIC has a plurality of MOSFET transistor chains connected to one another through vias. In one embodiment there are three chains and the first transistor chain is a NFET transistor chain, the second transistor chain is a PFET transistor chain, and the third transistor chain is a NFET transistor chain. The first, second and third transistor chains are formed into devices made of transistors that are selected from a voltage threshold group consisting of LVT, SVT and HVT devices, where the first and third transistor chains are formed into devices from a voltage threshold group that is different from one another. In another embodiment transistor drive strength may be varied in the transistor chains of the logic block. In yet another embodiment both voltage threshold and drive strength may be varied together in a symmetrical manner.
摘要翻译：用于结构化ASIC的通孔可配置逻辑块架构具有通过通孔彼此连接的多个MOSFET晶体管链。在一个实施例中，存在三条链，第一晶体管链是NFET晶体管链，第二晶体管链是PFET晶体管链，第三晶体管链是NFET晶体管链。第一，第二和第三晶体管链形成为由从由LVT，SVT和HVT器件组成的电压阈值组中选择的晶体管制成的器件，其中第一和第三晶体管链由电压阈值组形成器件，彼此不同在另一个实施例中，晶体管驱动强度可以在逻辑块的晶体管链中变化。在另一个实施例中，电压阈值和驱动强度可以以对称的方式一起变化。

10. 发明申请

US20040119098A1 Method for fabrication of semiconductor device 有权
公开(公告)号：US20040119098A1
公开(公告)日：2004-06-24
申请号：US10321669
申请日：2002-12-18
申请人： eASIC Corporation
发明人： Zvi Or-Bach , Laurance Cooke
IPC分类号： H01L027/10
CPC分类号： H01L23/525 , H01L2924/0002 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.

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