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1. 发明申请

US20090006930A1 Techniques For Generating Bit Reliability Information In The Post Processor 有权
标题翻译：在后处理器中生成位可靠性信息的技术
公开(公告)号：US20090006930A1
公开(公告)日：2009-01-01
申请号：US11771226
申请日：2007-06-29
申请人： Ivana Djurdjevic , Richard Leo Galbraith , Bruce Alexander Wilson , Yuan Xing Lee , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Zongwang Li
发明人： Ivana Djurdjevic , Richard Leo Galbraith , Bruce Alexander Wilson , Yuan Xing Lee , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Zongwang Li
IPC分类号： H03M13/00
CPC分类号： H03M13/45 , H03M13/11 , H03M13/41 , H03M13/43 , H03M13/6575 , H04L1/005
摘要： A detector generates a detected sequence, and a post processor generates probability values that indicate the likelihood of a plurality of error events in the detected sequence. The post processor partitions the values into first and second subsets. The post processor selects a first most likely value from the first subset of the values and a second most likely value from the second subset of the values. The post processor generates a bit reliability based on the first and the second most likely values.
摘要翻译：检测器产生检测到的序列，并且后处理器产生指示检测到的序列中的多个错误事件的可能性的概率值。后处理器将值分为第一和第二子集。后处理器从值的第一子集中选择第一最可能的值，并从值的第二子集中选择第二最有可能的值。后处理器基于第一和第二最有可能的值产生位可靠性。

2. 发明申请

US20080244359A1 Techniques For Correcting Errors Using Iterative Decoding 有权
标题翻译：使用迭代解码校正错误的技术
公开(公告)号：US20080244359A1
公开(公告)日：2008-10-02
申请号：US11694676
申请日：2007-03-30
申请人： Zongwang Li , Yuan Xing Lee , Richard Leo Galbraith , Ivana Djurdjevic , Travis Roger Oenning
发明人： Zongwang Li , Yuan Xing Lee , Richard Leo Galbraith , Ivana Djurdjevic , Travis Roger Oenning
IPC分类号： H03M13/00
CPC分类号： H03M13/112 , H03M13/1102 , H03M13/1117 , H03M13/1128 , H03M13/1515 , H03M13/2966 , H03M13/2975 , H03M13/2987 , H03M13/6331 , H03M13/658 , H04L1/005 , H04L1/0057
摘要： Techniques are provided for iteratively decoding data recorded on a data storage device. An iterative decoder decodes the data using multiple decoding iterations to correct errors. In multiple iterations of the iterative decoder, a post processing block generates soft information, and a decoder applies a minimum sum decoding algorithm to a low density parity check (LDPC) code to generate extrinsic information based on the soft information and updated soft information.
摘要翻译：提供了用于迭代地解码记录在数据存储设备上的数据的技术。迭代解码器使用多个解码迭代来解码数据以校正错误。在迭代解码器的多次迭代中，后处理块产生软信息，并且解码器将最小和解码算法应用于低密度奇偶校验（LDPC）码，以基于软信息和更新的软信息生成外在信息。

3. 发明申请

US20090006931A1 Techniques For Generating Bit Reliability Information In A Post-Processor Using An Error Correction Constraint 有权
标题翻译：使用误差校正约束在后处理器中生成位可靠性信息的技术
公开(公告)号：US20090006931A1
公开(公告)日：2009-01-01
申请号：US11771783
申请日：2007-06-29
申请人： Ivana Djurdjevic , Bruce Alexander Wilson , Mario Blaum , Richard Leo Galbraith , Ksenija Lakovic , Yuan Xing Lee , Zongwang Li , Travis Roger Oenning
发明人： Ivana Djurdjevic , Bruce Alexander Wilson , Mario Blaum , Richard Leo Galbraith , Ksenija Lakovic , Yuan Xing Lee , Zongwang Li , Travis Roger Oenning
IPC分类号： G06F11/34
CPC分类号： G11B20/1833 , G11B20/10046 , G11B2020/185 , G11B2020/1863 , H03M13/1102 , H03M13/2957 , H03M13/6343
摘要： Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the first bit value, finds a second set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the second bit value, selects a first most likely combination of one or more events of the first set and a second most likely combination of one or more events of the second set, and generates a bit reliability based on the first and the second most likely values.
摘要翻译：提供了为检测到的序列生成位可靠性的技术。检测器产生检测到的序列。根据一个实施例，后处理器在检测到的序列中找到一个或多个错误事件的组合的第一组，其满足对应于第一位值的完整集合或纠错约束的子集，找到第二组组合检测到的序列中的一个或多个错误事件满足对应于第二位值的完整集合或纠错约束的子集，选择第一集合中的一个或多个事件的第一最有可能的组合和第一集合的第二最有可能的组合或更多的事件，并且基于第一和第二最有可能的值产生位可靠性。

4. 发明授权

US08341506B2 Techniques for correcting errors using iterative decoding 有权
标题翻译：使用迭代解码校正错误的技术
公开(公告)号：US08341506B2
公开(公告)日：2012-12-25
申请号：US11694676
申请日：2007-03-30
申请人： Zongwang Li , Yuan Xing Lee , Richard Leo Galbraith , Ivana Djurdjevic , Travis Roger Oenning
发明人： Zongwang Li , Yuan Xing Lee , Richard Leo Galbraith , Ivana Djurdjevic , Travis Roger Oenning
IPC分类号： H03M13/00 , H03M13/03
CPC分类号： H03M13/112 , H03M13/1102 , H03M13/1117 , H03M13/1128 , H03M13/1515 , H03M13/2966 , H03M13/2975 , H03M13/2987 , H03M13/6331 , H03M13/658 , H04L1/005 , H04L1/0057
摘要： Techniques are provided for iteratively decoding data recorded on a data storage device. An iterative decoder decodes the data using multiple decoding iterations to correct errors. In multiple iterations of the iterative decoder, a post processing block generates soft information, and a decoder applies a minimum sum decoding algorithm to a low density parity check (LDPC) code to generate extrinsic information based on the soft information and updated soft information.
摘要翻译：提供了用于迭代地解码记录在数据存储设备上的数据的技术。迭代解码器使用多个解码迭代来解码数据以校正错误。在迭代解码器的多次迭代中，后处理块产生软信息，并且解码器将最小和解码算法应用于低密度奇偶校验（LDPC）码，以基于软信息和更新的软信息生成外在信息。

5. 发明授权

US08037394B2 Techniques for generating bit reliability information in a post-processor using an error correction constraint 有权
标题翻译：使用纠错约束在后处理器中生成比特可靠性信息的技术
公开(公告)号：US08037394B2
公开(公告)日：2011-10-11
申请号：US11771783
申请日：2007-06-29
申请人： Ivana Djurdjevic , Bruce Alexander Wilson , Mario Blaum , Richard Leo Galbraith , Ksenija Lakovic , Yuan Xing Lee , Zongwang Li , Travis Roger Oenning
发明人： Ivana Djurdjevic , Bruce Alexander Wilson , Mario Blaum , Richard Leo Galbraith , Ksenija Lakovic , Yuan Xing Lee , Zongwang Li , Travis Roger Oenning
IPC分类号： H03M13/45
CPC分类号： G11B20/1833 , G11B20/10046 , G11B2020/185 , G11B2020/1863 , H03M13/1102 , H03M13/2957 , H03M13/6343
摘要： Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the first bit value, finds a second set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the second bit value, selects a first most likely combination of one or more events of the first set and a second most likely combination of one or more events of the second set, and generates a bit reliability based on the first and the second most likely values.
摘要翻译：提供了为检测到的序列生成位可靠性的技术。检测器产生检测到的序列。根据一个实施例，后处理器在检测到的序列中找到一个或多个错误事件的组合的第一组，其满足对应于第一位值的完整集合或纠错约束的子集，找到第二组组合检测到的序列中的一个或多个错误事件满足对应于第二位值的完整集合或纠错约束的子集，选择第一集合中的一个或多个事件的第一最有可能的组合和第一集合的第二最有可能的组合或更多的事件，并且基于第一和第二最有可能的值产生位可靠性。

6. 发明授权

US08037393B2 Techniques for generating bit reliability information in the post processor 有权
标题翻译：用于在后处理器中生成位可靠性信息的技术
公开(公告)号：US08037393B2
公开(公告)日：2011-10-11
申请号：US11771226
申请日：2007-06-29
申请人： Ivana Djurdjevic , Richard Leo Galbraith , Bruce Alexander Wilson , Yuan Xing Lee , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Zongwang Li
发明人： Ivana Djurdjevic , Richard Leo Galbraith , Bruce Alexander Wilson , Yuan Xing Lee , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Zongwang Li
IPC分类号： H03M13/45
CPC分类号： H03M13/45 , H03M13/11 , H03M13/41 , H03M13/43 , H03M13/6575 , H04L1/005
摘要： A detector generates a detected sequence, and a post processor generates probability values that indicate the likelihood of a plurality of error events in the detected sequence. The post processor partitions the values into first and second subsets. The post processor selects a first most likely value from the first subset of the values and a second most likely value from the second subset of the values. The post processor generates a bit reliability based on the first and the second most likely values.
摘要翻译：检测器产生检测到的序列，并且后处理器产生指示检测到的序列中的多个错误事件的可能性的概率值。后处理器将值分为第一和第二子集。后处理器从值的第一子集中选择第一最可能的值，并从值的第二子集中选择第二最有可能的值。后处理器基于第一和第二最可能的值产生位可靠性。

7. 发明申请

US20090235142A1 Systems Using Low Density Parity Check Codes For Correcting Errors 有权
标题翻译：使用低密度奇偶校验码纠正错误的系统
公开(公告)号：US20090235142A1
公开(公告)日：2009-09-17
申请号：US12046108
申请日：2008-03-11
申请人： Richard Leo Galbraith , Bruce Alexander Wilson , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Ivana Djurdjevic
发明人： Richard Leo Galbraith , Bruce Alexander Wilson , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Ivana Djurdjevic
IPC分类号： H03M13/11 , G06F11/10
CPC分类号： H03M13/1111 , G11B20/18
摘要： A system corrects errors in a bit stream. The system includes an encoder and a decoder. The encoder encodes the bit stream using a low density parity check code by inserting parity check bits into the bit stream to generate codewords. The decoder decodes the codewords using parity check equations that are based on the low density parity check code. The parity check bits may comprise no more than four percent of the bits in the codewords of the low density parity check code. The low density parity check code can have a minimum separation of at least 7 between any two ones in each row of a parity-check matrix that is based on the low density parity check code. The encoder and the decoder can be defined in hardware using logic circuits that are interconnected to implement a trellis based on the low density parity check code.
摘要翻译：系统校正位流中的错误。该系统包括编码器和解码器。编码器使用低密度奇偶校验码将奇偶校验位插入比特流来编码比特流以产生码字。解码器使用基于低密度奇偶校验码的奇偶校验等式来解码码字。奇偶校验位可以包括不超过低密度奇偶校验码的码字中的比特的百分之四。低密度奇偶校验码可以在基于低密度奇偶校验码的奇偶校验矩阵的每行中的任何两个之间具有至少7的最小间隔。编码器和解码器可以使用互连的逻辑电路在硬件中定义，以实现基于低密度奇偶校验码的网格。

8. 发明授权

US08209578B2 Systems using low density parity check codes for correcting errors 有权
标题翻译：使用低密度奇偶校验码纠正错误的系统
公开(公告)号：US08209578B2
公开(公告)日：2012-06-26
申请号：US12046108
申请日：2008-03-11
申请人： Richard Leo Galbraith , Bruce Alexander Wilson , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Ivana Djurdjevic
发明人： Richard Leo Galbraith , Bruce Alexander Wilson , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Ivana Djurdjevic
IPC分类号： H03M13/05
CPC分类号： H03M13/1111 , G11B20/18
摘要： A system corrects errors in a bit stream. The system includes an encoder and a decoder. The encoder encodes the bit stream using a low density parity check code by inserting parity check bits into the bit stream to generate codewords. The decoder decodes the codewords using parity check equations that are based on the low density parity check code. The parity check bits may comprise no more than four percent of the bits in the codewords of the low density parity check code. The low density parity check code can have a minimum separation of at least 7 between any two ones in each row of a parity-check matrix that is based on the low density parity check code. The encoder and the decoder can be defined in hardware using logic circuits that are interconnected to implement a trellis based on the low density parity check code.
摘要翻译：系统校正位流中的错误。该系统包括编码器和解码器。编码器使用低密度奇偶校验码将奇偶校验位插入比特流来编码比特流以产生码字。解码器使用基于低密度奇偶校验码的奇偶校验等式来解码码字。奇偶校验位可以包括不超过低密度奇偶校验码的码字中的比特的百分之四。低密度奇偶校验码可以在基于低密度奇偶校验码的奇偶校验矩阵的每行中的任何两个之间具有至少7的最小间隔。编码器和解码器可以使用互连的逻辑电路在硬件中定义，以实现基于低密度奇偶校验码的网格。

9. 发明授权

US08654464B2 Implementing magnetic defect classification using phase modulation 失效
标题翻译：使用相位调制实现磁缺陷分类
公开(公告)号：US08654464B2
公开(公告)日：2014-02-18
申请号：US13277047
申请日：2011-10-19
申请人： Richard Leo Galbraith , Weldon Mark Hanson , Martin Aureliano Hassner , Travis Roger Oenning , Satoshi Yamamoto
发明人： Richard Leo Galbraith , Weldon Mark Hanson , Martin Aureliano Hassner , Travis Roger Oenning , Satoshi Yamamoto
IPC分类号： G11B5/02
CPC分类号： G11B5/09 , G11B20/18 , G11B27/36 , G11B2020/1826 , G11B2220/2516
摘要： A method, apparatus, and system are provided for implementing magnetic defect classification using phase modulation for hard disk drives. A magnetic media readback signal of a hard disk drive is processed to identify predefined phase modulation (PM) characteristics to implement magnetic defect classification of magnetic media bump and pit defects.
摘要翻译：提供了一种使用硬盘驱动器的相位调制实现磁缺陷分类的方法，装置和系统。处理硬盘驱动器的磁性媒体回读信号以识别预定的相位调制（PM）特性，以实现磁性介质凸起和凹坑缺陷的磁性缺陷分类。

10. 发明授权

US08369143B2 Early detection of degradation in NOR flash memory 有权
标题翻译：早期检测NOR闪存中的降解
公开(公告)号：US08369143B2
公开(公告)日：2013-02-05
申请号：US12930019
申请日：2010-12-22
申请人： Luiz M. Franca-Neto , Richard Leo Galbraith , Travis Roger Oenning
发明人： Luiz M. Franca-Neto , Richard Leo Galbraith , Travis Roger Oenning
IPC分类号： G11C11/34
CPC分类号： G11C16/3495
摘要： The embodiments of the invention in this disclosure describe techniques for early warning of degradation in NOR Flash memories by estimating the dispersion of the threshold voltages (VT's), of a set of NOR Flash memory cells during read operations. In an embodiment invention the time-to-completion (TTC) values for the read operation for the memory cells are used as a proxy for dispersion of the threshold voltages (VT's). If the measured TTC dispersion differs by more than a selected amount from the reference dispersion value, a warning signal is provided to indicate that the page of memory has degraded significantly. Higher level components in the system can use the warning signal to take appropriate action. Since every cell's VT position in an ideal distribution can be estimated, the data from each cell can have a confidence level assigned based on deviation from the mean of an ideal distribution.
摘要翻译：本公开的本发明的实施例通过估计在读取操作期间的一组NOR闪存单元的阈值电压（VT）的偏差来描述用于NOR闪存中的劣化预警的技术。在一个实施例中，用于存储器单元的读取操作的时间到完成（TTC）值被用作阈值电压（VT's）的色散的代理。如果所测量的TTC色散比参考色散值差异多于所选择的量，则提供警告信号以指示存储器页面显着降级。系统中较高级别的组件可以使用警告信号采取适当的措施。由于可以估计每个单元的理想分布中的VT位置，所以来自每个单元的数据可以具有基于与理想分布的平均值的偏差分配的置信水平。

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