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1. 发明授权

US08422296B2 Early detection of degradation in NAND flash memory 失效
标题翻译：早期检测NAND闪存中的劣化
公开(公告)号：US08422296B2
公开(公告)日：2013-04-16
申请号：US12930016
申请日：2010-12-22
申请人： Luiz M. Franca-Neto , Richard Leo Galbraith , Travis Roger Oenning
发明人： Luiz M. Franca-Neto , Richard Leo Galbraith , Travis Roger Oenning
IPC分类号： G11C11/34
CPC分类号： G11C16/3495
摘要： Techniques for early detection of degradation in NAND Flash memories by measuring the dispersion of the threshold voltages (VT's), of a set (e.g. page) of NAND Flash memory cells during read operations are described. In an embodiment of the invention the time-to-completion (TTC) values for the read operation for the memory cells are used as a proxy for dispersion of the threshold voltages (VT's). A Dispersion Analyzer determines the dispersion of the set of TTC values. In one embodiment the delta between the maximum and minimum TTC values is used as the dispersion measurement. If the measured TTC dispersion differs by more than a selected amount from a reference dispersion value, a warning signal is provided to indicate that the page of memory has degraded. The warning signal can be used to take appropriate action such as moving the data to a new page.
摘要翻译：描述了在读取操作期间通过测量NAND闪存单元组（例如页面）的阈值电压（VT）的偏差来早期检测NAND闪存中的劣化的技术。在本发明的一个实施例中，用于存储器单元的读取操作的完成时间（TTC）值用作阈值电压（VT）的色散的代理。色散分析仪确定一组TTC值的色散。在一个实施例中，使用最大和最小TTC值之间的差值作为色散测量。如果测量的TTC色散比参考色散值差多于选定量，则提供警告信号以指示存储器页面已经劣化。警告信号可用于采取适当措施，例如将数据移动到新页面。

2. 发明授权

US08300342B2 Multi-bit phase alignment for synchronization mark pattern matching 有权
标题翻译：用于同步标记模式匹配的多位相位对齐
公开(公告)号：US08300342B2
公开(公告)日：2012-10-30
申请号：US12150814
申请日：2008-04-30
申请人： Richard Leo Galbraith , Weldon Mark Hanson , Travis Roger Oenning , Todd Carter Truax
发明人： Richard Leo Galbraith , Weldon Mark Hanson , Travis Roger Oenning , Todd Carter Truax
IPC分类号： G11B5/09 , H04L27/06
CPC分类号： G11B20/10009 , G11B20/10027 , G11B20/10046 , G11B20/10055 , G11B20/10194 , G11B20/10212 , G11B20/10222 , G11B20/10296 , G11B20/14 , G11B2020/1287 , G11B2020/1476 , G11B2220/2516
摘要： Embodiments of the present invention relate to the detection of synchronization marks in data storage and retrieval. To detect a synchronization mark, embodiments of the present invention require both pattern matching and proper phase alignment, following a repeating synchronization field. According to one particular embodiment, proper phase alignment following a repeated four bit synchronization field, is utilized in conjunction with pattern matching, to identify a synchronization mark. By allowing a synchronization mark to be identified only with proper phase alignment at the earliest possible occurrence of the synchronization mark, accuracy of synchronization mark detection may be improved.
摘要翻译：本发明的实施例涉及数据存储和检索中的同步标记的检测。为了检测同步标记，在重复的同步字段之后，本发明的实施例需要模式匹配和适当的相位对准。根据一个特定实施例，在重复的四位同步字段之后的适当的相位对准与模式匹配结合使用以识别同步标记。通过允许在同步标记的最早可能出现的情况下仅通过适当的相位对准来识别同步标记，可以提高同步标记检测的精度。

3. 发明授权

US07733591B2 Data storage device with data recovery process using fixed phase clocking for analog-to-digital conversion 失效
标题翻译：具有数据恢复过程的数据存储设备使用固定相位时钟进行模数转换
公开(公告)号：US07733591B2
公开(公告)日：2010-06-08
申请号：US11641322
申请日：2006-12-18
申请人： Kraig Bottemiller , Richard Leo Galbraith , Weldon Mark Hanson , Travis Roger Oenning , Michael Joseph Ross , Fuminori Sai
发明人： Kraig Bottemiller , Richard Leo Galbraith , Weldon Mark Hanson , Travis Roger Oenning , Michael Joseph Ross , Fuminori Sai
IPC分类号： G11B5/09 , G11B15/52 , G11B19/02 , G11B5/02 , G11B20/18
CPC分类号： G11B5/09 , G11B20/10055 , G11B20/10222 , G11B20/10481 , G11B20/10527 , G11B20/1403 , G11B2020/1062
摘要： The invention includes apparatus and methods that allow a data storage device perform an enhanced data recovery procedure (DRP) that includes obtaining a new digital sampling of the voltages for the failing unit of data by re-reading the analog signal and converting it to digital form using an analog-to-digital conversion (ADC) using a fixed phase clock signal. The data samples are re-interpolated using a programmable delay line. The digital values representing the voltages are stored a buffer so that the data can be processed repeatedly using varying parameters as part of the data recovery procedure. Optionally the samples stored in the buffer can be processed in the reverse direction (from end of sector to beginning of sector) without requiring modification of the standard Viterbi detector since it inherently works on data processed in either direction.
摘要翻译：本发明包括允许数据存储设备执行增强型数据恢复过程（DRP）的装置和方法，其包括通过重新读取模拟信号并将其转换为数字形式来获得用于数据故障单元的电压的新数字采样使用固定相位时钟信号的模数转换（ADC）。使用可编程延迟线重新插值数据采样。表示电压的数字值被存储在缓冲器中，使得可以使用变化的参数重复处理数据，作为数据恢复过程的一部分。可选地，存储在缓冲器中的样本可以在相反方向（从扇区的结束到扇区的开始）进行处理，而不需要修改标准维特比检测器，因为它固有地对在任一方向上处理的数据进行工作。

4. 发明申请

US20090235142A1 Systems Using Low Density Parity Check Codes For Correcting Errors 有权
标题翻译：使用低密度奇偶校验码纠正错误的系统
公开(公告)号：US20090235142A1
公开(公告)日：2009-09-17
申请号：US12046108
申请日：2008-03-11
申请人： Richard Leo Galbraith , Bruce Alexander Wilson , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Ivana Djurdjevic
发明人： Richard Leo Galbraith , Bruce Alexander Wilson , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Ivana Djurdjevic
IPC分类号： H03M13/11 , G06F11/10
CPC分类号： H03M13/1111 , G11B20/18
摘要： A system corrects errors in a bit stream. The system includes an encoder and a decoder. The encoder encodes the bit stream using a low density parity check code by inserting parity check bits into the bit stream to generate codewords. The decoder decodes the codewords using parity check equations that are based on the low density parity check code. The parity check bits may comprise no more than four percent of the bits in the codewords of the low density parity check code. The low density parity check code can have a minimum separation of at least 7 between any two ones in each row of a parity-check matrix that is based on the low density parity check code. The encoder and the decoder can be defined in hardware using logic circuits that are interconnected to implement a trellis based on the low density parity check code.
摘要翻译：系统校正位流中的错误。该系统包括编码器和解码器。编码器使用低密度奇偶校验码将奇偶校验位插入比特流来编码比特流以产生码字。解码器使用基于低密度奇偶校验码的奇偶校验等式来解码码字。奇偶校验位可以包括不超过低密度奇偶校验码的码字中的比特的百分之四。低密度奇偶校验码可以在基于低密度奇偶校验码的奇偶校验矩阵的每行中的任何两个之间具有至少7的最小间隔。编码器和解码器可以使用互连的逻辑电路在硬件中定义，以实现基于低密度奇偶校验码的网格。

5. 发明申请

US20090006930A1 Techniques For Generating Bit Reliability Information In The Post Processor 有权
标题翻译：在后处理器中生成位可靠性信息的技术
公开(公告)号：US20090006930A1
公开(公告)日：2009-01-01
申请号：US11771226
申请日：2007-06-29
申请人： Ivana Djurdjevic , Richard Leo Galbraith , Bruce Alexander Wilson , Yuan Xing Lee , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Zongwang Li
发明人： Ivana Djurdjevic , Richard Leo Galbraith , Bruce Alexander Wilson , Yuan Xing Lee , Travis Roger Oenning , Mario Blaum , Ksenija Lakovic , Zongwang Li
IPC分类号： H03M13/00
CPC分类号： H03M13/45 , H03M13/11 , H03M13/41 , H03M13/43 , H03M13/6575 , H04L1/005
摘要： A detector generates a detected sequence, and a post processor generates probability values that indicate the likelihood of a plurality of error events in the detected sequence. The post processor partitions the values into first and second subsets. The post processor selects a first most likely value from the first subset of the values and a second most likely value from the second subset of the values. The post processor generates a bit reliability based on the first and the second most likely values.
摘要翻译：检测器产生检测到的序列，并且后处理器产生指示检测到的序列中的多个错误事件的可能性的概率值。后处理器将值分为第一和第二子集。后处理器从值的第一子集中选择第一最可能的值，并从值的第二子集中选择第二最有可能的值。后处理器基于第一和第二最有可能的值产生位可靠性。

6. 发明申请

US20080244359A1 Techniques For Correcting Errors Using Iterative Decoding 有权
标题翻译：使用迭代解码校正错误的技术
公开(公告)号：US20080244359A1
公开(公告)日：2008-10-02
申请号：US11694676
申请日：2007-03-30
申请人： Zongwang Li , Yuan Xing Lee , Richard Leo Galbraith , Ivana Djurdjevic , Travis Roger Oenning
发明人： Zongwang Li , Yuan Xing Lee , Richard Leo Galbraith , Ivana Djurdjevic , Travis Roger Oenning
IPC分类号： H03M13/00
CPC分类号： H03M13/112 , H03M13/1102 , H03M13/1117 , H03M13/1128 , H03M13/1515 , H03M13/2966 , H03M13/2975 , H03M13/2987 , H03M13/6331 , H03M13/658 , H04L1/005 , H04L1/0057
摘要： Techniques are provided for iteratively decoding data recorded on a data storage device. An iterative decoder decodes the data using multiple decoding iterations to correct errors. In multiple iterations of the iterative decoder, a post processing block generates soft information, and a decoder applies a minimum sum decoding algorithm to a low density parity check (LDPC) code to generate extrinsic information based on the soft information and updated soft information.
摘要翻译：提供了用于迭代地解码记录在数据存储设备上的数据的技术。迭代解码器使用多个解码迭代来解码数据以校正错误。在迭代解码器的多次迭代中，后处理块产生软信息，并且解码器将最小和解码算法应用于低密度奇偶校验（LDPC）码，以基于软信息和更新的软信息生成外在信息。

7. 发明授权

US08654464B2 Implementing magnetic defect classification using phase modulation 失效
标题翻译：使用相位调制实现磁缺陷分类
公开(公告)号：US08654464B2
公开(公告)日：2014-02-18
申请号：US13277047
申请日：2011-10-19
申请人： Richard Leo Galbraith , Weldon Mark Hanson , Martin Aureliano Hassner , Travis Roger Oenning , Satoshi Yamamoto
发明人： Richard Leo Galbraith , Weldon Mark Hanson , Martin Aureliano Hassner , Travis Roger Oenning , Satoshi Yamamoto
IPC分类号： G11B5/02
CPC分类号： G11B5/09 , G11B20/18 , G11B27/36 , G11B2020/1826 , G11B2220/2516
摘要： A method, apparatus, and system are provided for implementing magnetic defect classification using phase modulation for hard disk drives. A magnetic media readback signal of a hard disk drive is processed to identify predefined phase modulation (PM) characteristics to implement magnetic defect classification of magnetic media bump and pit defects.
摘要翻译：提供了一种使用硬盘驱动器的相位调制实现磁缺陷分类的方法，装置和系统。处理硬盘驱动器的磁性媒体回读信号以识别预定的相位调制（PM）特性，以实现磁性介质凸起和凹坑缺陷的磁性缺陷分类。

8. 发明授权

US08369143B2 Early detection of degradation in NOR flash memory 有权
标题翻译：早期检测NOR闪存中的降解
公开(公告)号：US08369143B2
公开(公告)日：2013-02-05
申请号：US12930019
申请日：2010-12-22
申请人： Luiz M. Franca-Neto , Richard Leo Galbraith , Travis Roger Oenning
发明人： Luiz M. Franca-Neto , Richard Leo Galbraith , Travis Roger Oenning
IPC分类号： G11C11/34
CPC分类号： G11C16/3495
摘要： The embodiments of the invention in this disclosure describe techniques for early warning of degradation in NOR Flash memories by estimating the dispersion of the threshold voltages (VT's), of a set of NOR Flash memory cells during read operations. In an embodiment invention the time-to-completion (TTC) values for the read operation for the memory cells are used as a proxy for dispersion of the threshold voltages (VT's). If the measured TTC dispersion differs by more than a selected amount from the reference dispersion value, a warning signal is provided to indicate that the page of memory has degraded significantly. Higher level components in the system can use the warning signal to take appropriate action. Since every cell's VT position in an ideal distribution can be estimated, the data from each cell can have a confidence level assigned based on deviation from the mean of an ideal distribution.
摘要翻译：本公开的本发明的实施例通过估计在读取操作期间的一组NOR闪存单元的阈值电压（VT）的偏差来描述用于NOR闪存中的劣化预警的技术。在一个实施例中，用于存储器单元的读取操作的时间到完成（TTC）值被用作阈值电压（VT's）的色散的代理。如果所测量的TTC色散比参考色散值差异多于所选择的量，则提供警告信号以指示存储器页面显着降级。系统中较高级别的组件可以使用警告信号采取适当的措施。由于可以估计每个单元的理想分布中的VT位置，所以来自每个单元的数据可以具有基于与理想分布的平均值的偏差分配的置信水平。

9. 发明申请

US20090213484A1 Techniques For Providing DC-free Detection of DC Equalization Target 有权
标题翻译：提供DC均衡目标的无DC检测技术
公开(公告)号：US20090213484A1
公开(公告)日：2009-08-27
申请号：US12035338
申请日：2008-02-21
申请人： Richard Leo Galbraith , Travis Roger Oenning
发明人： Richard Leo Galbraith , Travis Roger Oenning
IPC分类号： G11B5/035
CPC分类号： G11B5/035 , G11B5/09 , G11B20/10009 , G11B20/10037 , G11B20/10046 , G11B20/10055 , G11B20/10101 , G11B20/10203 , G11B20/10296 , G11B2020/185 , G11B2220/2516
摘要： A data storage device includes a first filter that generates a short DC equalization target in response to a read back signal generated from magnetic patterns that are recorded on a storage medium using perpendicular recording. The data storage device also includes a first detector that generates an output sequence in response to the short DC equalization target. The data storage device also includes a high pass filter that attenuates DC components of the short DC equalization target and that passes low frequency components of the short DC equalization target above a cutoff frequency to generate a filtered signal. The data storage device also includes a second detector that processes the output sequence in response to the filtered signal.
摘要翻译：数据存储装置包括：第一滤波器，其响应于使用垂直记录记录在存储介质上的磁性图案产生的回读信号，生成短DC均衡目标。数据存储装置还包括响应于短DC均衡目标而生成输出序列的第一检测器。数据存储装置还包括高通滤波器，其衰减短DC均衡目标的DC分量，并将短直流均衡目标的低频分量通过截止频率以产生滤波信号。数据存储装置还包括响应于滤波信号处理输出序列的第二检测器。

10. 发明授权

US08649215B2 Data management in flash memory using probability of charge disturbances 有权
标题翻译：使用电荷扰动概率的闪存中的数据管理
公开(公告)号：US08649215B2
公开(公告)日：2014-02-11
申请号：US12930017
申请日：2010-12-22
申请人： Luiz M. Franca-Neto , Richard Leo Galbraith , Travis Roger Oenning
发明人： Luiz M. Franca-Neto , Richard Leo Galbraith , Travis Roger Oenning
IPC分类号： G11C16/34 , G11C16/06 , G11C29/00 , G11C29/44
CPC分类号： G11C16/3495 , G11C29/50 , G11C2029/5002
摘要： A Flash memory system and a method for data management using the system's sensitivity to charge-disturbing operations and the history of charge-disturbing operations executed by the system are described. In an embodiment of the invention, the sensitivity to charge-disturbing operations is embodied in a disturb-strength matrix in which selected operations have an associated numerical value that is an estimate of the relative strength of that operation to cause disturbances in charge that result in data errors. The disturb-strength matrix can also include the direction of the error which indicates either a gain or loss of charge. The disturb-strength matrix can be determined by the device conducting a self-test in which charge-disturb errors are provoked by executing a selected operation until a detectable error occurs. In alternative embodiments the disturb-strength matrix is determined by testing selected units from a homogeneous population.
摘要翻译：描述了使用系统对充电干扰操作的灵敏度和系统执行的充电干扰操作的历史的数据管理的闪存系统和方法。在本发明的一个实施例中，对电荷干扰操作的灵敏度体现在干扰强度矩阵中，其中所选择的操作具有相关联的数值，该相关数值是该操作的相对强度的估计，以引起电荷干扰，导致导致数据错误。干扰强度矩阵还可以包括指示电荷增益或损失的误差方向。扰动强度矩阵可以由进行自检的装置确定，其中通过执行所选择的操作而引起充电扰乱错误，直到出现可检测的错误。在替代实施例中，通过从均匀群体测试所选择的单位来确定干扰强度矩阵。

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