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    • 1. 发明授权
    • Polish method for semiconductor device planarization
    • 用于半导体器件平面化的抛光方法
    • US07172970B2
    • 2007-02-06
    • US10384641
    • 2003-03-11
    • Zong Huei LinArt YuChia Rung HsuTeng-Chun Tsai
    • Zong Huei LinArt YuChia Rung HsuTeng-Chun Tsai
    • H01L21/461H01L21/469
    • H01L21/7684H01L21/31053H01L21/76229H01L21/76232
    • A polish method for planarization is disclosed. The method uses a combination of a traditional oxide CMP and HSP-CMP (High Selectivity and Planarization) with a fix abrasive pad to meet the requirements of the CMP process for a device feature dimension under 0.18 micron even to 0.09 micron. By using a first polish step with a conventional polish pad and an oxide polish slurry, the non-uniformity of the over-fill thickness of the STI dielectric layer can be firstly removed and a much more smooth and uniform topography favorable for the HSP-CMP process the fix abrasive polishing pad can be obtained. Then the HSP-CMP process with the fix abrasive polishing pad can be performed to provide a planarized surface with accurate dimension control.
    • 公开了一种用于平坦化的抛光方法。 该方法使用传统氧化物CMP和HSP-CMP(高选择性和平面化)与固定磨料垫的组合,以满足在0.18微米甚至0.09微米下的器件特征尺寸的CMP工艺的要求。 通过使用具有常规抛光垫和氧化物抛光浆料的第一抛光步骤,可以首先除去STI介电层的过度填充厚度的不均匀性,并且对HSP-CMP有利的更平滑和均匀的形貌 可以获得固定磨料抛光垫的工艺。 然后可以执行具有固定磨料抛光垫的HSP-CMP工艺,以提供具有精确尺寸控制的平坦化表面。