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    • 3. 发明授权
    • Chemical mechanical polishing process for forming shallow trench isolation structure
    • 用于形成浅沟槽隔离结构的化学机械抛光工艺
    • US07294575B2
    • 2007-11-13
    • US10752362
    • 2004-01-05
    • Chia-Rung HsuArt YuHsiao-Ling LuTeng-Chun Tsai
    • Chia-Rung HsuArt YuHsiao-Ling LuTeng-Chun Tsai
    • H01L31/461
    • H01L21/76229H01L21/31053
    • A shallow trench isolation (STI) multistage chemical mechanical polishing (CMP) method for forming a shallow trench isolation structure is provided. The substrate comprising a dense region and an isolation region, a silicon nitride layer formed over the substrate, a plurality of trenches formed in the silicon nitride layer and the substrate, an oxide layer formed over the substrate, filling the trenches, wherein a width of the trenches in the dense region is smaller than that in the isolation region. A first polishing step is performed to remove a portion of the silicon oxide layer until a thickness of the remaining portion of the oxide layer reaches a predetermined thickness. A second polishing step is performed to remove a portion of the remaining portion of the silicon oxide layer until the silicon nitride layer is exposed.
    • 提供了一种用于形成浅沟槽隔离结构的浅沟槽隔离(STI)多级化学机械抛光(CMP)方法。 所述基板包括致密区域和隔离区域,在所述基板上形成的氮化硅层,形成在所述氮化硅层和所述基板中的多个沟槽,形成在所述基板上方的填充所述沟槽的氧化物层, 密集区域中的沟槽小于隔离区域中的沟槽。 执行第一抛光步骤以除去氧化硅层的一部分直到氧化物层的剩余部分的厚度达到预定厚度。 执行第二抛光步骤以去除氧化硅层的剩余部分的一部分,直到暴露氮化硅层。
    • 4. 发明授权
    • Polish method for semiconductor device planarization
    • 用于半导体器件平面化的抛光方法
    • US07172970B2
    • 2007-02-06
    • US10384641
    • 2003-03-11
    • Zong Huei LinArt YuChia Rung HsuTeng-Chun Tsai
    • Zong Huei LinArt YuChia Rung HsuTeng-Chun Tsai
    • H01L21/461H01L21/469
    • H01L21/7684H01L21/31053H01L21/76229H01L21/76232
    • A polish method for planarization is disclosed. The method uses a combination of a traditional oxide CMP and HSP-CMP (High Selectivity and Planarization) with a fix abrasive pad to meet the requirements of the CMP process for a device feature dimension under 0.18 micron even to 0.09 micron. By using a first polish step with a conventional polish pad and an oxide polish slurry, the non-uniformity of the over-fill thickness of the STI dielectric layer can be firstly removed and a much more smooth and uniform topography favorable for the HSP-CMP process the fix abrasive polishing pad can be obtained. Then the HSP-CMP process with the fix abrasive polishing pad can be performed to provide a planarized surface with accurate dimension control.
    • 公开了一种用于平坦化的抛光方法。 该方法使用传统氧化物CMP和HSP-CMP(高选择性和平面化)与固定磨料垫的组合,以满足在0.18微米甚至0.09微米下的器件特征尺寸的CMP工艺的要求。 通过使用具有常规抛光垫和氧化物抛光浆料的第一抛光步骤,可以首先除去STI介电层的过度填充厚度的不均匀性,并且对HSP-CMP有利的更平滑和均匀的形貌 可以获得固定磨料抛光垫的工艺。 然后可以执行具有固定磨料抛光垫的HSP-CMP工艺,以提供具有精确尺寸控制的平坦化表面。