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1. 发明授权

US09171834B2 Over voltage protection for a thin oxide load circuit 有权
标题翻译：用于薄氧化物负载电路的过压保护
公开(公告)号：US09171834B2
公开(公告)日：2015-10-27
申请号：US13690046
申请日：2012-11-30
申请人： Xinghai Tang , Hector Sanchez
发明人： Xinghai Tang , Hector Sanchez
IPC分类号： H02H9/04 , H05K3/30 , H01L27/02
CPC分类号： H01L27/0266 , H02H9/046 , Y10T29/4913
摘要： An IC includes: a substrate having a thick oxide portion and a thin oxide portion; a load circuit disposed on the thin oxide portion and coupled between a supply node and a virtual supply node; and a current source circuit and protection circuit disposed on the substrate. The current source circuit has an output coupled to the virtual supply node and is operable to provide a voltage at the virtual supply node. The protection circuit includes a sensing portion and a protection portion. The sensing portion is coupled to the virtual supply node and is operable to detect the voltage at the virtual supply node. The protection portion is coupled to the sensing portion and is operable, in response to the sensed voltage, to prevent a difference in voltage between the voltage at the virtual supply node and a second voltage at the supply node from exceeding a maximum voltage.
摘要翻译： IC包括：具有厚氧化物部分和薄氧化物部分的衬底; 负载电路，设置在所述薄氧化物部分上并且耦合在供应节点和虚拟供应节点之间; 以及设置在基板上的电流源电路和保护电路。电流源电路具有耦合到虚拟电源节点的输出，并且可操作以在虚拟电源节点处提供电压。保护电路包括感测部分和保护部分。感测部分耦合到虚拟供应节点并且可操作以检测虚拟供应节点处的电压。保护部分耦合到感测部分，并且响应于感测的电压可操作，以防止虚拟电源节点处的电压与供电节点处的第二电压之间的电压差超过最大电压。

2. 发明申请

US20140153148A1 OVER VOLTAGE PROTECTION FOR A THIN OXIDE LOAD CIRCUIT 有权
标题翻译：超过氧化物负载电路的电压保护
公开(公告)号：US20140153148A1
公开(公告)日：2014-06-05
申请号：US13690046
申请日：2012-11-30
申请人： XINGHAI TANG , HECTOR SANCHEZ
发明人： XINGHAI TANG , HECTOR SANCHEZ
IPC分类号： H02H9/04 , H05K3/30
CPC分类号： H01L27/0266 , H02H9/046 , Y10T29/4913
摘要： An IC includes: a substrate having a thick oxide portion and a thin oxide portion; a load circuit disposed on the thin oxide portion and coupled between a supply node and a virtual supply node; and a current source circuit and protection circuit disposed on the substrate. The current source circuit has an output coupled to the virtual supply node and is operable to provide a voltage at the virtual supply node. The protection circuit includes a sensing portion and a protection portion. The sensing portion is coupled to the virtual supply node and is operable to detect the voltage at the virtual supply node. The protection portion is coupled to the sensing portion and is operable, in response to the sensed voltage, to prevent a difference in voltage between the voltage at the virtual supply node and a second voltage at the supply node from exceeding a maximum voltage.
摘要翻译： IC包括：具有厚氧化物部分和薄氧化物部分的衬底; 负载电路，设置在所述薄氧化物部分上并且耦合在供应节点和虚拟供应节点之间; 以及设置在基板上的电流源电路和保护电路。电流源电路具有耦合到虚拟电源节点的输出，并且可操作以在虚拟电源节点处提供电压。保护电路包括感测部分和保护部分。感测部分耦合到虚拟供应节点并且可操作以检测虚拟供应节点处的电压。保护部分耦合到感测部分，并且响应于感测的电压可操作，以防止虚拟电源节点处的电压与供电节点处的第二电压之间的电压差超过最大电压。

3. 发明授权

US08558591B1 Phase locked loop with power supply control 有权
标题翻译：带电源控制的锁相环
公开(公告)号：US08558591B1
公开(公告)日：2013-10-15
申请号：US13629643
申请日：2012-09-28
申请人： Hector Sanchez , Xinghai Tang , Gayathri A. Bhagavatheeswaran
发明人： Hector Sanchez , Xinghai Tang , Gayathri A. Bhagavatheeswaran
IPC分类号： H03L7/06
CPC分类号： H03L7/18
摘要： A phase locked loop (PLL) includes a phase frequency detector powered by a first analog supply voltage; a charge pump powered by a second analog supply voltage, different from the first analog supply voltage; a voltage controlled oscillator (VCO) powered by a third analog supply voltage, different from the first and second analog supply voltages, wherein a frequency of the VCO is controlled by a control voltage; and a supply voltage provider having a first circuit node coupled to a fourth analog supply voltage, a second circuit node which provides the first analog supply voltage, a third circuit node which provides the second analog supply voltage, and a fourth circuit node which provides the third analog supply voltage, and a current compensator coupled to one of the second, third, or fourth circuit nodes, wherein the current compensator provides a variable current draw based on the control voltage.
摘要翻译：锁相环（PLL）包括由第一模拟电源电压供电的相位频率检测器; 由第一模拟电源电压供电的电荷泵，与第一模拟电源电压不同; 由与第一和第二模拟电源电压不同的第三模拟电源电压供电的压控振荡器（VCO），其中VCO的频率由控制电压控制; 以及电源电压提供器，具有耦合到第四模拟电源电压的第一电路节点，提供第一模拟电源电压的第二电路节点，提供第二模拟电源电压的第三电路节点和提供第二模拟电源电压的第四电路节点，第三模拟电源电压和耦合到第二，第三或第四电路节点之一的电流补偿器，其中电流补偿器基于控制电压提供可变电流汲取。

4. 发明授权

US08030983B2 Common mode tracking receiver 有权
标题翻译：共模跟踪接收器
公开(公告)号：US08030983B2
公开(公告)日：2011-10-04
申请号：US12484425
申请日：2009-06-15
申请人： Xinghai Tang , Hector Sanchez
发明人： Xinghai Tang , Hector Sanchez
IPC分类号： H03K3/00
CPC分类号： H03K5/1565 , H03K5/082 , H03L7/08
摘要： A clock receiver (301) on an integrated circuit (202) includes a programmable AC voltage divider (502) for receiving, through an input capacitor (406), a clock signal (206) from a clock generator (204) off the integrated circuit and for outputting a modified signal that has a reduced voltage swing, an inverter (440) coupled to the programmable voltage divider, and a common mode setting circuit (506), coupled to an input and an output of the inverter. The common mode setting circuit sets and maintains a common mode at the input of the inverter in response to a voltage at the input of the inverter and a voltage at the output of the inverter. The strength of transistors in the common mode tracking circuit tracks the strength of transistors in the inverter such that the common mode at the input to the inverter tracks a trip point of the inverter.
摘要翻译：集成电路（202）上的时钟接收器（301）包括可编程交流分压器（502），用于通过输入电容器（406）从时钟发生器（204）接收来自集成电路的时钟信号（206）并且用于输出具有降低的电压摆幅的修改信号，耦合到可编程分压器的反相器（440）和耦合到反相器的输入和输出的共模设置电路（506）。共模设定电路响应于逆变器输入端的电压和逆变器输出端的电压，在变频器的输入端设定并保持共模。共模跟踪电路中的晶体管的强度跟踪逆变器中的晶体管的强度，使得反相器输入端的共模跟踪逆变器的跳变点。

5. 发明申请

US20070008001A1 Cascadable level shifter cell 有权
公开(公告)号：US20070008001A1
公开(公告)日：2007-01-11
申请号：US11170398
申请日：2005-06-29
申请人： Hector Sanchez , Carlos Greaves , Jim Nissen , Xinghai Tang
发明人： Hector Sanchez , Carlos Greaves , Jim Nissen , Xinghai Tang
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113
摘要： A level shifter circuit including first and second circuits and a protection layer. The first circuit receives an input signal and switches first and second nodes to opposite states within a first voltage range between first and second supply voltages. The second circuit switches the third and fourth nodes to opposite states within a second voltage range between third and fourth supply voltages in response to switching of the first and second nodes. The protection layer couples the first and second nodes to third and fourth nodes via respective first and second isolation paths. The isolation paths operate to keep the first and second nodes within the first voltage range and to keep the third and fourth nodes within the second voltage range. Isolation enables the use of thin gate-oxide devices for speed while extending the voltage range beyond the maximum voltage allowable for a single thin gate-oxide device.

6. 发明申请

US20060197608A1 Fully programmable phase locked loop 有权
公开(公告)号：US20060197608A1
公开(公告)日：2006-09-07
申请号：US11069664
申请日：2005-03-01
申请人： Hector Sanchez , Carlos Greaves , Jim Nissen , Xinghai Tang
发明人： Hector Sanchez , Carlos Greaves , Jim Nissen , Xinghai Tang
IPC分类号： H03L7/00
CPC分类号： H03L7/0995 , H03K3/0377 , H03K5/084 , H03K5/133 , H03K2005/00071 , H03L7/0896
摘要： A programmable PLL including a receiver, a phase frequency detector, a charge pump, and a VCO. The receiver includes a programmable capacitor voltage divider that shifts voltage of an input clock to provide a level-shifted clock. The AC interface includes a state detection and correction circuit that ensures proper state of the level-shifted clock. The PLL includes a pulse delay modulator for generating delayed clock control signals. The VCO includes a programmable phase control circuit that dynamically adjusts phase using the delayed clock control signals. The VCO circuit includes a ring oscillator circuit with one or more phase control nodes. The programmable phase control circuit selectively couples devices to the phase control node using the clock control signals to adjust phase. The devices may be capacitors or transistors, each switched using switches controlled by the delayed clock control signals. The capacitors may be metal capacitors or semiconductor transistor capacitors.

7. 发明申请

US20060197563A1 Anti-gate leakage programmable capacitor 有权
标题翻译：防漏电可编程电容器
公开(公告)号：US20060197563A1
公开(公告)日：2006-09-07
申请号：US11069537
申请日：2005-03-01
申请人： Hector Sanchez , Xinghai Tang
发明人： Hector Sanchez , Xinghai Tang
IPC分类号： H03L7/06
CPC分类号： H03L7/093 , H03L7/0891
摘要： An anti-gate leakage programmable capacitor including at least one capacitor having a first terminal coupled to a first node and a second terminal, a second node, and a control circuit which selectively couples the second terminal of the capacitor to the second node or which drives the second terminal to the same voltage as the first node. In one embodiment, the programmable capacitor includes multiple capacitors, an amplifier having an input coupled to the first node and an output, and a switch circuit coupled to the second node, to each second terminal of each capacitor and to the amplifier output. The switch circuit selectively switches each second terminal of each capacitor between the amplifier output and the second node. The switch circuit may include pairs of switches each controlled by a corresponding select signal to selectively switch a corresponding capacitor between the reference node and the output of the amplifier.
摘要翻译：一种防栅泄漏可编程电容器，包括至少一个具有耦合到第一节点的第一端子和第二端子的电容器，第二节点和控制电路，其选择性地将电容器的第二端子耦合到第二节点或驱动第二端子与第一节点具有相同的电压。在一个实施例中，可编程电容器包括多个电容器，具有耦合到第一节点的输入和输出的放大器，以及耦合到第二节点的开关电路，到每个电容器的每个第二端子和放大器输出端。开关电路有选择地在放大器输出端和第二节点之间切换每个电容器的每个第二端子。开关电路可以包括开关对，每对开关由相应的选择信号控制，以选择性地在参考节点和放大器的输出之间切换相应的电容器。

8. 发明申请

US20070001716A1 High speed output buffer with AC-coupled level shift and DC level detection and correction 有权
公开(公告)号：US20070001716A1
公开(公告)日：2007-01-04
申请号：US11169862
申请日：2005-06-29
申请人： Hector Sanchez , Xinghai Tang , Carlos Greaves , Jim Nissen
发明人： Hector Sanchez , Xinghai Tang , Carlos Greaves , Jim Nissen
IPC分类号： H03B1/00
CPC分类号： H03K19/00315 , H03K19/018585
摘要： A high speed output buffer including an input circuit providing first and second signals within a first voltage range having a first common mode voltage, an AC interface receiving the first and second signals and providing first and second preliminary drive signals, a detection and correction circuit that corrects a state of the first preliminary drive signal AC coupled to the first signal, first and second drive circuits receiving the preliminary drive signals and providing first and second drive signals, where the first drive circuit operates within a second voltage range having a greater common mode voltage and where the second drive circuit operates within a third voltage range, and an output that switches an output node within a voltage range that is greater than a maximum voltage range. The first, second and third voltage ranges are each within the maximum voltage range suitable for thin-gate devices.

9. 发明授权

US09209819B2 Phase locked loop with burn-in mode 有权
标题翻译：带有老化模式的锁相环
公开(公告)号：US09209819B2
公开(公告)日：2015-12-08
申请号：US13627333
申请日：2012-09-26
申请人： Xinghai Tang , Gayathri A. Bhagavatheeswaran , Hector Sanchez
发明人： Xinghai Tang , Gayathri A. Bhagavatheeswaran , Hector Sanchez
IPC分类号： H03L7/06 , H03L7/089 , H03L7/099
CPC分类号： H03L7/0891 , H03L7/0995
摘要： A phase locked loop having a normal mode and a burn-in mode. The logic portion is coupled to a logic power supply terminal and includes a clock receiver coupled to a phase frequency detector. The analog portion has a charge pump coupled to the phase frequency detector and to an analog power supply terminal. The analog portion also has a voltage controlled oscillator coupled to the charge pump at an analog node and to the analog power supply terminal. The phase locked loop has a node control circuit that is coupled to the analog node during the burn-in mode that controls a voltage at the analog node sufficiently below a voltage at the analog power supply terminal to avoid over-stressing the charge pump and the voltage controlled oscillator during the burn-in mode.
摘要翻译：具有正常模式和老化模式的锁相环。逻辑部分耦合到逻辑电源端子并且包括耦合到相位频率检测器的时钟接收器。模拟部分具有耦合到相位频率检测器和模拟电源端子的电荷泵。模拟部分还具有耦合到模拟节点处的电荷泵和模拟电源端子的压控振荡器。锁相环具有在老化模式期间耦合到模拟节点的节点控制电路，其控制在模拟节点处的电压足够低于模拟电源端子处的电压，以避免电荷泵的过度应力和老化模式下的压控振荡器。

10. 发明授权

US08766680B2 Voltage translation circuit 有权
标题翻译：电压转换电路
公开(公告)号：US08766680B2
公开(公告)日：2014-07-01
申请号：US13627327
申请日：2012-09-26
申请人： Xinghai Tang , Gayathri A. Bhagavatheeswaran , Hector Sanchez
发明人： Xinghai Tang , Gayathri A. Bhagavatheeswaran , Hector Sanchez
IPC分类号： H03L7/06 , H03L5/00
CPC分类号： H03L7/0995
摘要： A voltage translation circuit (116) provides an output analog voltage signal that has a translated voltage of the voltage of an input analog voltage signal over a range of values of the input analog voltage signal. The voltage translation circuit includes an input stage (202) having a circuit node and an input transistor (210) coupled between the circuit node and a power supply terminal, wherein a gate of the input transistor is coupled to receive the input analog voltage signal; a current path circuit (204) in parallel with the input transistor, wherein the current path includes a first transistor coupled between the circuit node and the power supply terminal; and a circuit coupled to provide a variable body bias voltage to a body of the first transistor.
摘要翻译：电压转换电路（116）提供输出模拟电压信号，其在输入模拟电压信号的值的范围内具有输入模拟电压信号的电压的转换电压。电压转换电路包括具有电路节点和耦合在电路节点与电源端子之间的输入晶体管（210）的输入级（202），其中输入晶体管的栅极耦合以接收输入模拟电压信号; 与所述输入晶体管并联的电流路径电路（204），其中所述电流路径包括耦合在所述电路节点和所述电源端子之间的第一晶体管; 以及耦合以向第一晶体管的主体提供可变主体偏置电压的电路。

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