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1. 发明授权

US6159834A Method of forming a gate quality oxide-compound semiconductor structure 失效
标题翻译：形成栅极氧化物半导体结构的方法
公开(公告)号：US6159834A
公开(公告)日：2000-12-12
申请号：US22595
申请日：1998-02-12
申请人： Zhiyi (Jimmy) Yu , Matthias Passlack , Brian Bowers , Corey Daniel Overgaard , Ravindranath Droopad , Jonathan Kwadwo Abrokwah
发明人： Zhiyi (Jimmy) Yu , Matthias Passlack , Brian Bowers , Corey Daniel Overgaard , Ravindranath Droopad , Jonathan Kwadwo Abrokwah
IPC分类号： H01L21/28 , H01L21/316 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28264 , H01L21/31604 , H01L21/31666
摘要： A gate quality oxide-compound semiconductor structure (10) is formed by the steps of providing a III-V compound semiconductor wafer structure (13) with an atomically ordered and chemically clean semiconductor surface in an ultra high vacuum (UHV) system (20), directing a molecular beam (26) of gallium oxide onto the surface of the wafer structure to initiate the oxide deposition, and providing a second beam (28) of atomic oxygen to form a Ga.sub.2 O.sub.3 layer (14) with low defect density on the surface of the wafer structure. The second beam of atomic oxygen is supplied upon completion of the first 1-2 monolayers of Ga.sub.2 O.sub.3. The molecular beam of gallium oxide is provided by thermal evaporation from a crystalline Ga.sub.2 O.sub.3 or gallate source, and the atomic beam of oxygen is provided by either RF or microwave plasma discharge, thermal dissociation, or a neutral electron stimulated desorption atom source.
摘要翻译：通过在超高真空（UHV）系统（20）中提供具有原子级和化学清洁的半导体表面的III-V化合物半导体晶片结构（13）的步骤形成栅极质量氧化物 - 化合物半导体结构（10）将氧化镓的分子束（26）引导到晶片结构的表面上以引发氧化物沉积，以及提供原子氧的第二光束（28）以在表面上形成具有低缺陷密度的Ga 2 O 3层（14）的晶片结构。当第一个1-2单层的Ga2O3完成时，第二个原子氧束被提供。通过从结晶Ga 2 O 3或没食子酸酯源的热蒸发提供氧化镓的分子束，并且氧原子束由RF或微波等离子体放电，热解离或中性电子刺激的解吸原子源提供。

2. 发明授权

US6094295A Ultraviolet transmitting oxide with metallic oxide phase and method of fabrication 失效
标题翻译：具有金属氧化物相的紫外线透射氧化物及其制造方法
公开(公告)号：US6094295A
公开(公告)日：2000-07-25
申请号：US022703
申请日：1998-02-12
申请人： Matthias Passlack , Jonathan Kwadwo Abrokwah , Zhiyi Jimmy Yu
发明人： Matthias Passlack , Jonathan Kwadwo Abrokwah , Zhiyi Jimmy Yu
IPC分类号： C23C14/08 , H01L21/316 , H01L31/0224 , H01L31/18 , G02F1/00 , B05D3/06 , H01L21/31 , H01L29/94
CPC分类号： C23C14/08 , H01L21/31604 , H01L31/022466 , H01L31/1884 , Y02E10/50
摘要： An electro-conductive ultraviolet light transmitting Ga.sub.2 O.sub.3 material (10) with a metallic oxide phase is deposited on a GaAs substrate or supporting structure (12). The Ga.sub.2 O.sub.3 material or thin layer comprises a minor component of metallic IrO.sub.2. The Ga.sub.2 O.sub.3 thin layer may be positioned using thermal evaporation (106) of Ga.sub.2 O.sub.3 or of a Ga.sub.2 O.sub.3 containing a compound from an Iridium crucible (108). Alternatively, the Ir may be co-evaporated (110) by electron beam evaporation. The electro-conductive ultraviolet light transmitting material Ga.sub.2 O.sub.3 with a metallic oxide phase is suitable for use on solar cells and in laser lithography.
摘要翻译：在GaAs衬底或支撑结构（12）上沉积具有金属氧化物相的透射Ga 2 O 3材料（10）的导电紫外光。 Ga 2 O 3材料或薄层包含金属IrO 2的次要组分。可以使用Ga 2 O 3的热蒸发（106）或含有来自铱坩埚（108）的化合物的Ga 2 O 3来定位Ga 2 O 3薄层。或者，Ir可以通过电子束蒸发共蒸发（110）。具有金属氧化物相的导电紫外线透射材料Ga 2 O 3适用于太阳能电池和激光光刻。

3. 发明授权

US5945718A Self-aligned metal-oxide-compound semiconductor device and method of fabrication 失效
标题翻译：自对准金属氧化物半导体器件及其制造方法
公开(公告)号：US5945718A
公开(公告)日：1999-08-31
申请号：US22593
申请日：1998-02-12
申请人： Matthias Passlack , Jonathan Kwadwo Abrokwah , Zhiyi Yu
发明人： Matthias Passlack , Jonathan Kwadwo Abrokwah , Zhiyi Yu
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51 , H07L29/78
CPC分类号： H01L29/517 , H01L21/28158 , H01L29/66522
摘要： A self-aligned enhancement mode metal-oxide-compound semiconductor FET (10) includes a stoichiometric Ga.sub.2 O.sub.3 gate oxide layer (14) positioned on upper surface (16) of a compound semiconductor wafer structure (13). The stoichiometric Ga.sub.2 O.sub.3 layer forms an atomically abrupt interface with the compound semiconductor wafer structure. A refractory metal gate electrode (17) is positioned on upper surface (18) of the stoichiometric Ga.sub.2 O.sub.3 gate oxide layer (14). The refractory metal is stable on the stoichiometric Ga.sub.2 O.sub.3 gate oxide layer at elevated temperature. Self-aligned source and drain areas, and source and drain contacts (19, 20) are positioned on the source and drain areas (21, 22).
摘要翻译：自对准增强型金属氧化物半导体FET（10）包括位于化合物半导体晶片结构（13）的上表面（16）上的化学计量的Ga 2 O 3栅极氧化物层（14）。化学计量的Ga 2 O 3层与化合物半导体晶片结构形成原子突变的界面。难熔金属栅电极（17）位于化学计量的Ga 2 O 3栅极氧化物层（14）的上表面（18）上。难熔金属在高温下在化学计量的Ga 2 O 3栅极氧化物层上是稳定的。自对准源极和漏极区以及源极和漏极接触（19,20）位于源极和漏极区域（21,22）上。

4. 发明授权

US06359294B1 Insulator-compound semiconductor interface structure 失效
标题翻译：绝缘体 - 复合半导体界面结构
公开(公告)号：US06359294B1
公开(公告)日：2002-03-19
申请号：US08812952
申请日：1997-03-04
申请人： Matthias Passlack , Jun Wang , Jonathan K. Abrokwah , Zhiyi Jimmy Yu
发明人： Matthias Passlack , Jun Wang , Jonathan K. Abrokwah , Zhiyi Jimmy Yu
IPC分类号： H01L2976
CPC分类号： H01L29/517 , H01L21/28158 , H01L21/28264 , H01L29/66462 , H01L29/802
摘要： An insulator-compound semiconductor interface structure is disclosed including compound semiconductor material with a spacer layer of semiconductor material having a bandgap which is wider than the bandgap of the compound semiconductor material positioned on a surface of the compound semiconductor material and an insulating layer positioned on the spacer layer. Minimum and maximum thicknesses of the spacer layer are determined by the penetration of the carrier wave function into the spacer layer and by the desired device performance. In a specific embodiment, the interface structure is formed in a multi-wafer epitaxial production system including a transfer and load module with a III-V growth chamber attached and an insulator chamber attached.
摘要翻译：公开了一种绝缘体 - 化合物半导体界面结构，其包括具有半导体材料的隔离层的化合物半导体材料，该间隔层具有比位于化合物半导体材料的表面上的化合物半导体材料的带隙宽的带隙和位于化合物半导体材料的表面上的绝缘层间隔层。间隔层的最小和最大厚度由载波函数穿入间隔层和所需器件性能决定。在具体实施例中，界面结构形成在多晶片外延生产系统中，该系统包括连接有III-V生长室的传输和负载模块，并连接有绝缘体室。

5. 发明授权

US5907792A Method of forming a silicon nitride layer 失效
标题翻译：形成氮化硅层的方法
公开(公告)号：US5907792A
公开(公告)日：1999-05-25
申请号：US917122
申请日：1997-08-25
申请人： Ravi Droopad , Jonathan K. Abrokwah , Matthias Passlack , Zhiyi Jimmy Yu
发明人： Ravi Droopad , Jonathan K. Abrokwah , Matthias Passlack , Zhiyi Jimmy Yu
IPC分类号： C23C14/06 , H01L21/318 , H01L29/78
CPC分类号： C23C14/0652 , H01L21/3185 , Y10S148/169 , Y10S438/961
摘要： A method of forming a silicon nitride layer or film on a semiconductor wafer structure includes forming a silicon nitride layer on the surface of a wafer structure using a molecular beam of high purity elemental Si and an atomic beam of high purity nitrogen. In a preferred embodiment, a III-V compound semiconductor wafer structure is heated in an ultra high vacuum system to a temperature below the decomposition temperature of said compound semiconductor wafer structure and a silicon nitride layer is formed using a molecular beam of Si provided by either thermal evaporation or electron beam evaporation, and an atomic nitrogen beam provided by either RF or microwave plasma discharge.
摘要翻译：在半导体晶片结构上形成氮化硅层或膜的方法包括使用高纯度元素Si的分子束和高纯氮原子束在晶片结构的表面上形成氮化硅层。在优选实施例中，III-V族化合物半导体晶片结构在超高真空系统中被加热至低于所述化合物半导体晶片结构的分解温度的温度，并且使用由以下两者之一提供的Si的分子束形成氮化硅层热蒸发或电子束蒸发，以及由RF或微波等离子体放电提供的原子氮光束。

6. 发明授权

US5902130A Thermal processing of oxide-compound semiconductor structures 失效
标题翻译：氧化物半导体结构的热处理
公开(公告)号：US5902130A
公开(公告)日：1999-05-11
申请号：US896234
申请日：1997-07-17
申请人： Matthias Passlack , Jonathan K. Abrokwah , Zhiyi Jimmy Yu
发明人： Matthias Passlack , Jonathan K. Abrokwah , Zhiyi Jimmy Yu
IPC分类号： H01L21/265 , H01L21/336 , H01L29/51 , H01L21/28
CPC分类号： H01L21/26553 , H01L29/66522 , H01L29/517 , H01L29/518
摘要： A method of thermal processing a supporting structure comprised of various compound semiconductor layers having a Gd free Ga.sub.2 O.sub.3 surface layer including coating the surface layer with a dielectric or a metallic cap layer or combinations thereof, such that the low D.sub.it Ga.sub.2 O.sub.3 -compound semiconductor structure is conserved during thermal processing, e.g. during activation of ion implants of a self aligned metal-oxide-compound semiconductor gate structure. In a preferred embodiment, the semiconductor structure has a surface of GaAs, the Gd free Ga.sub.2 O.sub.3 layer has a thickness in a range of approximately 1 nm to 20 nm, and the insulating or metallic cap layer has a thickness in a range of approximately 1 nm to 500 nm.
摘要翻译：一种热处理由具有Gd游离Ga 2 O 3表面层的各种化合物半导体层构成的支撑结构的方法，包括用电介质或金属覆盖层或其组合涂覆表面层，使得低Dit Ga 2 O 3化合物半导体结构被保守在热处理过程中，例如在自对准的金属氧化物 - 化合物半导体栅极结构的离子注入的激活期间。在优选实施例中，半导体结构具有GaAs的表面，Gd自由的Ga 2 O 3层的厚度在约1nm至20nm的范围内，并且绝缘或金属覆盖层的厚度在约1nm的范围内至500nm。

7. 发明申请

US20090085073A1 MOSFET STRUCTURE AND METHOD OF MANUFACTURE 有权
标题翻译： MOSFET结构及其制造方法
公开(公告)号：US20090085073A1
公开(公告)日：2009-04-02
申请号：US11864274
申请日：2007-09-28
申请人： Ravindranath Droopad , Matthias Passlack
发明人： Ravindranath Droopad , Matthias Passlack
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28264 , H01L29/517
摘要： A method of forming a portion (10) of a compound semiconductor MOSFET structure comprises forming a compound semiconductor layer structure (14) and an oxide layer (20) overlying the same. Forming the compound semiconductor structure (14) includes forming at least one channel material (16) and a group-III rich surface termination layer (18) overlying the at least one channel material. Forming the oxide layer (20) includes forming the oxide layer to overlie the group-III rich surface termination layer and comprises one of (a) depositing essentially congruently evaporating oxide of at least one of (a(i)) a ternary oxide and (a(ii)) an oxide more complex than a ternary oxide and (b) depositing oxide molecules, with use of at least one of (b(i)) a ternary oxide and (b(ii)) an oxide more complex than a ternary oxide.
摘要翻译：形成化合物半导体MOSFET结构的部分（10）的方法包括：形成化合物半导体层结构（14）和覆盖其上的氧化物层（20）。形成化合物半导体结构（14）包括形成至少一个沟道材料（16）和覆盖至少一个沟道材料的III族富集表面终止层（18）。形成氧化物层（20）包括形成氧化物层以覆盖III族富集表面终止层，并且包括（a）基本上一致地沉积（a（i））三元氧化物和（（ii））比三元氧化物更复杂的氧化物和（b）使用（b（i））三元氧化物和（b（ii））中的至少一种沉积氧化物分子，其比三元氧化物。

8. 发明申请

US20060030098A1 Method of forming an oxide layer on a compound semiconductor structure 有权
标题翻译：在化合物半导体结构上形成氧化物层的方法
公开(公告)号：US20060030098A1
公开(公告)日：2006-02-09
申请号：US11239749
申请日：2005-09-30
申请人： Ravindranath Droopad , Matthias Passlack
发明人： Ravindranath Droopad , Matthias Passlack
IPC分类号： H01L21/8238
CPC分类号： H01L21/02266 , H01L21/02175 , H01L21/022 , H01L21/28264 , H01L21/31604 , H01L29/20 , H01L29/513 , H01L29/78
摘要： A method of forming a dielectric layer structure on a supporting semiconductor structure having a first surface comprises providing a first beam of oxide; depositing a first layer of oxide on the first surface of the supporting semiconductor structure using the first beam of oxide, wherein the first layer of oxide has a second surface; terminating the first beam of oxide, and concurrently providing a second beam of oxide, a beam of metal and a beam of oxygen, wherein the first and second beams of oxide are separate and distinct beams of oxide; and depositing a second layer of oxide on the second surface simultaneously using the second beam of oxide, the beam of metal, and the beam of oxygen.
摘要翻译：在具有第一表面的支撑半导体结构上形成电介质层结构的方法包括：提供第一氧化物束; 使用第一氧化物束在支撑半导体结构的第一表面上沉积第一层氧化物，其中所述第一氧化物层具有第二表面; 终止第一氧化物束，并且同时提供第二氧化物束，金属梁和氧束，其中所述第一和第二氧化物束是分离的和不同的氧化物束; 以及使用所述第二氧化物束，所述金属束和所述氧束将所述第二表面的氧化物沉积在所述第二表面上。

9. 发明授权

US08847280B2 Insulated gate field effect transistors 有权
标题翻译：绝缘栅场效应晶体管
公开(公告)号：US08847280B2
公开(公告)日：2014-09-30
申请号：US13293910
申请日：2011-11-10
申请人： Jonathan K. Abrokwah , Ravindranath Droopad , Matthias Passlack
发明人： Jonathan K. Abrokwah , Ravindranath Droopad , Matthias Passlack
IPC分类号： H01L29/78 , H01L23/31 , H01L29/778 , H01L29/51 , H01L29/207
CPC分类号： H01L29/7783 , H01L23/3192 , H01L29/207 , H01L29/513 , H01L2924/0002 , H01L2924/12044 , H01L2924/13091 , H01L2924/00
摘要： An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
摘要翻译：通过提供期望地包括III-V半导体的衬底来获得改进的绝缘栅场效应器件，所述衬底在衬底上具有另外的半导体层，其适于在形成在半导体层上的间隔开的源 - 漏电极之间容纳器件的沟道。在半导体层上形成介电层。在电介质层上形成密封层并暴露于氧等离子体。在源 - 漏电极之间的电介质层上形成栅电极。电介质层优选包含氧化镓和/或钆 - 镓氧化物，氧等离子体优选为电感耦合等离子体。希望在密封层的上方设置另外的例如氮化硅的密封层。否则对泄漏和通道薄层电阻有不利影响的表面状态和栅极电介质阱将大大减少。

10. 发明授权

US08105925B2 Method for forming an insulated gate field effect device 有权
标题翻译：一种形成绝缘栅场效应器件的方法
公开(公告)号：US08105925B2
公开(公告)日：2012-01-31
申请号：US12182349
申请日：2008-07-30
申请人： Jonathan K. Abrokwah , Ravindranath Droopad , Matthias Passlack
发明人： Jonathan K. Abrokwah , Ravindranath Droopad , Matthias Passlack
IPC分类号： H01L21/26
CPC分类号： H01L29/7783 , H01L23/3192 , H01L29/207 , H01L29/513 , H01L2924/0002 , H01L2924/12044 , H01L2924/13091 , H01L2924/00
摘要： An improved insulated gate field effect device (60) is obtained by providing a substrate (20) desirably comprising a III-V semiconductor, having a further semiconductor layer (22) on the substrate (20) adapted to contain the channel (230) of the device (60) between spaced apart source-drain electrodes (421, 422) formed on the semiconductor layer (22). A dielectric layer (24) is formed on the semiconductor layer (22). A sealing layer (28) is formed on the dielectric layer (24) and exposed to an oxygen plasma (36). A gate electrode (482) is formed on the dielectric layer (24) between the source-drain electrodes (421, 422). The dielectric layer (24) preferably comprises gallium-oxide (25) and/or gadolinium-gallium oxide (26, 27), and the oxygen plasma (36) is preferably an inductively coupled plasma. A further sealing layer (44) of, for example, silicon nitride is desirably provided above the sealing layer (28). Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
摘要翻译：通过提供期望地包括III-V半导体的衬底（20）来获得改进的绝缘栅场效应器件（60），所述衬底（20）在所述衬底（20）上具有另外的半导体层（22），所述半导体层适于容纳所述沟道（230）所述器件（60）形成在所述半导体层（22）上形成的间隔开的源 - 漏电极（421,422）之间。在半导体层（22）上形成介电层（24）。密封层（28）形成在电介质层（24）上并暴露于氧等离子体（36）。在源漏电极（421,422）之间的电介质层（24）上形成栅电极（482）。电介质层（24）优选包含氧化镓（25）和/或氧化钆 - 氧化镓（26,27），氧等离子体（36）优选为电感耦合等离子体。期望地在密封层（28）的上方设置例如氮化硅的另外的密封层（44）。否则对泄漏和通道薄层电阻有不利影响的表面状态和栅极电介质阱将大大减少。

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