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    • 2. 发明授权
      US07243254B1 Low power memory controller that is adaptable to either double data rate DRAM or single data rate synchronous DRAM circuits 有权
    • Low power memory controller that is adaptable to either double data rate DRAM or single data rate synchronous DRAM circuits
    • 低功耗存储器控制器，适用于双数据速率DRAM或单数据速率同步DRAM电路
    • US07243254B1
    • 2007-07-10
    • US10701639
    • 2003-11-05
    • Vijendra Kuroodi , Geeta Desai , Eric Hung
    • Vijendra Kuroodi , Geeta Desai , Eric Hung
    • G06F1/04
    • G06F13/1694
    • A memory controller is provided and a method for transferring data between the memory controller and a memory device. The memory controller can be implemented on an integrated circuit that also contains an execution unit. The execution unit can be clocked at a first clock rate, whereas the memory controller can be selectively clocked at either the first clock rate or a second clock rate that is approximately one-half frequency of the first clock rate. By clocking the memory controller at either the first clock rate or the second clock rate, the memory controller can accommodate different types of semiconductor memory. For example, the memory controller can control single data rate (SDR) DRAM memory if it is clocked at a first clock rate. Conversely, the memory controller can control double data rate (DDR) DRAM memory if it is clocked at approximately one-half the first clock rate. By selectively clocking the memory controller at different clocking rates, the memory controller need not be modified in hardware, yet can accommodate different memory devices by allowing a user to simply plug one type of memory into a receptacle rather than another depending on the cost constraints and user application. Therefore, the memory controller is adaptable during a power-on reset in which the computer system is initialized to automatically receive and control different types of memory selected by a user.
    • 提供了存储器控制器和用于在存储器控制器和存储器件之间传送数据的方法。 存储器控制器可以在还包含执行单元的集成电路上实现。 可以以第一时钟速率对执行单元进行计时，而存储器控制器可以以第一时钟速率或大约为第一时钟速率的大约二分之一频率的第二时钟速率选择性地计时。 通过以第一时钟速率或第二时钟速率对存储器控制器进行计时，存储器控制器可以适应不同类型的半导体存储器。 例如，如果存储器控制器以第一时钟速率被计时，则可以控制单数据速率（SDR）DRAM存储器。 相反，如果存储器控制器的时钟频率约为第一个时钟速率的一半，则存储器控制器可以控制双倍数据速率（DDR）DRAM存储器。 通过以不同的时钟速率有选择地对存储器控制器进行定时，存储器控制器不需要在硬件中进行修改，而是可以通过允许用户根据成本限制简单地将一种类型的存储器插入存储器而不是另一种存储器来容纳不同的存储器件 用户应用程序。 因此，存储器控制器在上电复位期间是可适应的，其中计算机系统被初始化以自动接收和控制由用户选择的不同类型的存储器。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US07409572B1 Low power memory controller with leaded double data rate DRAM package arranged on a two layer printed circuit board 有权
    • Low power memory controller with leaded double data rate DRAM package arranged on a two layer printed circuit board
    • 低功耗存储控制器，带有双重数据速率DRAM封装，布置在双层印刷电路板上
    • US07409572B1
    • 2008-08-05
    • US10728492
    • 2003-12-05
    • Eric Hung , Geeta K. Desai , Vijendra Kuroodi , Alexander Miretsky , Mirko Vojnovic
    • Eric Hung , Geeta K. Desai , Vijendra Kuroodi , Alexander Miretsky , Mirko Vojnovic
    • G06F1/00 , G06F1/04 , G06F1/12
    • G06F1/3203 , G06F1/324 , G06F1/3275 , Y02D10/126 , Y02D10/14
    • An integrated circuit is provided that includes an execution engine and a memory controller. The execution engine is clocked at a first rate and the memory controller is clocked at a second rate that is less than the first rate. Pins on the integrated circuit can transfer data to and from the integrated circuit on both the rising and falling edges of a second clock transitioning at the second clock rate. The integrated circuit is preferably packaged using a lead frame and wire bonds extending from pads on the integrated circuit to corresponding leads. The leads are secured to trace conductors on a surface of a printed circuit board. The board contains no more than two conductive layers separated by a dielectric layer. Thus, an overall electronic system is formed having a board with no more than two conductive layers, an execution engine that receives a first clock signal, a memory controller which receives a second clock signal, and a memory device that sends data to and from the memory controller at twice the rate of the second clock signal. Using a throttled second clock signal allows for less expensive packaging and mounting of packaged integrated circuits on a less expensive PCB, while still maintaining use of a DDR DRAM transfer mechanism.
    • 提供了一种集成电路，其包括执行引擎和存储器控制器。 执行引擎以第一速率进行计时，并且存储器控制器以小于第一速率的第二速率被计时。 集成电路上的引脚可以以第二个时钟速率转换的第二个时钟的上升沿和下降沿将数据传输到集成电路和从集成电路传输数据。 集成电路优选地使用引线框封装，并且引线键从集成电路上的焊盘延伸到相应的引线。 引线固定到印刷电路板表面上的迹线导体上。 该电路板包含不超过两个由电介质层分离的导电层。 因此，整体电子系统形成为具有不超过两个导电层的板，接收第一时钟信号的执行引擎，接收第二时钟信号的存储器控​​制器以及向其发送数据的存储器件 存储器控制器是第二个时钟信号速率的两倍。 使用节流的第二时钟信号允许在廉价的PCB上封装和安装封装的集成电路，同时仍然保持使用DDR DRAM传输机制。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US07023719B1 Memory module having mirrored placement of DRAM integrated circuits upon a four-layer printed circuit board 有权
    • Memory module having mirrored placement of DRAM integrated circuits upon a four-layer printed circuit board
    • 存储器模块将DRAM集成电路的镜像放置在四层印刷电路板上
    • US07023719B1
    • 2006-04-04
    • US10692091
    • 2003-10-23
    • Eric Hung , Norman Sai
    • Eric Hung , Norman Sai
    • G11C5/06
    • H05K1/181 , G11C5/04 , G11C5/063 , H05K2201/10545 , Y02P70/611
    • A memory module is provided as well as a method for forming a memory module. The memory module includes a printed circuit board having opposed first and second outside surfaces. At least one via can extend through the printed circuit board and couples a conductor on one outside surface to a conductor on another outside surface. A semiconductor memory device on one of those outside surfaces can thereby be connected to one end of the via, with another semiconductor memory device on the opposing outside surface connected to the other end of the via. Preferably, the pair of memory devices are placed on a portion of each respective outside surface so that they essentially align in mirrored fashion with each other. Accordingly, any vias which extend from the footprint of one memory device will take the shortest path to the footprint of the other memory device, with the stubs between the footprint and the via being of essentially the same length and relatively short. The printed circuit board preferably has no more than four conductive layers dielectrically spaced from each other. Two layers are reserved for the opposing outer surfaces, and two layers carrying power and ground signals are embedded within the board. The memory devices are preferably DDR SDRAMs connected to each other as well as a memory controller, each of are placed and maintained upon a single printed circuit board.
    • 提供存储器模块以及用于形成存储器模块的方法。 存储器模块包括具有相对的第一和第二外表面的印刷电路板。 至少一个通孔可以延伸穿过印刷电路板，并将一个外表面上的导体连接到另一个外表面上的导体。 因此，其中一个外表面上的半导体存储器件可以连接到通孔的一端，另一半导体存储器件在相对的外表面上连接到通孔的另一端。 优选地，一对存储器件被放置在每个相应的外表面的一部分上，使得它们基本上以镜像方式彼此对准。 因此，从一个存储器件的占位面延伸的任何通孔将采取到另一存储器件的覆盖区的最短路径，其中覆盖区和通孔之间的短截线基本上相同的长度并且相对较短。 印刷电路板优选地具有不超过四个彼此介电间隔的导电层。 为相对的外表面预留两层，并且承载电力和接地信号的两层嵌入在电路板内。 存储器件优选地彼此连接的DDR SDRAM以及存储器控制器，每个存储器控制器被放置并保持在单个印刷电路板上。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US07657774B1 Low power memory controller with leaded double data rate DRAM package on a two layer printed circuit board 有权
    • Low power memory controller with leaded double data rate DRAM package on a two layer printed circuit board
    • 低功耗存储控制器，采用双层数据速率DRAM封装在双层印刷电路板上
    • US07657774B1
    • 2010-02-02
    • US12140144
    • 2008-06-16
    • Eric Hung , Geeta K. Desai , Vijendra Kuroodi , Alexander Miretsky , Mirko Vojnovic
    • Eric Hung , Geeta K. Desai , Vijendra Kuroodi , Alexander Miretsky , Mirko Vojnovic
    • G06F1/00 , G06F1/04 , G06F12/00 , H05K1/00
    • G06F1/3203 , G06F1/324 , G06F1/3275 , Y02D10/126 , Y02D10/14
    • An integrated circuit is provided that includes an execution engine and a memory controller. The execution engine is clocked at a first rate and the memory controller is clocked at a second rate that is less than the first rate. Pins on the integrated circuit can transfer data to and from the integrated circuit on both the rising and falling edges of a second clock transitioning at the second clock rate. The integrated circuit is preferably packaged using a lead frame and wire bonds extending from pads on the integrated circuit to corresponding leads. The leads are secured to trace conductors on a surface of a printed circuit board. The board contains no more than two conductive layers separated by a dielectric layer. Thus, an overall electronic system is formed having a board with no more than two conductive layers, an execution engine that receives a first clock signal, a memory controller which receives a second clock signal, and a memory device that sends data to and from the memory controller at twice the rate of the second clock signal. Using a throttled second clock signal allows for less expensive packaging and mounting of packaged integrated circuits on a less expensive PCB, while still maintaining use of a DDR DRAM transfer mechanism.
    • 提供了一种集成电路，其包括执行引擎和存储器控制器。 执行引擎以第一速率进行计时，并且存储器控制器以小于第一速率的第二速率被计时。 集成电路上的引脚可以以第二个时钟速率转换的第二个时钟的上升沿和下降沿将数据传输到集成电路和从集成电路传输数据。 集成电路优选地使用引线框封装，并且引线键从集成电路上的焊盘延伸到相应的引线。 引线固定到印刷电路板表面上的迹线导体上。 该电路板包含不超过两个由电介质层分离的导电层。 因此，整体电子系统形成为具有不超过两个导电层的板，接收第一时钟信号的执行引擎，接收第二时钟信号的存储器控​​制器以及向其发送数据的存储器件 存储器控制器是第二个时钟信号速率的两倍。 使用节流的第二时钟信号允许在廉价的PCB上封装和安装封装的集成电路，同时仍然保持使用DDR DRAM传输机制。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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