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1. 发明授权

US07340634B2 Real time clock architecture and/or method for a system on a chip (SOC) application 失效
标题翻译：用于片上系统（SOC）应用的实时时钟架构和/或方法
公开(公告)号：US07340634B2
公开(公告)日：2008-03-04
申请号：US10929011
申请日：2004-08-27
申请人： Ho-Ming Leung , Remi C. Lenoir , Zoltan Toth , Daniel S. Perrin , Eric Hung , Timothy J. Wilson
发明人： Ho-Ming Leung , Remi C. Lenoir , Zoltan Toth , Daniel S. Perrin , Eric Hung , Timothy J. Wilson
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： An apparatus comprising a first portion, a second portion and a processor. The first portion is configured to generate a count signal in response to a number of oscillations of a clock signal. The first portion is powered by an unswitched power source. The second portion is configured to generate an interrupt signal in response to the count signal and a predetermined stored value. The second portion is powered by a switched power source. The processor is configured to (i) receive the interrupt signal and (ii) generate the switched power.
摘要翻译：一种包括第一部分，第二部分和处理器的装置。第一部分被配置为响应于时钟信号的振荡的数量产生计数信号。第一部分由未切换的电源供电。第二部分被配置为响应于计数信号和预定的存储值产生中断信号。第二部分由开关电源供电。处理器被配置为（i）接收中断信号和（ii）产生开关电源。

2. 发明申请

US20060047991A1 Real time clock architecture and/or method for a system on a chip (SOC) application 失效
标题翻译：用于片上系统（SOC）应用的实时时钟架构和/或方法
公开(公告)号：US20060047991A1
公开(公告)日：2006-03-02
申请号：US10929011
申请日：2004-08-27
申请人： Ho-Ming Leung , Remi Lenoir , Zoltan Toth , Daniel Perrin , Eric Hung , Timothy Wilson
发明人： Ho-Ming Leung , Remi Lenoir , Zoltan Toth , Daniel Perrin , Eric Hung , Timothy Wilson
IPC分类号： G06F1/26
CPC分类号： G06F1/04
摘要： An apparatus comprising a first portion, a second portion and a processor. The first portion is configured to generate a count signal in response to a number of oscillations of a clock signal. The first portion is powered by an unswitched power source. The second portion is configured to generate an interrupt signal in response to the count signal and a predetermined stored value. The second portion is powered by a switched power source. The processor is configured to (i) receive the interrupt signal and (ii) generate the switched power.
摘要翻译：一种包括第一部分，第二部分和处理器的装置。第一部分被配置为响应于时钟信号的振荡的数量产生计数信号。第一部分由未切换的电源供电。第二部分被配置为响应于计数信号和预定的存储值产生中断信号。第二部分由开关电源供电。处理器被配置为（i）接收中断信号和（ii）产生开关电源。

3. 发明授权

US07327172B2 Integrated clock generator with programmable spread spectrum using standard PLL circuitry 失效
标题翻译：具有可编程扩展频谱的集成时钟发生器，采用标准PLL电路
公开(公告)号：US07327172B2
公开(公告)日：2008-02-05
申请号：US11167629
申请日：2005-06-27
申请人： Ho-Ming Leung , Elliot Sowadsky , Eric Hung
发明人： Ho-Ming Leung , Elliot Sowadsky , Eric Hung
IPC分类号： H03L7/06
CPC分类号： H03L7/197 , H03L7/1976
摘要： An apparatus comprising a phase lock loop circuit and a control circuit. The phase lock loop circuit configured to generate an output signal having a first frequency in response to (i) an input signal having a second frequency, (ii) a first divider value and (iii) a second divider value. The second divider value may control spread spectrum modulation of the phase lock loop circuit. The control circuit configured to generate the second divider value in response to (i) the output signal and (ii) a programmable control signal.
摘要翻译：一种包括锁相环电路和控制电路的装置。锁相环电路被配置为响应于（i）具有第二频率的输入信号，（ii）第一分频值和（iii）第二分频值，产生具有第一频率的输出信号。第二分频值可以控制锁相环电路的扩频调制。控制电路被配置为响应于（i）输出信号和（ii）可编程控制信号而产生第二分频器值。

4. 发明申请

US20060290391A1 Integrated clock generator with programmable spread spectrum using standard PLL circuitry 失效
标题翻译：具有可编程扩展频谱的集成时钟发生器，采用标准PLL电路
公开(公告)号：US20060290391A1
公开(公告)日：2006-12-28
申请号：US11167629
申请日：2005-06-27
申请人： Ho-Ming Leung , Elliot Sowadsky , Eric Hung
发明人： Ho-Ming Leung , Elliot Sowadsky , Eric Hung
IPC分类号： H03L7/06
CPC分类号： H03L7/197 , H03L7/1976
摘要： An apparatus comprising a phase lock loop circuit and a control circuit. The phase lock loop circuit may be configured to generate an output signal having a first frequency in response to (i) an input signal having a second frequency, (ii) a first divider value and (iii) a second divider value. The second divider value may control spread spectrum modulation of the phase lock loop circuit. The control circuit may be configured to generate the second divider value in response to (i) the output signal and (ii) a programmable control signal.
摘要翻译：一种包括锁相环电路和控制电路的装置。响应于（i）具有第二频率的输入信号，（ii）第一分频器值和（iii）第二分频器值，锁相环电路可以被配置为产生具有第一频率的输出信号。第二分频值可以控制锁相环电路的扩频调制。控制电路可以被配置为响应于（i）输出信号和（ii）可编程控制信号而产生第二分频器值。

5. 发明申请

US20080085124A1 Clock generation with minimum number of crystals in a multimedia system 审中-公开
标题翻译：在多媒体系统中具有最少数量的晶体的时钟生成
公开(公告)号：US20080085124A1
公开(公告)日：2008-04-10
申请号：US11545406
申请日：2006-10-10
申请人： Ho-Ming Leung , Elliot Sowadsky
发明人： Ho-Ming Leung , Elliot Sowadsky
IPC分类号： H04B10/00
CPC分类号： H04N21/2368 , H04N21/4305 , H04N21/4307 , H04N21/4341
摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a transport stream having (i) audio/video data, (ii) video presentation time stamps, and (iii) audio presentation time stamps. The second circuit may have one or more phase locked loop circuits and a control circuit. The control circuit may. be configured to synchronize the playback of the audio/video data by adjusting a fractional divider of one or more of the phase locked loop circuits.
摘要翻译：一种包括第一电路和第二电路的装置。第一电路可以被配置为呈现具有（i）音频/视频数据，（ii）视频呈现时间戳和（iii）音频呈现时间戳）的传输流。第二电路可以具有一个或多个锁相环电路和控制电路。控制电路可以。被配置为通过调整一个或多个锁相环电路的分数分频器来同步音频/视频数据的重放。

6. 发明授权

US07111199B2 Built-in debug feature for complex VLSI chip 有权
标题翻译：用于复杂VLSI芯片的内置调试功能
公开(公告)号：US07111199B2
公开(公告)日：2006-09-19
申请号：US10190933
申请日：2002-07-08
申请人： Ho-Ming Leung , Fan Zhang , Chiu-Tsun Chu , Gary Chang
发明人： Ho-Ming Leung , Fan Zhang , Chiu-Tsun Chu , Gary Chang
IPC分类号： G06F11/00
CPC分类号： G01R31/31705 , G01R31/31723 , G01R31/318516
摘要： An apparatus comprising (i) a first circuit configured to generate one or more node signals at one or more internal nodes and (ii) a second circuit configured to present one or more of the node signals and a trigger signal in response to one or more control signals.
摘要翻译：一种装置，包括：（i）第一电路，被配置为在一个或多个内部节点处产生一个或多个节点信号;以及（ii）第二电路，被配置为响应于一个或多个节点信号呈现所述节点信号中的一个或多个以及触发信号控制信号。

7. 发明申请

US20050185713A1 Method and apparatus for determining a second picture for temporal direct-mode block prediction 有权
标题翻译：用于确定用于时间直接模式块预测的第二图像的方法和装置
公开(公告)号：US20050185713A1
公开(公告)日：2005-08-25
申请号：US10785273
申请日：2004-02-24
申请人： Lowell Winger , Simon Booth , Elliot Linzer , Ho-Ming Leung
发明人： Lowell Winger , Simon Booth , Elliot Linzer , Ho-Ming Leung
IPC分类号： H04N7/12 , H04N7/26 , H04N7/36 , H04N7/46 , H04N7/50
CPC分类号： H04N19/577 , H04N19/423 , H04N19/51 , H04N19/573 , H04N19/61
摘要： A method for determining a first and a second reference picture used for inter-prediction of a macroblock, comprising the steps of (A) finding a co-located picture and block, (B) determining a reference index, (C) mapping the reference index to a lowest valued reference index in a current reference list and (D) using the reference index to determine the second reference picture.
摘要翻译：一种用于确定用于宏块的相互预测的第一和第二参考图像的方法，包括以下步骤：（A）找到共同定位的图像和块，（B）确定参考索引，（C）映射参考索引到当前参考列表中的最低值参考索引，并且（D）使用参考索引来确定第二参考图片。

8. 发明申请

US20110123172A1 DVD RECORDER AND PVR INSTANT ON ARCHITECTURE 有权
标题翻译： DVD录像机和PVR建筑物
公开(公告)号：US20110123172A1
公开(公告)日：2011-05-26
申请号：US13021972
申请日：2011-02-07
申请人： Ho-Ming Leung , Elliot Sowadsky , Suryanaryana M. Potharaju , Peter G. Panagas, JR.
发明人： Ho-Ming Leung , Elliot Sowadsky , Suryanaryana M. Potharaju , Peter G. Panagas, JR.
IPC分类号： H04N9/80
CPC分类号： H04N5/76 , H04N5/765 , H04N5/781 , H04N5/85
摘要： A method for transitioning a video system is disclosed. The method generally includes a first step for (A) executing in a processing circuit a standby code stored in a nonvolatile memory while the video system is in an off state, the off state defining a low power configuration for the processing circuit and a power off condition for the video system, the standby code being responsive to a plurality of wake up conditions to wake up the video system. In a second step, the method may (B) store an application code in a volatile memory while in the off state, the application code configured to operate the video system while in an on state of the video system. The method generally includes a third step for (C) transitioning from the off state to the on state upon detection of at least one of the wake up conditions. A step for (D) executing in the processing circuit the application code while in the on state to decode video may also exist in the method.
摘要翻译：公开了一种用于转换视频系统的方法。该方法通常包括：（A）在视频系统处于关闭状态时，在处理电路中执行存储在非易失性存储器中的待机代码的第一步骤，关闭状态定义用于处理电路的低功率配置和断电视频系统的条件，待机代码响应于多个唤醒条件来唤醒视频系统。在第二步骤中，所述方法可以（B）在处于关闭状态的情况下将应用代码存储在易失性存储器中，所述应用代码被配置为在处于视频系统的接通状态的情况下操作视频系统。该方法通常包括用于（C）在检测到至少一个唤醒条件时从断开状态转换到接通状态的第三步骤。该方法中也可以存在用于（D）在处理电路中执行应用代码以处于开状态以解码视频的步骤。

9. 发明授权

US07822121B2 Method and/or apparatus for implementing global motion compensation in a video system 有权
标题翻译：用于在视频系统中实现全局运动补偿的方法和/或装置
公开(公告)号：US07822121B2
公开(公告)日：2010-10-26
申请号：US11082639
申请日：2005-03-17
申请人： Kasturiranga Rangam , Elliot Sowadsky , Ho-Ming Leung
发明人： Kasturiranga Rangam , Elliot Sowadsky , Ho-Ming Leung
IPC分类号： H04N7/12
CPC分类号： H04N19/523 , H04N19/23 , H04N19/43 , H04N19/433 , H04N19/44 , H04N19/527 , H04N19/537 , H04N19/61
摘要： An apparatus comprising a video decoder, a video memory and a global motion circuit. The video decoder may be configured to generate a decoded video signal in response to a coded video signal. The video memory may be connected to the video decoder. The global motion circuit may be configured within the video decoder circuit. The global motion circuit may be configured to (i) receive one or more warp points and (ii) generate one or more warping addresses presented directly to the video memory.
摘要翻译：一种包括视频解码器，视频存储器和全局运动电路的装置。视频解码器可以被配置为响应于编码的视频信号产生解码的视频信号。视频存储器可以连接到视频解码器。全局运动电路可以配置在视频解码器电路内。全局运动电路可以被配置为（i）接收一个或多个翘曲点，并且（ii）生成直接呈现给视频存储器的一个或多个翘曲地址。

10. 发明授权

US07408988B2 Motion estimation engine with parallel interpolation and search hardware 有权
标题翻译：具有并行插值和搜索硬件的运动估计引擎
公开(公告)号：US07408988B2
公开(公告)日：2008-08-05
申请号：US10325188
申请日：2002-12-20
申请人： Elliot N. Linzer , Ho-Ming Leung , Soo-Chul Han
发明人： Elliot N. Linzer , Ho-Ming Leung , Soo-Chul Han
IPC分类号： H04N7/18
CPC分类号： H04N5/145 , G06T7/223 , G06T2207/10016 , H04N19/43 , H04N19/523 , H04N19/533 , H04N19/57
摘要： A method for motion estimating. The method generally includes the steps of (A) generating a first interpolated block having a sub-pixel resolution in response to a first interpolation process operating on a reference block of a reference frame of a video signal having an integer pixel resolution, (B) generating a motion vector in response to the first interpolated block and a current block of a current frame of the video signal having the integer pixel resolution and (C) generating a second interpolated block having the sub-pixel resolution in response to a second interpolation process operating on the reference block.
摘要翻译：一种运动估计的方法。该方法通常包括以下步骤：（A）响应于对具有整数像素分辨率的视频信号的参考帧的参考块进行操作的第一内插处理，生成具有子像素分辨率的第一内插块，（B）产生响应于第一内插块的运动矢量和具有整数像素分辨率的视频信号的当前帧的当前块，以及（C）响应于第二内插处理产生具有子像素分辨率的第二内插块在参考块上操作。

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