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1. 发明申请

US20130173902A1 SPLIT DEEP POWER DOWN OF I/O MODULE 有权
标题翻译：分离深度I / O模块的电源
公开(公告)号：US20130173902A1
公开(公告)日：2013-07-04
申请号：US13342023
申请日：2011-12-31
申请人： Inder M. Sodhi , Amjad M. Khan , Zeev Offen , Ryan D. Wells
发明人： Inder M. Sodhi , Amjad M. Khan , Zeev Offen , Ryan D. Wells
IPC分类号： G06F1/26 , G06F9/00
CPC分类号： G06F1/3296 , G06F1/3243 , G06F1/3287 , G06F8/52 , G06F9/3017 , G06F9/3877 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： I/O logic can be separated into critical and non-critical portions, with the non-critical portions being powered down during processor idle. The I/O logic is separated into gate logic and ungated logic, where the ungated logic continues to be powered during a processor deep sleep state, and the gated logic is powered off during the deep sleep state. A power control unit can trigger the shutting down of the I/O logic.
摘要翻译： I / O逻辑可以分为关键部分和非关键部分，非关键部分在处理器空闲期间关闭。 I / O逻辑分为门逻辑和非门逻辑，其中非门逻辑在处理器深度睡眠状态期间继续供电，并且门控逻辑在深度睡眠状态期间断电。电源控制单元可以触发I / O逻辑的关闭。

2. 发明授权

US08954771B2 Split deep power down of I/O module 有权
标题翻译：分离I / O模块的深度电源
公开(公告)号：US08954771B2
公开(公告)日：2015-02-10
申请号：US13342023
申请日：2011-12-31
申请人： Inder M. Sodhi , Amjad M. Khan , Zeev Offen , Ryan D. Wells
发明人： Inder M. Sodhi , Amjad M. Khan , Zeev Offen , Ryan D. Wells
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3296 , G06F1/3243 , G06F1/3287 , G06F8/52 , G06F9/3017 , G06F9/3877 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： I/O logic can be separated into critical and non-critical portions, with the non-critical portions being powered down during processor idle. The I/O logic is separated into gate logic and ungated logic, where the ungated logic continues to be powered during a processor deep sleep state, and the gated logic is powered off during the deep sleep state. A power control unit can trigger the shutting down of the I/O logic.
摘要翻译： I / O逻辑可以分为关键部分和非关键部分，非关键部分在处理器空闲期间关闭。 I / O逻辑分为门逻辑和非门逻辑，其中非门逻辑在处理器深度睡眠状态期间继续供电，并且门控逻辑在深度睡眠状态期间断电。电源控制单元可以触发I / O逻辑的关闭。

3. 发明授权

US09250901B2 Execution context swap between heterogeneous functional hardware units 有权
标题翻译：异构功能硬件单元之间执行上下文交换
公开(公告)号：US09250901B2
公开(公告)日：2016-02-02
申请号：US13795338
申请日：2013-03-12
申请人： Inder M. Sodhi , Marc Torrant , Zeev Offen , Michael Mishaeli , Ashish V. Choubal , Jason W. Brandt
发明人： Inder M. Sodhi , Marc Torrant , Zeev Offen , Michael Mishaeli , Ashish V. Choubal , Jason W. Brandt
IPC分类号： G06F9/30 , G06F9/38 , G06F1/32 , G06F9/46
CPC分类号： G06F9/30123 , G06F1/32 , G06F1/3243 , G06F1/3287 , G06F9/3836 , G06F9/461 , Y02D10/152 , Y02D10/171
摘要： Remapping technologies for execution context swap between heterogeneous functional hardware units are described. A computing system includes multiple registers configured to store remote contexts of functional units. A mapping table maps the remote context to the functional units. An execution unit is configured to execute a remapping tool that intercepts an operation to access a remote context of a first functional unit of the plurality of functional units that is taken offline. The remapping tool determines that the first functional unit is remapped to a second functional unit using the mapping table. The operation is performed to access the remote context that is remapped to the second functional unit. The first functional unit and the second functional unit may be heterogeneous functional units.
摘要翻译：描述用于异构功能硬件单元之间执行上下文交换的重新映射技术。计算系统包括配置成存储功能单元的远程上下文的多个寄存器。映射表将远程上下文映射到功能单元。执行单元被配置为执行重新映射工具，该重新映射工具拦截用于访问脱机的多个功能单元中的第一功能单元的远程上下文的操作。重新映射工具确定使用映射表将第一功能单元重新映射到第二功能单元。执行操作以访问被重新映射到第二功能单元的远程上下文。第一功能单元和第二功能单元可以是异构功能单元。

4. 发明申请

US20140258760A1 Controlling Operating Voltage Of A Processor 有权
标题翻译：控制处理器的工作电压
公开(公告)号：US20140258760A1
公开(公告)日：2014-09-11
申请号：US13793037
申请日：2013-03-11
申请人： Ryan D. Wells , Itai Feit , Doron Rajwan , Nadav Shulman , Zeev Offen , Inder M. Sodhi
发明人： Ryan D. Wells , Itai Feit , Doron Rajwan , Nadav Shulman , Zeev Offen , Inder M. Sodhi
IPC分类号： G06F1/26
CPC分类号： G06F1/28 , G06F1/266 , G06F1/3206 , G06F1/324 , Y02D10/126
摘要： In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括具有多个核心的核心域和具有第一逻辑的功率控制器，该第一逻辑接收第一请求以将核心域的第一核心的工作电压增加到第二电压，以指示电压调节器将工作电压增加到临时电压，然后指示电压调节器将工作电压增加到第二电压。描述和要求保护其他实施例。

5. 发明申请

US20150178091A1 CONTEXT SAVE AND RESTORE 有权
标题翻译：内容保存和恢复
公开(公告)号：US20150178091A1
公开(公告)日：2015-06-25
申请号：US14139798
申请日：2013-12-23
申请人： Zeev Offen , Inder M. Sodhi
发明人： Zeev Offen , Inder M. Sodhi
IPC分类号： G06F9/38 , G06F1/32
CPC分类号： G06F9/3861 , G06F1/3287 , Y02D10/171
摘要： Processor context save latency is reduced by only restoring context registers with saved state that differs from the reset value of registers. A system agent monitors access to the design blocks and sets a dirty bit to indicate which design block has registers that have changed since the last context save. During a context save operation, the system agent bypasses design blocks that have not had context changes since the latest context save operation. During a context restore operation the system agent does not restore the context registers with saved context values that are equal to the reset value of the context register.
摘要翻译：处理器上下文保存延迟仅通过恢复具有与寄存器的复位值不同的保存状态的上下文寄存器来减少。系统代理监视对设计块的访问，并设置脏位，以指示哪个设计块具有自上一个上下文保存以来已更改的寄存器。在上下文保存操作期间，系统代理绕过自最新上下文保存操作以来没有上下文更改的设计块。在上下文恢复操作期间，系统代理不使用等于上下文寄存器的复位值的保存的上下文值来还原上下文寄存器。

6. 发明申请

US20140281380A1 EXECUTION CONTEXT SWAP BETWEEN HETEROGENOUS FUNCTIONAL HARDWARE UNITS 有权
标题翻译：执行异构功能硬件单元之间的上下文交换
公开(公告)号：US20140281380A1
公开(公告)日：2014-09-18
申请号：US13795338
申请日：2013-03-12
申请人： Inder M. Sodhi , Marc Torrant , Zeev Offen , Michael Mishaeli , Ashish V. Choubal , Jason W. Brandt
发明人： Inder M. Sodhi , Marc Torrant , Zeev Offen , Michael Mishaeli , Ashish V. Choubal , Jason W. Brandt
IPC分类号： G06F15/76
CPC分类号： G06F9/30123 , G06F1/32 , G06F1/3243 , G06F1/3287 , G06F9/3836 , G06F9/461 , Y02D10/152 , Y02D10/171
摘要： Remapping technologies for execution context swap between heterogeneous functional hardware units are described. A computing system includes multiple registers configured to store remote contexts of functional units. A mapping table maps the remote context to the functional units. An execution unit is configured to execute a remapping tool that intercepts an operation to access a remote context of a first functional unit of the plurality of functional units that is taken offline. The remapping tool determines that the first functional unit is remapped to a second functional unit using the mapping table. The operation is performed to access the remote context that is remapped to the second functional unit. The first functional unit and the second functional unit may be heterogeneous functional units.
摘要翻译：描述用于异构功能硬件单元之间执行上下文交换的重新映射技术。计算系统包括配置成存储功能单元的远程上下文的多个寄存器。映射表将远程上下文映射到功能单元。执行单元被配置为执行重新映射工具，该重新映射工具拦截用于访问脱机的多个功能单元中的第一功能单元的远程上下文的操作。重新映射工具确定使用映射表将第一功能单元重新映射到第二功能单元。执行操作以访问被重新映射到第二功能单元的远程上下文。第一功能单元和第二功能单元可以是异构功能单元。

7. 发明申请

US20140189299A1 HETERGENEOUS PROCESSOR APPARATUS AND METHOD 有权
标题翻译：空气处理器装置和方法
公开(公告)号：US20140189299A1
公开(公告)日：2014-07-03
申请号：US13730565
申请日：2012-12-28
申请人： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , David A. Koufaty , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Ravishankar Iyer , Nagabhushan Chitlur , Inder M. Sodhi , Gaurav Khanna , Russell J. Fenger
发明人： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , David A. Koufaty , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Ravishankar Iyer , Nagabhushan Chitlur , Inder M. Sodhi , Gaurav Khanna , Russell J. Fenger
IPC分类号： G06F9/38
CPC分类号： G06F9/3891
摘要： A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.
摘要翻译：描述异构处理器架构。例如，根据本发明的一个实施例的处理器包括：一组大的物理处理器核心; 一组具有相对较低性能处理能力的小物理处理器核和相对于大型物理处理器核的相对较低的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将大型物理处理器核心集合暴露给软件，并从该软件中隐藏一组小型物理处理器核心。

8. 发明申请

US20120159216A1 METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING ENHANCED TEMPERATURE BASED VOLTAGE CONTROL 有权
标题翻译：能源效率和能源保护的方法，装置和系统，包括基于增强温度的电压控制
公开(公告)号：US20120159216A1
公开(公告)日：2012-06-21
申请号：US13335747
申请日：2011-12-22
申请人： Ryan D. Wells , Uzi Sasson , Inder M. Sodhi , Sanjeev Jahagirdar
发明人： Ryan D. Wells , Uzi Sasson , Inder M. Sodhi , Sanjeev Jahagirdar
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/26 , G06F1/206 , G06F1/3206 , G06F1/3296 , Y02D10/16 , Y02D10/172
摘要： Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enhanced temperature based voltage control are described. In one embodiment, an apparatus includes a processor and a controller coupled with the processor. In one embodiment, the controller receives a temperature measurement corresponding to a current temperature of the processor. In one embodiment, the controller further determines an adjustment to a voltage being applied to the processor based at least in part on the temperature measurement and a plurality of internal limits of the processor, wherein the determined adjustment to the voltage is based on an inverse temperature dependence relationship between at least one of an operating frequency and a voltage of the processor, and temperature. In one embodiment, the controller provides the determined adjustment to the voltage to a voltage regulator interface.
摘要翻译：描述了包括增强的基于温度的电压控制的能量效率和节能的系统，装置和方法的实施例。在一个实施例中，一种装置包括处理器和与处理器耦合的控制器。在一个实施例中，控制器接收与处理器的当前温度相对应的温度测量。在一个实施例中，控制器至少部分地基于温度测量和处理器的多个内部限制来确定对施加到处理器的电压的调整，其中所确定的对电压的调整基于逆温度处理器的工作频率和电压中的至少一个之间的依赖关系以及温度。在一个实施例中，控制器将确定的调整提供给电压调节器接口的电压。

9. 发明授权

US09400545B2 Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devices 有权
标题翻译：节能和节能的方法，装置和系统，包括设备中自主的基于硬件的深度断电
公开(公告)号：US09400545B2
公开(公告)日：2016-07-26
申请号：US13335738
申请日：2011-12-22
申请人： Inder M. Sodhi , Alon Naveh , Doron Rajwan , Ryan D. Wells , Eric C. Samson
发明人： Inder M. Sodhi , Alon Naveh , Doron Rajwan , Ryan D. Wells , Eric C. Samson
IPC分类号： G06F1/32
CPC分类号： G06F3/0625 , G06F1/3206 , G06F1/3278 , G06F1/3287 , G06F3/0634 , G06F3/0673 , Y02D10/157 , Y02D10/171
摘要： Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.
摘要翻译：描述了能量效率和能量节约的系统，装置和方法的实施例，包括实现设备的自主的基于硬件的深度断电。在一个实施例中，系统包括与设备和静态存储器耦合的设备，静态存储器和功率控制单元。该系统还包括功率控制单元的深度掉电逻辑，用于监视设备的状态，并且当设备空闲时将设备传送到深度断电状态。在系统中，当处于深功率关闭状态时，器件消耗的功率小于空闲状态。

10. 发明申请

US20150186313A1 Managing Shared Resources Between Multiple Processing Devices 有权
标题翻译：管理多个处理设备之间的共享资源
公开(公告)号：US20150186313A1
公开(公告)日：2015-07-02
申请号：US14141828
申请日：2013-12-27
申请人： Inder M. Sodhi , Joydeep Ray , Varghese George
发明人： Inder M. Sodhi , Joydeep Ray , Varghese George
IPC分类号： G06F13/36 , G06F9/50
CPC分类号： G06F13/36 , G06F9/52
摘要： In accordance with embodiments disclosed herein, there is provided systems and methods for managing shared resources between multiple processing devices. The processor may include a first processing device comprising a first non-coherent hardware block (hb) including a non-coherent data and a second processing device comprising a second non-coherent hb including the non-coherent data. The processor may also include a first hb in communication with the first non-coherent hb and the second non-coherent hb to track and share the non-coherent data between the first and the second processing devices.
摘要翻译：根据本文公开的实施例，提供了用于管理多个处理设备之间的共享资源的系统和方法。处理器可以包括包括包括非相干数据的第一非相干硬件块（hb）的第一处理设备和包括包括非相干数据的第二非相干hb的第二处理设备。处理器还可以包括与第一非相干hb和第二非相干hb通信的第一hb以跟踪和共享第一和第二处理设备之间的非相干数据。

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