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1. 发明申请

US20120179953A1 Semiconductor Integrated Circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20120179953A1
公开(公告)日：2012-07-12
申请号：US13368461
申请日：2012-02-08
申请人： Yutaka SHINAGAWA , Takeshi KATAOKA , Eiichi ISHIKAWA , Toshihiro TANAKA , Kazumasa YANAGISAWA , Kazufumi SUZUKAWA
发明人： Yutaka SHINAGAWA , Takeshi KATAOKA , Eiichi ISHIKAWA , Toshihiro TANAKA , Kazumasa YANAGISAWA , Kazufumi SUZUKAWA
IPC分类号： G11C16/04 , G06F11/10 , H03M13/05
CPC分类号： G11C16/349 , G11C16/06 , G11C16/3495
摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information, and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.
摘要翻译：半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数更多。

2. 发明申请

US20110246860A1 Semiconductor Integrated Circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20110246860A1
公开(公告)日：2011-10-06
申请号：US13162180
申请日：2011-06-16
申请人： Yutaka SHINAGAWA , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
发明人： Yutaka SHINAGAWA , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
IPC分类号： H03M13/05 , G11C16/04 , G06F11/10
CPC分类号： G11C16/349 , G11C16/06 , G11C16/3495
摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed In an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior In a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.
摘要翻译：半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写非易失性存储区域。非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以不利于保证重写操作的次数; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。可以优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数更多。

3. 发明申请

US20110309428A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110309428A1
公开(公告)日：2011-12-22
申请号：US13223380
申请日：2011-09-01
申请人： TOSHIHIRO TANAKA , Yukiko UMEMOTO , Mitsuru HIRAKI , Yutaka SHINAGAWA , Masamichi FUJITO , Kazufumi SUZUKAWA , Hiroyuki TANIKAWA , Takeshi YAMAKI , Yoshiaki KAMIGAKI , Shinichi MINAMI , Kozo KATAYAMA , Nozomu MATSUZAKI
发明人： TOSHIHIRO TANAKA , Yukiko UMEMOTO , Mitsuru HIRAKI , Yutaka SHINAGAWA , Masamichi FUJITO , Kazufumi SUZUKAWA , Hiroyuki TANIKAWA , Takeshi YAMAKI , Yoshiaki KAMIGAKI , Shinichi MINAMI , Kozo KATAYAMA , Nozomu MATSUZAKI
IPC分类号： H01L29/788
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

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