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1. 发明授权

US08576643B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08576643B2
公开(公告)日：2013-11-05
申请号：US13368461
申请日：2012-02-08
申请人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
发明人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
IPC分类号： G11C7/00
CPC分类号： G11C16/349 , G11C16/06 , G11C16/3495
摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has a maximum variation width of a threshold voltage for memorizing an information set larger than that of the second nonvolatile memory area. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information, and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information.
摘要翻译：半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。第一非易失性存储区具有用于存储大于第二非易失性存储区的信息集的阈值电压的最大变化宽度。可以优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数。

2. 发明申请

US20090052238A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20090052238A1
公开(公告)日：2009-02-26
申请号：US12258964
申请日：2008-10-27
申请人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
发明人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
IPC分类号： G11C16/00
CPC分类号： G11C16/349 , G11C16/06 , G11C16/3495
摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more.
摘要翻译：半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以在保证重写操作次数方面较差; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以优先考虑第二非易失性存储器区域，以保证存储器信息的重写操作的次数更多。

3. 发明授权

US08130571B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08130571B2
公开(公告)日：2012-03-06
申请号：US13162180
申请日：2011-06-16
申请人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
发明人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
IPC分类号： G11C7/00
CPC分类号： G11C16/349 , G11C16/06 , G11C16/3495
摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed In an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior In a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.
摘要翻译：半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写非易失性存储区域。非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以不利于保证重写操作的次数; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。可以优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数更多。

4. 发明申请

US20110246860A1 Semiconductor Integrated Circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20110246860A1
公开(公告)日：2011-10-06
申请号：US13162180
申请日：2011-06-16
申请人： Yutaka SHINAGAWA , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
发明人： Yutaka SHINAGAWA , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
IPC分类号： H03M13/05 , G11C16/04 , G06F11/10
CPC分类号： G11C16/349 , G11C16/06 , G11C16/3495
摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed In an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior In a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.
摘要翻译：半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写非易失性存储区域。非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以不利于保证重写操作的次数; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。可以优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数更多。

5. 发明授权

US07978545B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07978545B2
公开(公告)日：2011-07-12
申请号：US12775377
申请日：2010-05-06
申请人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
发明人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
IPC分类号： G11C7/00
CPC分类号： G11C16/349 , G11C16/06 , G11C16/3495
摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.
摘要翻译：半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以在保证重写操作次数方面较差; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。可以优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数更多。

6. 发明申请

US20100220531A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20100220531A1
公开(公告)日：2010-09-02
申请号：US12775377
申请日：2010-05-06
申请人： YUTAKA SHINAGAWA , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
发明人： YUTAKA SHINAGAWA , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
IPC分类号： G11C16/04 , G06F12/02 , G06F11/00 , G06F13/20
CPC分类号： G11C16/349 , G11C16/06 , G11C16/3495
摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.
摘要翻译：半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以在保证重写操作次数方面较差; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。可以优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数更多。

7. 发明授权

US07821824B2 Semiconductor integrated circuit having buses with different data transfer rates 有权
标题翻译：具有不同数据传输速率的总线的半导体集成电路
公开(公告)号：US07821824B2
公开(公告)日：2010-10-26
申请号：US12258964
申请日：2008-10-27
申请人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
发明人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
IPC分类号： G11C16/04
CPC分类号： G11C16/349 , G11C16/06 , G11C16/3495
摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information.
摘要翻译：半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以在保证重写操作次数方面较差; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数。

8. 发明申请

US20070247918A1 Semiconductor Integrated Circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20070247918A1
公开(公告)日：2007-10-25
申请号：US11573004
申请日：2004-08-30
申请人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
发明人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
IPC分类号： G11C11/34
CPC分类号： G11C16/349 , G11C16/06 , G11C16/3495
摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more.
摘要翻译：半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以在保证重写操作次数方面较差; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。优先考虑第一非易失性存储区域以加快存储器信息的读取速度，并且可以优先考虑第二非易失性存储器区域以保证存储器信息的重写操作的次数更多。

9. 发明授权

US07277979B2 Microcomputer with mode-controlled memory 失效
标题翻译：具有模式控制存储器的微型计算机
公开(公告)号：US07277979B2
公开(公告)日：2007-10-02
申请号：US10981612
申请日：2004-11-05
申请人： Naoki Yada , Eiichi Ishikawa
发明人： Naoki Yada , Eiichi Ishikawa
IPC分类号： G06F12/00
CPC分类号： G06F8/60 , G06F9/4401 , G06F13/387
摘要： A microcomputer capable of on-board programming of dedicated user communication protocols without requiring a serial interface on the mounted board, and that will not destroy the dedicated user communication protocol code even if the system runs out of control. A user boot mat other than a user mat is provided for programming control programs for the user in the on-chip non-volatile memory of the microcomputer. The user boot mat serves as the mat for programming the dedicated user communication protocol and also provides a user boot mode for running the program. The user boot mat cannot program or erase in this user boot mode. By separating the user boot mat and user mat, an interface capable of programming and erasing the user-specified programming can be achieved without having to program a dedicated communication protocol on the user mat.
摘要翻译：一种能够在不需要安装板上的串行接口的情况下对专用用户通信协议进行板载编程的微型计算机，即使系统失去控制也不会破坏专用用户通信协议代码。提供除用户垫之外的用户启动垫用于微型计算机的片上非易失性存储器中的用户的编程控制程序。用户启动垫用作编程专用用户通信协议的垫，并且还提供用于运行程序的用户引导模式。在此用户启动模式下，用户启动垫无法编程或擦除。通过分离用户启动垫和用户垫，可以实现能够编程和擦除用户指定的编程的接口，而无需在用户垫上编程专用通信协议。

10. 发明申请

US20070206432A1 Microcomputer and microprocessor having flash memory operable from single external power supply 失效
标题翻译：具有从单个外部电源可操作的闪存的微计算机和微处理器
公开(公告)号：US20070206432A1
公开(公告)日：2007-09-06
申请号：US11797579
申请日：2007-05-04
申请人： Eiichi Ishikawa , Yasuyuki Saito , Masanao Sato , Naoki Yada , Kiyoshi Matsubara
发明人： Eiichi Ishikawa , Yasuyuki Saito , Masanao Sato , Naoki Yada , Kiyoshi Matsubara
IPC分类号： G11C16/06
CPC分类号： G11C16/12 , G11C5/14 , G11C5/145 , G11C5/147 , G11C16/30
摘要： A data processing apparatus supplied a first voltage from outside, includes a CPU, a first voltage generating circuit, a second voltage generating circuit, a clock generating circuit, and, a nonvolatile memory which can be accessed by the CPU. The first voltage generating circuit generates a second voltage, a voltage level of which is lower than that of the first voltage. The clock generating circuit is supplied the second voltage from the first voltage generating circuit and generates a clock signal, and the second voltage generating circuit is supplied the second voltage from the first voltage generating circuit and the clock signal from the clock generating circuit, and generates a second voltage, a voltage level of which is higher than that of the first voltage, for supplying to the nonvolatile memory.
摘要翻译：从外部提供第一电压的数据处理装置包括CPU，第一电压产生电路，第二电压产生电路，时钟发生电路和可被CPU访问的非易失性存储器。第一电压产生电路产生其电压电平低于第一电压的第二电压。时钟发生电路从第一电压产生电路提供第二电压并产生时钟信号，并且第二电压产生电路从第一电压产生电路提供第二电压和来自时钟发生电路的时钟信号，并产生其电压电平高于第一电压的第二电压，用于提供给非易失性存储器。

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