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1. 发明授权

US08148774B2 Method of fabricating semiconductor device with a high breakdown voltage between neighboring wells 有权
标题翻译：制造相邻孔之间具有高击穿电压的半导体器件的方法
公开(公告)号：US08148774B2
公开(公告)日：2012-04-03
申请号：US12606634
申请日：2009-10-27
申请人： Hidemitsu Mori , Kazuhiro Takimoto , Toshiyuki Shou , Kenji Sasaki , Yutaka Akiyama
发明人： Hidemitsu Mori , Kazuhiro Takimoto , Toshiyuki Shou , Kenji Sasaki , Yutaka Akiyama
IPC分类号： H01L29/66 , H01L21/8238
CPC分类号： H01L21/823892 , H01L21/26513 , H01L21/823493
摘要： To provide a semiconductor device in which an interval between first wells can be shortened by improving a separation breakdown voltage between the first wells and a method for manufacturing the same. A semiconductor device includes a first conductivity type semiconductor substrate 1, second conductivity type first wells 2 and 3 disposed on a surface layer of the semiconductor substrate 1 with a predetermined interval between them, a first conductivity type second well 4 disposed between the first wells 2 and 3 on the surface layer of the semiconductor substrate 1 and having an impurity concentration higher than that of the semiconductor substrate, a first conductivity type third well 5 at least disposed below the second well 4 in the semiconductor substrate 1 and having an impurity concentration higher than that of the semiconductor substrate 1 and lower than that of the second well 4, and a first conductivity type fourth well 11 at least disposed below the third well 5 in the semiconductor substrate 1 and having an impurity concentration higher than that of the semiconductor substrate 1 and lower than that of the second well 4.
摘要翻译：提供一种半导体器件，其中可以通过改善第一阱之间的分离击穿电压及其制造方法来缩短第一阱之间的间隔。半导体器件包括第一导电类型半导体衬底1，设置在半导体衬底1的表面层上的第二导电类型的第一阱2和3之间的预定间隔，设置在第一阱2之间的第一导电类型第二阱4 并且在半导体衬底1的表面层上具有杂质浓度高于半导体衬底1的杂质浓度的第一导电类型第三阱5，至少设置在半导体衬底1中的第二阱4的下方并且杂质浓度更高比半导体衬底1低，而低于第二阱4，以及第一导电类型的第四阱11，其至少设置在半导体衬底1中的第三阱5的下方，其杂质浓度高于半导体衬底的杂质浓度 1且低于第二孔4的厚度。

2. 发明授权

US07969256B2 Signal transmission circuit and signal transmission system with reduced reflection 有权
标题翻译：信号传输电路和信号传输系统减少反射
公开(公告)号：US07969256B2
公开(公告)日：2011-06-28
申请号：US12153786
申请日：2008-05-23
申请人： Kanji Otsuka , Yutaka Akiyama
发明人： Kanji Otsuka , Yutaka Akiyama
IPC分类号： H04B3/28
CPC分类号： H04L25/028
摘要： A signal transmission circuit includes a transmitting circuit for outputting a transmitting signal to a transmission line, a parallel circuit including a capacitor and a first resistance connected between an output terminal of the transmitting circuit and the transmission line, and a series circuit including an inductor and a second resistance connected between an output side of the parallel circuit and a ground.
摘要翻译：信号传输电路包括用于向传输线输出发送信号的发送电路，包括电容器的并联电路和连接在发送电路的输出端子与传输线路之间的第一电阻，以及串联电路，包括电感器和连接在并联电路的输出侧和地之间的第二电阻。

3. 发明申请

US20110073352A1 PAIRED LOW-CHARACTERISTIC IMPEDANCE POWER LINE AND GROUND LINE STRUCTURE 审中-公开
标题翻译：配对低特性阻抗电源线和接地线结构
公开(公告)号：US20110073352A1
公开(公告)日：2011-03-31
申请号：US12991929
申请日：2009-05-21
申请人： Kanji Otsuka , Yutaka Akiyama , Toshiyuki Kawaguchi , Kazutoki Tahara
发明人： Kanji Otsuka , Yutaka Akiyama , Toshiyuki Kawaguchi , Kazutoki Tahara
IPC分类号： H05K1/00
CPC分类号： H05K1/0234 , H05K1/0218 , H05K1/0245 , H05K1/025 , H05K1/167 , H05K3/28 , H05K2201/0179 , H05K2201/0317 , H05K2201/09236
摘要： Disclosed is a paired low-characteristic impedance power line and ground line structure in which loop inductance is substantially 0. The paired low-characteristic impedance power line and ground line structure includes a laminated sheet in which a metal wiring layer having a power line and a ground line is provided on the surface of an insulating sheet, an insulating thin-film layer provided so as to cover the power line and the ground line, and a resistive layer provided on the surface of the insulating thin-film layer.
摘要翻译：公开了一种成对的低特性阻抗电力线和接地线结构，其中环路电感基本为零。成对的低特征阻抗电力线和接地线结构包括层压片，其中具有电力线和接地线设置在绝缘片的表面上，设置为覆盖电源线和接地线的绝缘薄膜层，以及设置在绝缘薄膜层的表面上的电阻层。

4. 发明授权

US06285970B1 Computer simulation method of silicon oxidation 失效
标题翻译：硅氧化计算机模拟方法
公开(公告)号：US06285970B1
公开(公告)日：2001-09-04
申请号：US09200749
申请日：1998-11-30
申请人： Yutaka Akiyama
发明人： Yutaka Akiyama
IPC分类号： G06F760
CPC分类号： G06F17/5018
摘要： A simulation method of Si oxidation is provided, which decreases the simulation time. A diffusion equation of oxidant is solved at individual nodes in a SiO2 region to calculate the surface concentration of the oxidant at the Si/SiO2 interface, resulting in the first value of the surface concentration of the oxidant at each of the nodes in the present time step. Then, the first value of the surface concentration of the oxidant at each of the nodes in the SiO2 region is adjusted to generate the second value of the surface concentration of the oxidant at each of the nodes in the SiO2 region in the present time step. Also, the second value of the surface concentration of the oxidant in the present time step is set as zero with respect to one of the nodes where the thickness increase of the SiO2 region has a value equal to or less than the specific small value. Simultaneously with this, the first value of the surface concentration of the oxidant is stored for a next time step. The stored first value of the surface concentration of the oxidant is added to a first value of the surface concentration of the oxidant obtained in the next time step, thereby producing a second value of the surface concentration of the oxidant in the next time step. The second value of the surface concentration of the oxidant is used in calculation of the thickness increase of the SiO2 region.
摘要翻译：提供了Si氧化的模拟方法，减少了模拟时间。在SiO 2区域的各个节点处求解氧化剂的扩散方程，计算出Si / SiO2界面处氧化剂的表面浓度，得到当前时刻各节点氧化剂表面浓度的第一值步。然后，调整SiO 2区域中的每个节点处的氧化剂的表面浓度的第一值，以在当前时间步长中产生SiO 2区域中的每个节点处的氧化剂的表面浓度的第二值。此外，当前时间步长中的氧化剂的表面浓度的第二值相对于其中SiO 2区域的厚度增加具有等于或小于特定小值的值的一个节点被设置为零。同时，将氧化剂的表面浓度的第一值存储下一个时间步长。将所存储的氧化剂的表面浓度的第一值加到在下一个时间步骤中获得的氧化剂的表面浓度的第一值，从而在下一个时间步骤中产生氧化剂的表面浓度的第二值。氧化剂的表面浓度的第二个值用于计算SiO 2区域的厚度增加。

5. 发明授权

US6044213A Process simulation method for calculating a surface oxidant concentration in oxidation process 失效
标题翻译：用于计算氧化过程中表面氧化剂浓度的过程模拟方法
公开(公告)号：US6044213A
公开(公告)日：2000-03-28
申请号：US65900
申请日：1998-04-24
申请人： Yutaka Akiyama
发明人： Yutaka Akiyama
IPC分类号： H01L21/316 , G06F17/50 , G06F19/00 , G06Q50/00 , G06Q50/04 , H01L21/00 , G06F9/455
CPC分类号： G06F17/5018 , G06F2217/16
摘要： The present invention provides a method of simulating a process for oxidation of silicon. The method comprises the following steps. A time "t" of oxidation calculation is set at zero. An effective surface oxidant concentration of a silicon surface exposed to an oxygen atmosphere is calculated assuming that a spontaneous silicon oxide film as an initial silicon oxide film extends over the silicon surface. The time "t" of oxidation calculation is forwarded by a predetermined time increment .DELTA.t. An oxidation rate is calculated by use of one of the effective surface oxidant concentration and the surface oxidant concentration. A new silicon surface is formed based upon the calculated oxidation rate and the time increment .DELTA.t. Variations in thickness of the silicon oxide film over time are found by a deformation calculation. There is verified whether or not the time "t" of oxidation calculation reaches a predetermined end time so that if the time "t" of oxidation calculation reaches the predetermined end time, then a current simulation is ended, while if the time "t" of oxidation calculation does not reach the predetermined end time, then an oxidant diffusion equation is solved for a deformed silicon oxide film to calculate the surface oxidant concentration of the silicon surface to be oxidized. A loop comprising the sequential third to seventh steps is repeated until the time "t" of oxidation calculation reaches the predetermined end time.
摘要翻译：本发明提供了一种模拟硅氧化工艺的方法。该方法包括以下步骤。氧化计算的时间“t”设定为零。假设作为初始氧化硅膜的自发氧化硅膜在硅表面上延伸，计算暴露于氧气氛的硅表面的有效表面氧化剂浓度。氧化计算的时间“t”以预定的时间增量DELTA t转发。通过使用有效表面氧化剂浓度和表面氧化剂浓度之一计算氧化速率。基于计算的氧化速率和时间增量DELTA t形成新的硅表面。通过变形计算可以发现氧化硅膜随时间的变化。验证氧化计算的时间“t”是否达到预定的结束时间，使得如果氧化计算的时间“t”达到预定的结束时间，则当前模拟结束，而如果时间“t” 的氧化计算未达到预定的结束时间，则对于变形的氧化硅膜求解氧化剂扩散方程，以计算待氧化的硅表面的表面氧化剂浓度。重复包括顺序的第三到第七步骤的循环，直到氧化计算的时间“t”达到预定的结束时间。

6. 发明授权

US08373072B2 Printed circuit board 有权
标题翻译：印刷电路板
公开(公告)号：US08373072B2
公开(公告)日：2013-02-12
申请号：US12501931
申请日：2009-07-13
申请人： Daisuke Iguchi , Kanji Otsuka , Yutaka Akiyama
发明人： Daisuke Iguchi , Kanji Otsuka , Yutaka Akiyama
IPC分类号： H05K1/03
CPC分类号： H05K9/0084 , H05K1/0218 , H05K1/0234 , H05K1/167 , H05K3/403 , H05K2201/0187 , H05K2201/0215 , H05K2201/09309
摘要： A printed circuit board includes a ground layer, a power source layer, a signal wiring layer, an insulating layer and an electromagnetic radiation suppressing member. The power source layer is provided to be opposed to the ground layer. The signal wiring layer transmits a signal in a predetermined frequency domain. The insulating layer insulates the ground layer, the power source layer and the signal wiring layer from one another. The electromagnetic radiation suppressing member is provided to cover a circumferential edge of the insulating layer. The electromagnetic radiation suppressing member has a negative dielectric constant and a positive magnetic permeability in a frequency domain including the predetermined frequency domain.
摘要翻译：印刷电路板包括接地层，电源层，信号布线层，绝缘层和电磁辐射抑制构件。电源层设置成与接地层相对。信号布线层发送预定频域的信号。绝缘层使接地层，电源层和信号布线层彼此绝缘。电磁辐射抑制构件被设置成覆盖绝缘层的周缘。电磁辐射抑制构件在包括预定频域的频域中具有负介电常数和正磁导率。

7. 发明授权

US07906840B2 Semiconductor integrated circuit package, printed circuit board, semiconductor apparatus, and power supply wiring structure 有权
标题翻译：半导体集成电路封装，印刷电路板，半导体装置和电源布线结构
公开(公告)号：US07906840B2
公开(公告)日：2011-03-15
申请号：US12204677
申请日：2008-09-04
申请人： Kanji Otsuka , Yutaka Akiyama
发明人： Kanji Otsuka , Yutaka Akiyama
IPC分类号： H01L23/02
CPC分类号： H05K1/0231 , H01L23/50 , H01L23/5286 , H01L23/552 , H01L23/66 , H01L2223/6638 , H01L2224/16225 , H01L2924/19051 , H01L2924/3011 , H05K1/0263 , H05K2201/09672 , H05K2201/10545 , H05K2201/10734
摘要： A semiconductor integrated circuit package, a printed circuit board, a semiconductor apparatus, and a power supply wiring structure that allow attainment of stable power source and ground wiring without causing resonance even in a high-frequency bandwidth are provided. In an interior portion of the package, a power source wiring and a ground wiring constitute a pair wiring structure in which the power source wiring and the ground wiring are juxtaposed at a predetermined interval so as to establish electromagnetic coupling therebetween. A plurality of pair wiring structures are combined in such a manner that, when viewed in a section perpendicular to a wiring extending direction, the pair wiring assembly assumes a staggered (checkered) configuration. It is preferable that, each of the silicon chip and the printed circuit board, like the package, has pair wiring structures disposed inside.
摘要翻译：提供了一种半导体集成电路封装，印刷电路板，半导体装置和电源布线结构，即使在高频带宽下也能够实现稳定的电源和接地布线而不引起共振。在封装的内部，电源布线和接地布线构成一对布线结构，其中电源布线和接地布线以预定的间隔并置，以便在它们之间建立电磁耦合。多个对布线结构以这样的方式组合，即当在与布线延伸方向垂直的截面中观察时，该对布线组件呈现交错（方格）的结构。优选地，像封装一样，硅芯片和印刷电路板中的每一个具有配置在内部的配线结构。

8. 发明申请

US20080310521A1 Signal transmission circuit and signal transmission system 有权
标题翻译：信号传输电路和信号传输系统
公开(公告)号：US20080310521A1
公开(公告)日：2008-12-18
申请号：US12153786
申请日：2008-05-23
申请人： Kanji Otsuka , Yutaka Akiyama
发明人： Kanji Otsuka , Yutaka Akiyama
IPC分类号： H04B3/00 , H04L27/00 , H04L25/00
CPC分类号： H04L25/028
摘要： A signal transmission circuit includes a transmitting circuit for outputting a transmitting signal to a transmission line, a parallel circuit including a capacitor and a first resistance connected between an output terminal of the transmitting circuit and the transmission line, and a series circuit including an inductor and a second resistance connected between an output side of the parallel circuit and a ground.
摘要翻译：信号传输电路包括用于向传输线输出发送信号的发送电路，包括电容器的并联电路和连接在发送电路的输出端子与传输线路之间的第一电阻，以及串联电路，包括电感器和连接在并联电路的输出侧和地之间的第二电阻。

9. 发明申请

US20070176708A1 Narrow impedance conversion device 有权
标题翻译：窄阻抗转换器件
公开(公告)号：US20070176708A1
公开(公告)日：2007-08-02
申请号：US11500943
申请日：2006-08-09
申请人： Kanji Otsuka , Tamotsu Usami , Yutaka Akiyama
发明人： Kanji Otsuka , Tamotsu Usami , Yutaka Akiyama
IPC分类号： H03H7/38
CPC分类号： H01P5/02
摘要： An impedance conversion device has four conductors arranged so that the first and second conductors form a transmission line having a first characteristic impedance, the third and fourth conductors form a transmission line having the first characteristic impedance, the first and third conductors form a transmission line having a second characteristic impedance, and the second and fourth conductors form a third transmission line having the second characteristic impedance. The second and fourth conductors are interconnected at proximate ends through a resistance equal to the first characteristic impedance. The third and fourth conductors are interconnected at proximate ends through a resistance equal to the second characteristic impedance. The lateral dimensions of the impedance conversion device are small enough to permit insertion in a stacked pair line.
摘要翻译：阻抗转换装置具有四个导体，其布置成使得第一和第二导体形成具有第一特征阻抗的传输线，第三和第四导体形成具有第一特征阻抗的传输线，第一和第三导体形成传输线，第二特征阻抗，第二和第四导体形成具有第二特性阻抗的第三传输线。第二和第四导体通过等于第一特征阻抗的电阻在近端互连。第三和第四导体通过等于第二特征阻抗的电阻在近端互连。阻抗转换装置的横向尺寸足够小以允许插入堆叠的对线。

10. 发明申请

US20070009916A1 Guanosine triphosphate-binding protein coupled receptors 审中-公开
标题翻译：鸟苷三磷酸结合蛋白偶联受体
公开(公告)号：US20070009916A1
公开(公告)日：2007-01-11
申请号：US11214063
申请日：2005-08-30
申请人： Makiko Suwa , Kiyoshi Asai , Yutaka Akiyama , Hiroyuki Aburatani
发明人： Makiko Suwa , Kiyoshi Asai , Yutaka Akiyama , Hiroyuki Aburatani
IPC分类号： C12Q1/68 , C07H21/04 , C12P21/06 , C07K14/705 , C07K16/28
CPC分类号： C07K14/705 , A61K38/00
摘要： The object of the present invention is to provide a technique for efficiently extracting GPCR sequences from human genome sequences, thereby comprehensively identifying novel GPCRs. An original automatic system for identifying GPCR sequences is disclosed, and 1035 novel GPCRs are successfully identified from the entire human genome by utilizing the system.
摘要翻译：本发明的目的是提供一种从人类基因组序列有效提取GPCR序列的技术，从而全面地鉴定新的GPCR。公开了一种用于鉴定GPCR序列的原始自动系统，并且通过利用该系统从整个人类基因组中成功地鉴定了1035种新型GPCR。

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