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1. 发明授权

US07804111B2 Semiconductor device and method for adjusting characteristics thereof 有权
标题翻译：用于调整其特性的半导体器件和方法
公开(公告)号：US07804111B2
公开(公告)日：2010-09-28
申请号：US12083573
申请日：2006-10-10
申请人： Kanji Otsuka , Munekazu Takano , Fumio Mizuno , Saburo Yokokura , Tsuneo Ito , Yuko Tanba , Yutaka Akiyama
发明人： Kanji Otsuka , Munekazu Takano , Fumio Mizuno , Saburo Yokokura , Tsuneo Ito , Yuko Tanba , Yutaka Akiyama
IPC分类号： H01L29/94
CPC分类号： H03K5/156 , H01L23/642 , H01L23/66 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/19041 , H01L2924/19051 , H01L2924/30107 , H01L2924/3011 , H03K2005/00026 , H03K2217/0018 , H04L25/085 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The object of the invention is to provide a semiconductor device including signal-transmission interconnections preferable for transmitting high frequency signal and capability to adjust characteristics of the above signal-transmission interconnections. A semiconductor device according to the present invention consists of a signal-transmission interconnection 20 for transmission of signals, a MOS capacitance element 10 having a gate electrode connected to the signal-transmission interconnection 20, a first voltage-applying interconnection 30 connected to a source and a drain of the MOS capacitance element 10 and applying a voltage to the source and the drain of the MOS capacitance element 10, a second voltage-applying interconnection 40 connected to a well of the MOS capacitance element 10, and applying a voltage to the well of said first MOS capacitance element 10. Jitters occurring in the signal-transmission interconnection 20 can be adjusted by adjusting each of voltages of the first voltage-applying interconnection 30 and the second voltage-applying interconnection 40.
摘要翻译：本发明的目的是提供一种半导体器件，其包括优选用于传输高频信号的信号传输互连和调整上述信号传输互连特性的能力。根据本发明的半导体器件包括用于传输信号的信号传输互连20，具有连接到信号传输互连20的栅电极的MOS电容元件10，连接到源的第一施加电压互连30 和MOS电容元件10的漏极，并向MOS电容元件10的源极和漏极施加电压，连接到MOS电容元件10的阱的第二施加电压互连40，并向可以通过调节第一施加电压互连30和第二施加电压互连40的每个电压来调节发生在信号传输互连20中的抖动。

2. 发明授权

US07969256B2 Signal transmission circuit and signal transmission system with reduced reflection 有权
标题翻译：信号传输电路和信号传输系统减少反射
公开(公告)号：US07969256B2
公开(公告)日：2011-06-28
申请号：US12153786
申请日：2008-05-23
申请人： Kanji Otsuka , Yutaka Akiyama
发明人： Kanji Otsuka , Yutaka Akiyama
IPC分类号： H04B3/28
CPC分类号： H04L25/028
摘要： A signal transmission circuit includes a transmitting circuit for outputting a transmitting signal to a transmission line, a parallel circuit including a capacitor and a first resistance connected between an output terminal of the transmitting circuit and the transmission line, and a series circuit including an inductor and a second resistance connected between an output side of the parallel circuit and a ground.
摘要翻译：信号传输电路包括用于向传输线输出发送信号的发送电路，包括电容器的并联电路和连接在发送电路的输出端子与传输线路之间的第一电阻，以及串联电路，包括电感器和连接在并联电路的输出侧和地之间的第二电阻。

3. 发明申请

US20110073352A1 PAIRED LOW-CHARACTERISTIC IMPEDANCE POWER LINE AND GROUND LINE STRUCTURE 审中-公开
标题翻译：配对低特性阻抗电源线和接地线结构
公开(公告)号：US20110073352A1
公开(公告)日：2011-03-31
申请号：US12991929
申请日：2009-05-21
申请人： Kanji Otsuka , Yutaka Akiyama , Toshiyuki Kawaguchi , Kazutoki Tahara
发明人： Kanji Otsuka , Yutaka Akiyama , Toshiyuki Kawaguchi , Kazutoki Tahara
IPC分类号： H05K1/00
CPC分类号： H05K1/0234 , H05K1/0218 , H05K1/0245 , H05K1/025 , H05K1/167 , H05K3/28 , H05K2201/0179 , H05K2201/0317 , H05K2201/09236
摘要： Disclosed is a paired low-characteristic impedance power line and ground line structure in which loop inductance is substantially 0. The paired low-characteristic impedance power line and ground line structure includes a laminated sheet in which a metal wiring layer having a power line and a ground line is provided on the surface of an insulating sheet, an insulating thin-film layer provided so as to cover the power line and the ground line, and a resistive layer provided on the surface of the insulating thin-film layer.
摘要翻译：公开了一种成对的低特性阻抗电力线和接地线结构，其中环路电感基本为零。成对的低特征阻抗电力线和接地线结构包括层压片，其中具有电力线和接地线设置在绝缘片的表面上，设置为覆盖电源线和接地线的绝缘薄膜层，以及设置在绝缘薄膜层的表面上的电阻层。

4. 发明申请

US20110255323A1 MEMORY/LOGIC CONJUGATE SYSTEM 失效
标题翻译：内存/逻辑连接系统
公开(公告)号：US20110255323A1
公开(公告)日：2011-10-20
申请号：US12977243
申请日：2010-12-23
申请人： Kanji Otsuka , Tsuneo Ito , Yoichi Sato , Masahiro Yoshida , Shigeru Yamamoto , Takeshi Koyama , Yuko Tanba , Yutaka Akiyama
发明人： Kanji Otsuka , Tsuneo Ito , Yoichi Sato , Masahiro Yoshida , Shigeru Yamamoto , Takeshi Koyama , Yuko Tanba , Yutaka Akiyama
IPC分类号： G11C5/06
CPC分类号： G06F13/4022 , G11C5/02 , G11C7/1006 , G11C2213/71
摘要： There is a problem that a bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. In an example of a memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories 20 including basic cells 10 arranged in a cluster, the basic cell 10 including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories 20 located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus 11 including a through-via, an arbitrary one of the basic cells 10 is directly accessed through the multibus 11 from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell 10 is switched to a logic circuit as conjugate.
摘要翻译：存在带宽瓶颈的问题，因为使用交叉开关来应对规模的增加。在根据本发明的存储器/逻辑共轭系统的示例中，多个集群存储器芯片，每个集群存储器芯片包括多个集群存储器20，其包括布置在集群中的基本单元10，基本单元10包括存储器电路，以及控制多个集群存储器的控制器芯片是三维堆叠的，沿着多个集群存储器芯片的堆叠方向定位的多个集群存储器20和控制器芯片经由多片11电连接到控制器芯片，通孔中，任意一个基本单元10通过多轴11从控制器芯片直接访问，从而将真值数据写入其中，从而将任意的基本单元10切换到逻辑电路作为共轭。

5. 发明授权

US07872612B2 Antenna apparatus utilizing aperture of transmission line 有权
标题翻译：利用传输线孔径的天线装置
公开(公告)号：US07872612B2
公开(公告)日：2011-01-18
申请号：US12155247
申请日：2008-05-30
申请人： Kanji Otsuka , Tamotsu Usami , Yutaka Akiyama , Chihiro Ueda
发明人： Kanji Otsuka , Tamotsu Usami , Yutaka Akiyama , Chihiro Ueda
IPC分类号： H01Q9/28
CPC分类号： H01Q13/06
摘要： An antenna apparatus utilizing an aperture of transmission line, which is connected to a first transmission line having a predetermined characteristic impedance, includes a tapered line portion, and an aperture portion. The tapered line portion is connected to one end of the transmission line, and the tapered line portion includes a second transmission line including a pair of line conductors. The tapered line portion keeps a predetermined characteristic impedance constant and expands at least one of a width of the transmission line and an interval in a tapered shape at a predetermined taper angle. The aperture portion has a radiation aperture connected to one end of the tapered line portion. A size of one side of the aperture end plane of the aperture portion is set to be equal to or higher than a quarter wavelength of the minimum operating frequency of the antenna apparatus.
摘要翻译：利用连接到具有预定特性阻抗的第一传输线的传输线孔径的天线装置包括锥形线部分和开口部分。锥形线部分连接到传输线的一端，并且锥形线部分包括包括一对线导体的第二传输线。锥形线部分保持预定的特性阻抗恒定，并以预定的锥角将传输线的宽度和间隔的至少一个以锥形形状扩展。开口部分具有连接到锥形线部分的一端的辐射孔。开口部的孔径端面的一侧的尺寸被设定为等于或高于天线装置的最小工作频率的四分之一波长。

6. 发明授权

US07791852B2 Electrostatic discharge protection circuit and terminating resistor circuit 有权
标题翻译：静电放电保护电路和终端电阻电路
公开(公告)号：US07791852B2
公开(公告)日：2010-09-07
申请号：US11819579
申请日：2007-06-28
申请人： Kanji Otsuka , Tamotsu Usami , Yutaka Akiyama , Tsuneo Ito , Yuko Tanba
发明人： Kanji Otsuka , Tamotsu Usami , Yutaka Akiyama , Tsuneo Ito , Yuko Tanba
IPC分类号： H02H3/22
CPC分类号： H01L27/0266
摘要： Disclosed is an electrostatic discharge protection circuit capable of realizing speeding up of differential signals by reducing a capacitance of the circuit. Transmission lines are connected to an IN terminal and an IN Bar terminal and differential signals are input to the terminals. The ESD protection circuit is connected to the transmission lines and protects an internal circuit from a surge voltage applied to the IN terminal and the IN Bar terminal. A pair of transistors of the ESD protection circuit is formed in the same well. Thereby, when differential signals transit, charges in drains of the pair of transistors holding a state before a transition transfer in the same well. As a result, the capacitances in the drains of the pair of transistors are reduced with respect to the transition of differential signals so that the speeding up of differential signals can be realized.
摘要翻译：公开了一种能够通过减小电路的电容来实现差分信号的加速的静电放电保护电路。传输线连接到IN端子，IN条形端子和差分信号输入端子。 ESD保护电路连接到传输线，并保护内部电路免受施加到IN端子和IN Bar端子的浪涌电压。 ESD保护电路的一对晶体管形成在同一个阱中。因此，当差分信号转移时，在同一井内转移转移之前保持状态的一对晶体管的漏极中的电荷。结果，一对晶体管的漏极中的电容相对于差分信号的转变而减小，从而可以实现差分信号的加速。

7. 发明申请

US20080316136A1 Antenna apparatus utilizing aperture of transmission line 有权
标题翻译：利用传输线孔径的天线装置
公开(公告)号：US20080316136A1
公开(公告)日：2008-12-25
申请号：US12155247
申请日：2008-05-30
申请人： Kanji Otsuka , Tamotsu Usami , Yutaka Akiyama , Chihiro Ueda
发明人： Kanji Otsuka , Tamotsu Usami , Yutaka Akiyama , Chihiro Ueda
IPC分类号： H01Q9/28
CPC分类号： H01Q13/06
摘要： An antenna apparatus utilizing an aperture of transmission line, which is connected to a first transmission line having a predetermined characteristic impedance, includes a tapered line portion, and an aperture portion. The tapered line portion is connected to one end of the transmission line, and the tapered line portion includes a second transmission line including a pair of line conductors. The tapered line portion keeps a predetermined characteristic impedance constant and expands at least one of a width of the transmission line and an interval in a tapered shape at a predetermined taper angle. The aperture portion has a radiation aperture connected to one end of the tapered line portion. A size of one side of the aperture end plane of the aperture portion is set to be equal to or higher than a quarter wavelength of the minimum operating frequency of the antenna apparatus.
摘要翻译：利用连接到具有预定特性阻抗的第一传输线的传输线孔径的天线装置包括锥形线部分和开口部分。锥形线部分连接到传输线的一端，并且锥形线部分包括包括一对线导体的第二传输线。锥形线部分保持预定的特性阻抗恒定，并以预定的锥角将传输线的宽度和间隔的至少一个以锥形形状扩展。开口部分具有连接到锥形线部分的一端的辐射孔。开口部的孔径端面的一侧的尺寸被设定为等于或高于天线装置的最小工作频率的四分之一波长。

8. 发明授权

US07446625B2 Narrow impedance conversion device 有权
标题翻译：窄阻抗转换器件
公开(公告)号：US07446625B2
公开(公告)日：2008-11-04
申请号：US11500943
申请日：2006-08-09
申请人： Kanji Otsuka , Tamotsu Usami , Yutaka Akiyama
发明人： Kanji Otsuka , Tamotsu Usami , Yutaka Akiyama
IPC分类号： H03H7/38 , H01P1/16
CPC分类号： H01P5/02
摘要： An impedance conversion device has four conductors arranged so that the first and second conductors form a transmission line having a first characteristic impedance, the third and fourth conductors form a transmission line having the first characteristic impedance, the first and third conductors form a transmission line having a second characteristic impedance, and the second and fourth conductors form a third transmission line having the second characteristic impedance. The second and fourth conductors are interconnected at proximate ends through a resistance equal to the first characteristic impedance. The third and fourth conductors are interconnected at proximate ends through a resistance equal to the second characteristic impedance. The lateral dimensions of the impedance conversion device are small enough to permit insertion in a stacked pair line.
摘要翻译：阻抗转换装置具有四个导体，其布置成使得第一和第二导体形成具有第一特征阻抗的传输线，第三和第四导体形成具有第一特征阻抗的传输线，第一和第三导体形成传输线，第二特征阻抗，第二和第四导体形成具有第二特性阻抗的第三传输线。第二和第四导体通过等于第一特征阻抗的电阻在近端互连。第三和第四导体通过等于第二特征阻抗的电阻在近端互连。阻抗转换装置的横向尺寸足够小以允许插入堆叠的对线。

9. 发明授权

US08736074B2 Multi chip semiconductor device 有权
标题翻译：多芯片半导体器件
公开(公告)号：US08736074B2
公开(公告)日：2014-05-27
申请号：US12624490
申请日：2009-11-24
申请人： Daisuke Iguchi , Kanji Otsuka , Yutaka Akiyama
发明人： Daisuke Iguchi , Kanji Otsuka , Yutaka Akiyama
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/66 , H01L24/17 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2223/6638 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/13099 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2225/0651 , H01L2225/06517 , H01L2225/06531 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： According to an aspect of the invention, a semiconductor device includes a substrate having an opening area, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip has a first electrode for high-speed communication and that is disposed around the opening area on the substrate. The second semiconductor chip has a second electrode and third electrode for power and low-speed communication and that is disposed on the first semiconductor chip so that the first electrode is coupled with the second electrode by electrostatic coupling and dielectric coupling, the third electrode facing the opening area.
摘要翻译：根据本发明的一个方面，半导体器件包括具有开口面积的衬底，第一半导体芯片和第二半导体芯片。第一半导体芯片具有用于高速连通的第一电极，并且设置在基板上的开口区域周围。第二半导体芯片具有用于功率和低速连通的第二电极和第三电极，并且设置在第一半导体芯片上，使得第一电极通过静电耦合和电介质耦合与第二电极耦合，第三电极面向开放区域。

10. 发明授权

US08305789B2 Memory/logic conjugate system 失效
标题翻译：存储器/逻辑共轭系统
公开(公告)号：US08305789B2
公开(公告)日：2012-11-06
申请号：US12977243
申请日：2010-12-23
申请人： Kanji Otsuka , Tsuneo Ito , Yoichi Sato , Masahiro Yoshida , Shigeru Yamamoto , Takeshi Koyama , Yuko Tanba , Yutaka Akiyama
发明人： Kanji Otsuka , Tsuneo Ito , Yoichi Sato , Masahiro Yoshida , Shigeru Yamamoto , Takeshi Koyama , Yuko Tanba , Yutaka Akiyama
IPC分类号： G11C5/06
CPC分类号： G06F13/4022 , G11C5/02 , G11C7/1006 , G11C2213/71
摘要： A bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. A memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories 20 including basic cells 10 arranged in a cluster, the basic cell 10 including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories 20 located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus 11 including a through-via, an arbitrary one of the basic cells 10 is directly accessed through the multibus 11 from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell 10 is switched to a logic circuit as conjugate.
摘要翻译：发生带宽瓶颈是因为使用横杠开关来应对规模的增加。根据本发明的存储器/逻辑共轭系统，多个集群存储器芯片，每个集群存储器芯片包括多个集群存储器20，集群存储器20包括布置在集群中的基本单元10，基本单元10包括存储器电路，以及控制芯片，多个集群存储器是三维堆叠的，沿着多个集群存储器芯片的堆叠方向定位的多个集群存储器20和控制器芯片经由包括通孔的多通道11电耦合到控制器芯片，基本单元10中的任意一个基本单元10通过多轴11从控制器芯片直接访问，从而将真值数据写入其中，并且由此将任意基本单元10切换到逻辑电路作为共轭。

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