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1. 发明申请

US20120243290A1 MULTI-LEVEL ELECTRICAL FUSE USING ONE PROGRAMMING DEVICE 有权
标题翻译：使用一个编程器件的多级电气保险丝
公开(公告)号：US20120243290A1
公开(公告)日：2012-09-27
申请号：US13492635
申请日：2012-06-08
申请人： Yung-Lung Lin , Jui-Jen Wu , Shine Chung , Fu-Lung Hsueh
发明人： Yung-Lung Lin , Jui-Jen Wu , Shine Chung , Fu-Lung Hsueh
IPC分类号： G11C17/16
CPC分类号： G11C11/5692 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method for programming a multi-level electrical fuse system comprises providing a fuse box with an electrical fuse and providing one of at least two fuse writing voltages to the electrical fuse to program the electrical fuse to one of at least two resistance states. The fuse box comprises at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.
摘要翻译：一种用于编程多电平电熔丝系统的方法包括：提供具有电熔丝的保险丝盒，并向所述电熔丝提供至少两个熔丝写入电压中的一个，以将所述电熔丝编程为至少两个电阻状态之一。保险丝盒包括至少一个电熔丝，串联耦合到电熔丝的编程装置，以及耦合到保险丝盒并配置成产生两个或多个电压电平的可变电源。

2. 发明授权

US08619488B2 Multi-level electrical fuse using one programming device 有权
标题翻译：使用一个编程设备的多级电气保险丝
公开(公告)号：US08619488B2
公开(公告)日：2013-12-31
申请号：US13492635
申请日：2012-06-08
申请人： Yung-Lung Lin , Jui-Jen Wu , Shine Chung , Fu-Lung Hsueh
发明人： Yung-Lung Lin , Jui-Jen Wu , Shine Chung , Fu-Lung Hsueh
IPC分类号： G11C17/18 , G11C17/14 , G11C17/16 , G11C17/00
CPC分类号： G11C11/5692 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method for programming a multi-level electrical fuse system comprises providing a fuse box with an electrical fuse and providing one of at least two fuse writing voltages to the electrical fuse to program the electrical fuse to one of at least two resistance states. The fuse box comprises at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.
摘要翻译：一种用于编程多电平电熔丝系统的方法包括：提供具有电熔丝的保险丝盒，并向所述电熔丝提供至少两个熔丝写入电压中的一个，以将所述电熔丝编程为至少两个电阻状态之一。保险丝盒包括至少一个电熔丝，串联耦合到电熔丝的编程装置，以及耦合到保险丝盒并配置成产生两个或多个电压电平的可变电源。

3. 发明申请

US20080217734A1 Multi-level electrical fuse using one programming device 有权
标题翻译：使用一个编程设备的多级电气保险丝
公开(公告)号：US20080217734A1
公开(公告)日：2008-09-11
申请号：US11715631
申请日：2007-03-08
申请人： Yung-Lung Lin , Jui-Jen Wu , Shine Chung , Fu-Lung Hsuen
发明人： Yung-Lung Lin , Jui-Jen Wu , Shine Chung , Fu-Lung Hsuen
IPC分类号： H01L29/00
CPC分类号： G11C11/5692 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A multi-level electrical fuse system comprises at least one fuse box having at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.
摘要翻译：多级电熔丝系统包括至少一个具有至少一个电熔丝的保险丝盒，串联耦合到电熔丝的编程装置，以及耦合到保险丝盒并被配置成产生两个或多个电压电平的可变电源。

4. 发明授权

US08223575B2 Multi-level electrical fuse using one programming device 有权
标题翻译：使用一个编程设备的多级电气保险丝
公开(公告)号：US08223575B2
公开(公告)日：2012-07-17
申请号：US11715631
申请日：2007-03-08
申请人： Yung-Lung Lin , Jui-Jen Wu , Shine Chung , Fu-Lung Hsuen
发明人： Yung-Lung Lin , Jui-Jen Wu , Shine Chung , Fu-Lung Hsuen
IPC分类号： G11C17/18 , G11C17/14 , G11C17/16 , G11C17/00
CPC分类号： G11C11/5692 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A multi-level electrical fuse system comprises at least one fuse box having at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.
摘要翻译：多级电熔丝系统包括至少一个具有至少一个电熔丝的保险丝盒，串联耦合到电熔丝的编程装置，以及耦合到保险丝盒并被配置为产生两个或多个电压电平的可变电源。

5. 发明授权

US07577052B2 Power switching circuit 有权
标题翻译：电源开关电路
公开(公告)号：US07577052B2
公开(公告)日：2009-08-18
申请号：US11638187
申请日：2006-12-13
申请人： Jui-Jen Wu , Kun-Lung Chen , Hung-Jen Liao , Yung-Lung Lin , Chen Yen-Huei , Dao-Ping Wang
发明人： Jui-Jen Wu , Kun-Lung Chen , Hung-Jen Liao , Yung-Lung Lin , Chen Yen-Huei , Dao-Ping Wang
IPC分类号： G11C5/10
CPC分类号： G11C11/412 , G11C11/413
摘要： A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to a control signal, a third terminal coupled to a first storage node of at least one tracking cell, a fourth terminal coupled to a second storage node of the tracking cell, and a fifth terminal coupled to the power node of the integrated circuit module, for controlling the switch device to pass the supply voltage to the power node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module.
摘要翻译：用于集成电路模块的功率控制电路包括耦合在电源电压和集成电路模块的功率节点之间的至少一个开关装置; 以及开关控制模块，其具有耦合到所述开关装置的第一端子，耦合到控制信号的第二端子，耦合到至少一个跟踪单元的第一存储节点的第三端子，耦合到所述至少一个跟踪单元的第二存储节点的第四端子跟踪单元和耦合到集成电路模块的功率节点的第五端子，用于根据集成电路模块的操作模式控制开关装置将电源电压传递到功率节点，具有或不具有实质的电压降。

6. 发明申请

US20080158939A1 MEMORY HAVING IMPROVED POWER DESIGN 有权
标题翻译：具有改进功率设计的记忆
公开(公告)号：US20080158939A1
公开(公告)日：2008-07-03
申请号：US11619103
申请日：2007-01-02
申请人： Yen-Huei Chen , Hung-Jen Liao , Kun-Lung Chen , Jui-Jen Wu , Yung-Lung Lin , Dao-Ping Wang
发明人： Yen-Huei Chen , Hung-Jen Liao , Kun-Lung Chen , Jui-Jen Wu , Yung-Lung Lin , Dao-Ping Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： A memory includes a plurality of cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein each cell is capable of storing a bit. Each cell is coupled between a first power supply node that receives a power supply voltage and a second power supply node that receives a second voltage. A plurality of word lines are associated with the memory cells and supplied by a third voltage in read or write operation. The third voltage is a suppressed power supply voltage. The second voltage is negative in read operation and positive in write operation.
摘要翻译：存储器包括以具有多个行和多个列的矩阵的形式排列的多个单元，其中每个单元能够存储位。每个单元耦合在接收电源电压的第一电源节点和接收第二电压的第二电源节点之间。多个字线与存储器单元相关联并且在读或写操作中由第三电压提供。第三电压是抑制电源电压。读操作中的第二电压为负，写操作为正。

7. 发明授权

US07505319B2 Method and apparatus for high efficiency redundancy scheme for multi-segment SRAM 有权
标题翻译：用于多段SRAM高效冗余方案的方法和装置
公开(公告)号：US07505319B2
公开(公告)日：2009-03-17
申请号：US11669667
申请日：2007-01-31
申请人： Jui-Jen Wu , Yung-Lung Lin , Yen-Huei Chen , Dao-Ping Wang
发明人： Jui-Jen Wu , Yung-Lung Lin , Yen-Huei Chen , Dao-Ping Wang
IPC分类号： G11C11/34
CPC分类号： G11C29/808
摘要： The disclosure generally relates to a method and apparatus for a high efficiency redundancy scheme for a memory system. In one embodiment, the disclosure relates to a memory circuit having: a memory array defined by a plurality of memory cells arranged in one or more columns and one or more rows, each memory cell communicating with one of a pair of complementary bit-lines and with a word-line; a plurality of IO circuits, each IO circuit associated with one of the plurality of memory cell columns; a plurality of redundant bit-lines, each redundant bit line communicating with a redundant bit cell; a first circuit for detecting a defective memory cell in said memory circuit; a second circuit for selecting one of the plurality of redundant bit-lines for switching from the failed memory cell to the redundant memory cell; and a third circuit for directing a word-line pulse of said defective memory cell to said selected redundant memory cell.
摘要翻译：本公开一般涉及用于存储器系统的高效冗余方案的方法和装置。在一个实施例中，本公开涉及一种存储器电路，其具有：由多个存储单元限定的存储器阵列，所述多个存储器单元被布置成一列或多列和一行或多行，每个存储器单元与一对互补位线中的一个通信，用字线; 多个IO电路，与所述多个存储单元列之一相关联的每个IO电路; 多个冗余位线，每个冗余位线与冗余位单元通信; 用于检测所述存储电路中的有缺陷的存储单元的第一电路; 用于选择所述多个冗余位线中的一个用于从所述故障存储器单元切换到所述冗余存储器单元的第二电路; 以及用于将所述有缺陷的存储器单元的字线脉冲引导到所述选择的冗余存储单元的第三电路。

8. 发明授权

US07271644B2 Multi-state electrical fuse 有权
标题翻译：多态电保险丝
公开(公告)号：US07271644B2
公开(公告)日：2007-09-18
申请号：US11328780
申请日：2006-01-10
申请人： Yung-Lung Lin , Jui-Jen Wu , Hung-Jen Liao
发明人： Yung-Lung Lin , Jui-Jen Wu , Hung-Jen Liao
IPC分类号： H01H37/76 , H01H85/00
CPC分类号： G11C11/56 , G11C17/18
摘要： An integrated circuit for programming an electrical fuse includes a first programming device coupled to the electrical fuse for selectively providing the same with a first programming current, and a second programming device coupled to the electrical fuse for selectively providing the same with a second programming current. A detection module is coupled to the electrical fuse for generating an output indicating a resistance level of the electrical fuse, wherein the resistance level has three or more predetermined states, which are provided by selectively programming the electrical fuse with the first or second programming current.
摘要翻译：用于编程电熔丝的集成电路包括耦合到电熔丝的第一编程装置，用于选择性地为其提供第一编程电流;以及耦合到电熔丝的第二编程装置，用于选择性地将其提供给第二编程电流。检测模块耦合到电熔丝，用于产生指示电熔丝的电阻电平的输出，其中电阻电平具有三个或更多个预定状态，这些状态通过用第一或第二编程电流选择性地编程电熔丝来提供。

9. 发明申请

US20080184064A1 METHOD AND APPARATUS FOR HIGH EFFICIENCY REDUNDANCY SCHEME FOR MULTI-SEGMENT SRAM 有权
标题翻译：多部分SRAM高效冗余方案的方法与装置
公开(公告)号：US20080184064A1
公开(公告)日：2008-07-31
申请号：US11669667
申请日：2007-01-31
申请人： Jui-Jen Wu , Yung-Lung Lin , Yen-Huei Chen , Dao-Ping Wang
发明人： Jui-Jen Wu , Yung-Lung Lin , Yen-Huei Chen , Dao-Ping Wang
IPC分类号： G06F11/16
CPC分类号： G11C29/808
摘要： The disclosure generally relates to a method and apparatus for a high efficiency redundancy scheme for a memory system. In one embodiment, the disclosure relates to a memory circuit having: a memory array defined by a plurality of memory cells arranged in one or more columns and one or more rows, each memory cell communicating with one of a pair of complementary bit-lines and with a word-line; a plurality of IO circuits, each IO circuit associated with one of the plurality of memory cell columns; a plurality of redundant bit-lines, each redundant bit line communicating with a redundant bit cell; a first circuit for detecting a defective memory cell in said memory circuit; a second circuit for selecting one of the plurality of redundant bit-lines for switching from the failed memory cell to the redundant memory cell; and a third circuit for directing a word-line pulse of said defective memory cell to said selected redundant memory cell.
摘要翻译：本公开一般涉及用于存储器系统的高效冗余方案的方法和装置。在一个实施例中，本公开涉及一种存储器电路，其具有：由多个存储单元限定的存储器阵列，所述多个存储器单元被布置成一列或多列和一行或多行，每个存储器单元与一对互补位线中的一个通信，用字线; 多个IO电路，与所述多个存储单元列之一相关联的每个IO电路; 多个冗余位线，每个冗余位线与冗余位单元通信; 用于检测所述存储器电路中的有缺陷的存储单元的第一电路; 用于选择所述多个冗余位线中的一个用于从所述故障存储器单元切换到所述冗余存储器单元的第二电路; 以及用于将所述有缺陷的存储器单元的字线脉冲引导到所述选择的冗余存储单元的第三电路。

10. 发明申请

US20070159231A1 Multi-state electrical fuse 有权
公开(公告)号：US20070159231A1
公开(公告)日：2007-07-12
申请号：US11328780
申请日：2006-01-10
申请人： Yung-Lung Lin , Jui-Jen Wu , Hung-Jen Liao
发明人： Yung-Lung Lin , Jui-Jen Wu , Hung-Jen Liao
IPC分类号： H01H37/76
CPC分类号： G11C11/56 , G11C17/18
摘要： An integrated circuit for programming an electrical fuse includes a first programming device coupled to the electrical fuse for selectively providing the same with a first programming current, and a second programming device coupled to the electrical fuse for selectively providing the same with a second programming current. A detection module is coupled to the electrical fuse for generating an output indicating a resistance level of the electrical fuse, wherein the resistance level has three or more predetermined states, which are provided by selectively programming the electrical fuse with the first or second programming current.

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