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1. 发明授权

US06706542B1 Application of InAIAs double-layer to block dopant out-diffusion in III-V device Fabrication 有权
标题翻译： InAIAs双层在III-V器件制造中阻挡掺杂物扩散的应用
公开(公告)号：US06706542B1
公开(公告)日：2004-03-16
申请号：US09645913
申请日：2000-08-25
申请人： Michael Geva , Yuliya Anatolyevna Akulova , Abdallah Ougazzaden
发明人： Michael Geva , Yuliya Anatolyevna Akulova , Abdallah Ougazzaden
IPC分类号： H01L2100
CPC分类号： H01S5/227 , H01L21/2205 , H01L33/02 , H01L33/305 , H01S5/2209 , H01S5/221 , H01S5/2224 , H01S5/2226 , H01S5/2227 , H01S5/2272 , H01S5/3072
摘要： The present invention relates to a multi-layer dopant barrier and its method of fabrication for use in semiconductor structures. In an illustrative embodiment, the multi-layer dopant barrier is disposed between a first doped layer and a second doped layer. The multi-layer dopant barrier further includes a first dopant blocking layer adjacent the first doped layer and a second dopant blocking layer adjacent the second doped layer. A technique for fabricating the multi layer dopant barrier is disclosed. A first dopant blocking layer is formed at a first temperature, and a second dopant blocking layer is formed at a second temperature over the first barrier layer.
摘要翻译：本发明涉及一种用于半导体结构的多层掺杂剂阻挡层及其制造方法。在说明性实施例中，多层掺杂剂阻挡层设置在第一掺杂层和第二掺杂层之间。多层掺杂剂阻挡层还包括与第一掺杂层相邻的第一掺杂剂阻挡层和与第二掺杂层相邻的第二掺杂剂阻挡层。公开了一种用于制造多层掺杂剂阻挡层的技术。在第一温度下形成第一掺杂剂阻挡层，并且在第一阻挡层上的第二温度下形成第二掺杂剂阻挡层。

2. 发明授权

US06819695B1 Dopant diffusion barrier layer for use in III-V structures 有权
标题翻译：用于III-V结构的掺杂扩散阻挡层
公开(公告)号：US06819695B1
公开(公告)日：2004-11-16
申请号：US09540471
申请日：2000-03-31
申请人： Yuliya Anatolyevna Akulova , Michael Geva , Abdallah Ougazzaden
发明人： Yuliya Anatolyevna Akulova , Michael Geva , Abdallah Ougazzaden
IPC分类号： H01S500
CPC分类号： H01S5/227 , H01L21/2205 , H01L33/02 , H01L33/305 , H01S5/2209 , H01S5/221 , H01S5/2224 , H01S5/2226 , H01S5/2227 , H01S5/2272 , H01S5/3072
摘要： A multi-layer dopant diffusion barrier is disclosed that effectively prevents dopant diffusion but does not contribute to parasitic pn junctions or parasitic capacitance. A multi-layer dopant diffusion barrier layer prevents dopant diffusion.
摘要翻译：公开了一种多层掺杂剂扩散阻挡层，其有效地防止掺杂剂扩散，但不会对寄生pn结或寄生电容有贡献。多层掺杂剂扩散阻挡层防止掺杂剂扩散。

3. 发明授权

US06437372B1 Diffusion barrier spikes for III-V structures 有权
标题翻译： III-V结构的扩散屏障尖峰
公开(公告)号：US06437372B1
公开(公告)日：2002-08-20
申请号：US09540474
申请日：2000-03-31
申请人： Michael Geva , Jayatirtha N Holavanahalli , Abdallah Ougazzaden , Lawrence Edwin Smith
发明人： Michael Geva , Jayatirtha N Holavanahalli , Abdallah Ougazzaden , Lawrence Edwin Smith
IPC分类号： H01L3300
CPC分类号： G02F1/017 , B82Y20/00 , G02F2202/102 , H01L33/305 , H01S5/221 , H01S5/2224 , H01S5/2227 , H01S5/227 , H01S5/2275 , H01S5/3072
摘要： A diffusion preventing barrier spike is disclosed. The spike prevents diffusion of dopants into another layer without forming a pn junction in the layer. The spikes are illustratively Al or an aluminum containing material such as AlAs and have a thickness on the order of 1 nm. The spikes of the present invention may be used to stop dopant diffusion out of a doped layer in a variety of III-V semiconductor structures, such a InP-based PIN devices.
摘要翻译：公开了防扩散阻挡尖峰。尖峰防止掺杂剂扩散到另一层中而不在该层中形成pn结。尖峰示例性地为Al或含铝材料如AlAs，并且具有约1nm的厚度。本发明的尖峰可用于阻止掺杂剂扩散到各种III-V半导体结构中的掺杂层，例如基于InP的PIN器件。

4. 发明授权

US06664605B1 Dopant diffusion blocking for optoelectronic devices using InAlAs and/or InGaAlAs 有权
标题翻译：使用InAlAs和/或InGaAlAs的光电器件的掺杂扩散阻挡
公开(公告)号：US06664605B1
公开(公告)日：2003-12-16
申请号：US09539882
申请日：2000-03-31
申请人： Yuliya A. Akulova , Sung-nee G. Chu , Michael Geva , Mark S. Hybertsen , Charles W. Lentz , Abdallah Ougazzaden
发明人： Yuliya A. Akulova , Sung-nee G. Chu , Michael Geva , Mark S. Hybertsen , Charles W. Lentz , Abdallah Ougazzaden
IPC分类号： H01L310232
CPC分类号： H01S5/227 , G02F1/025 , H01S5/221 , H01S5/2213 , H01S5/2226 , H01S5/3072 , H01S5/50
摘要： A method for decreasing the diffusion of dopant atoms in the active region, as well as the interdiffuision of different types of dopant atoms among adjacent doped regions, of optoelectronic devices is disclosed. The method of the present invention employs a plurality of InAlAs and/or InGaAlAs layers to avoid the direct contact between the dopant atoms and the active region, and between the dopant atoms in adjacent blocking structures of optoelectronic devices. A semi-insulating buried ridge structure, as well as a ridge structure, in which the interdiffusion of different types of dopant atoms is suppressed are also disclosed.
摘要翻译：公开了一种用于减少有源区中的掺杂剂原子的扩散以及相邻掺杂区中不同类型的掺杂剂原子在光电器件中的相互扩散的方法。本发明的方法采用多个InAlAs和/或InGaAlAs层以避免掺杂剂原子与有源区之间以及光电子器件的相邻阻挡结构中的掺杂剂原子之间的直接接触。还公开了抑制不同类型的掺杂剂原子的相互扩散的半绝缘掩埋隆起结构以及脊结构。

5. 发明申请

US20140050243A1 CMOS-COMPATIBLE GOLD-FREE CONTACTS 有权
标题翻译： CMOS兼容的GOLD-FREE CONTACTS
公开(公告)号：US20140050243A1
公开(公告)日：2014-02-20
申请号：US13995689
申请日：2011-12-22
申请人： Siddharth Jain , John Bowers , Matthew Sysak , John Heck , Ran Feldesh , Richard Jones , Yoel Shetrit , Michael Geva
发明人： Siddharth Jain , John Bowers , Matthew Sysak , John Heck , Ran Feldesh , Richard Jones , Yoel Shetrit , Michael Geva
IPC分类号： H01L23/00
CPC分类号： H01L24/45 , H01L21/28575 , H01L21/823814 , H01L21/823871 , H01L21/8258 , H01L27/1203 , H01L29/20 , H01L29/452 , H01L2224/45 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/12042 , H01S5/021 , H01S5/0425 , H01L2924/00 , H01L2224/45099 , H01L2224/43
摘要： A semiconductor metallurgy includes a ratio of germanium and palladium that provides low contact resistance to both n-type material and p-type material. The metallurgy allows for a contact that does not include gold and is compatible with mass-production CMOS techniques. The ratio of germanium and palladium can be achieved by stacking layers of the materials and annealing the stack, or simultaneously depositing the germanium and palladium on the material where the contact is to be manufactured.
摘要翻译：半导体冶金学包括对n型材料和p型材料提供低接触电阻的锗和钯的比例。冶金允许不包括金的接触，并且与大规模生产CMOS技术兼容。锗和钯的比例可以通过堆叠材料的层并退火叠层来实现，或者同时将锗和钯沉积在要制造接触的材料上。

6. 发明授权

US4755671A Method and apparatus for separating ions of differing charge-to-mass ratio 失效
标题翻译：用于分离不同电荷与质量比的离子的方法和装置
公开(公告)号：US4755671A
公开(公告)日：1988-07-05
申请号：US824828
申请日：1986-01-31
申请人： Lazar Friedland , Michael Geva , Jay Hirshfield
发明人： Lazar Friedland , Michael Geva , Jay Hirshfield
IPC分类号： B01D59/44 , H01J49/30
CPC分类号： B01D59/44
摘要： A method and apparatus for separating plural isotopes of a chemical substance is disclosed. The apparatus comprises a first magnetic field generating device for generating a uniform axial first magnetic field and a second magnetic field generating device such as a wiggler for generating a non-uniform, twisted, second magnetic field. An ion source provides a stream of ions of isotopes to be separated, the stream passing through the first and second magnetic fields. Ions of different charge-to-mass ratio will follow different trajectories or paths through the magnetic fields. A collector is positioned with respect to the second magnetic field generating device such that only the ions of isotopes to be collected strike the collector means and are collected thereon. The method includes generating the first and second magnetic fields and passing a stream of ions to be separated through the first and second magnetic field, whereby ions of different charge-to-mass ratio travel along different predetermined paths or trajectories. The ions of the isotope following at least one of the predetermined paths are then collected.
摘要翻译：公开了一种用于分离化学物质的多个同位素的方法和装置。该装置包括用于产生均匀的轴向第一磁场的第一磁场产生装置和用于产生不均匀的扭转的第二磁场的诸如摆动器的第二磁场产生装置。离子源提供待分离的同位素离子流，该流通过第一和第二磁场。不同电荷质量比的离子将遵循通过磁场的不同轨迹或路径。收集器相对于第二磁场产生装置定位，使得只有待收集的同位素的离子撞击收集器装置并在其上收集。该方法包括产生第一和第二磁场并使待分离的离子流通过第一和第二磁场，由此不同电荷质量比的离子沿着不同的预定路径或轨迹行进。然后收集遵循至少一个预定路径的同位素离子。

7. 发明授权

US09252118B2 CMOS-compatible gold-free contacts 有权
标题翻译： CMOS兼容的无金触点
公开(公告)号：US09252118B2
公开(公告)日：2016-02-02
申请号：US13995689
申请日：2011-12-22
申请人： Siddharth Jain , John Bowers , Matthew Sysak , John Heck , Ran Feldesh , Richard Jones , Yoel Shetrit , Michael Geva
发明人： Siddharth Jain , John Bowers , Matthew Sysak , John Heck , Ran Feldesh , Richard Jones , Yoel Shetrit , Michael Geva
IPC分类号： H01S5/042 , H01L23/00 , H01L21/8238 , H01L21/8258 , H01L21/285 , H01L29/45 , H01L27/12 , H01L29/20 , H01S5/02
CPC分类号： H01L24/45 , H01L21/28575 , H01L21/823814 , H01L21/823871 , H01L21/8258 , H01L27/1203 , H01L29/20 , H01L29/452 , H01L2224/45 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/12042 , H01S5/021 , H01S5/0425 , H01L2924/00 , H01L2224/45099 , H01L2224/43
摘要： A semiconductor metallurgy includes a ratio of germanium and palladium that provides low contact resistance to both n-type material and p-type material. The metallurgy allows for a contact that does not include gold and is compatible with mass-production CMOS techniques. The ratio of germanium and palladium can be achieved by stacking layers of the materials and annealing the stack, or simultaneously depositing the germanium and palladium on the material where the contact is to be manufactured.
摘要翻译：半导体冶金学包括对n型材料和p型材料提供低接触电阻的锗和钯的比例。冶金允许不包括金的接触，并且与大规模生产CMOS技术兼容。锗和钯的比例可以通过堆叠材料的层并退火叠层来实现，或者同时将锗和钯沉积在要制造接触的材料上。

8. 发明授权

US06520348B1 Multiple inclined wafer holder for improved vapor transport and reflux for sealed ampoule diffusion process 有权
标题翻译：多个倾斜的晶片支架，用于改善蒸汽输送和回流，用于密封安瓿扩散过程
公开(公告)号：US06520348B1
公开(公告)日：2003-02-18
申请号：US09542622
申请日：2000-04-04
申请人： Dutt V. Bulusu , Robert L. Mcanally , Michael Geva , Gustav E. Derkits , Robert A. Resta
发明人： Dutt V. Bulusu , Robert L. Mcanally , Michael Geva , Gustav E. Derkits , Robert A. Resta
IPC分类号： A47G1908
CPC分类号： H01L21/67313 , Y10S414/138
摘要： An apparatus and method for diffusion annealing impurities onto a plurality of wafers is described. A hollow wafer holder includes a plurality of first and second slots. The first slots are sized and shaped to receive a pair of wafers. The first slots are angled relative to a longitudinal axis of the wafer holder. The wafer holder is positioned at a first location within an ampoule, with a diffusion source being positioned at a second location within the ampoule. The ampoule is sealed and placed within or near a heat source. The heat source alters the physical state of the diffusion source to allow the entrained impurities to diffuse throughout the ampoule. The inclination of the first slots allows a sufficient clearance between the wafers and the ampoule to allow impurities within a gaseous diffusion source to extend throughout the ampoule. The presence of the second slots allows a more uniform diffusion of the impurities to the wafers.
摘要翻译：描述了将杂质扩散到多个晶片上的装置和方法。中空晶片保持器包括多个第一和第二槽。第一槽的尺寸和形状适于接收一对晶片。第一狭槽相对于晶片保持器的纵向轴线成角度。晶片保持器位于安瓿内的第一位置处，扩散源位于安瓿内的第二位置。将安瓿密封并置于热源内或附近。热源改变扩散源的物理状态，以允许夹带的杂质扩散到整个安瓿中。第一槽的倾斜允许晶片和安瓿之间的足够的间隙允许气体扩散源中的杂质延伸贯穿整个安瓿。第二槽的存在允许杂质更均匀地扩散到晶片。

9. 发明授权

US06542686B1 Optoelectronic device including a barrier layer and interface barrier layer and a method of manufacture thereof 有权
标题翻译：包括阻挡层和界面阻挡层的光电器件及其制造方法
公开(公告)号：US06542686B1
公开(公告)日：2003-04-01
申请号：US09648159
申请日：2000-08-25
申请人： Michael Geva , Claude Lewis Reynolds, Jr. , Lawrence E. Smith
发明人： Michael Geva , Claude Lewis Reynolds, Jr. , Lawrence E. Smith
IPC分类号： G02B610
CPC分类号： G02B6/132 , G02B6/131
摘要： The present invention provides an optoelectronic device and a method of manufacture therefor, that prevents dopant diffusion and controls the dopant concentration therein. The optoelectronic device includes an active region formed over a substrate, and an interface barrier layer and barrier layer located over the active region. The optoelectronic device further includes an upper cladding layer located over the interface barrier layer and the barrier layer. In an exemplary embodiment of the invention, the interface barrier layer is an indium phosphide interface barrier layer and the barrier layer is an indium gallium arsenide phosphide barrier layer.
摘要翻译：本发明提供一种光电器件及其制造方法，其防止掺杂剂扩散并控制其中的掺杂剂浓度。光电子器件包括在衬底上形成的有源区，以及位于有源区上方的界面阻挡层和阻挡层。光电子器件还包括位于界面阻挡层和阻挡层之上的上覆层。在本发明的示例性实施例中，界面阻挡层是磷化铟界面阻挡层，阻挡层是砷化镓磷化物阻挡层。

10. 发明授权

US5232873A Method of fabricating contacts for semiconductor devices 失效
标题翻译：制造半导体器件触点的方法
公开(公告)号：US5232873A
公开(公告)日：1993-08-03
申请号：US960526
申请日：1992-10-13
申请人： Michael Geva , Avishay Katz
发明人： Michael Geva , Avishay Katz
IPC分类号： H01L21/28 , H01L21/223 , H01L21/285 , H01L29/43
CPC分类号： H01L21/285 , H01L21/2233 , H01L21/28575 , Y10S148/11
摘要： A semiconductor device substrate has a major surface on which is located an insulating layer, such as silicon dioxide, having an aperture penetrating through it all the way down to the major surface. An impurity-doped plug, such as tungsten doped with zinc, is spatially selectively deposited in the aperture to a thickness such that the height of the plug is significantly less than the height of the aperture in the insulating layer, by means of a rapid-thermal-cycle low-pressure-metalorganic-chemical vapor deposition (RTC-LP-MOCVD) process. Then another plug, of (pure) conductive barrier metal such as tungsten, is deposited on at least the entire top surface of the impurity-doped plug and on the sidewalls of the insulating layer. The structure being fabricated can then be heated, in order to diffuse the impurity into the underlying semiconductor device substrate. A metallization layer such as titanium/platinum/gold can be deposited on the (pure) conductive barrier metal and patterned, in order to supply a desired access metallization for the device.

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