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1. 发明授权

US5208773A Semiconductor memory device having bit lines and word lines different in data reading and data writing 失效
标题翻译：具有位线和字线的半导体存储器件数据读取和数据写入不同
公开(公告)号：US5208773A
公开(公告)日：1993-05-04
申请号：US669437
申请日：1991-03-13
申请人： Takenori Okitaka , Yasunori Maeda , Yukio Miyazaki
发明人： Takenori Okitaka , Yasunori Maeda , Yukio Miyazaki
IPC分类号： G11C11/405 , G11C7/12 , G11C11/401 , G11C11/409 , H01L21/8242 , H01L27/108
CPC分类号： G11C7/12
摘要： Disclosed is the serial access memory having the improved precharging system of reading bit lines (4). In this serial access memory, an address pointer (9, 114) outputs a signal for selecting one of the reading bit lines (4). Meanwhile, each reading bit line (4) is provided with an MOS transistor (7) for precharging the same. By using the output of the address pointer (9, 114) to control on/off of the MOS transistor (7), the period when each reading bit line (4) is precharged is limited within the period when the reading bit line is selected. As a result, current flowing through the reading bit lines (4) during the data reading can be reduced to achieve the reduction in power consumption of the serial access memory and the increase in the operation speed.
摘要翻译：公开了具有读取位线（4）的改进的预充电系统的串行存取存储器。在该串行访问存储器中，地址指针（9,114）输出用于选择读取位线（4）之一的信号。同时，每个读取位线（4）都设置有用于对其进行预充电的MOS晶体管（7）。通过使用地址指针（9,114）的输出来控制MOS晶体管（7）的导通/截止，每个读取位线（4）被预充电的周期在选择读取位线的时段内被限制。结果，可以减少在数据读取期间流过读取位线（4）的电流，以实现串行存取存储器的功耗的降低和操作速度的提高。

2. 发明授权

US5103423A Dynamic random access memory and a method of operating the same 失效
标题翻译：动态随机存取存储器及其操作方法
公开(公告)号：US5103423A
公开(公告)日：1992-04-07
申请号：US657778
申请日：1991-02-20
申请人： Yukio Miyazaki , Takenori Okitaka , Yasunori Maeda
发明人： Yukio Miyazaki , Takenori Okitaka , Yasunori Maeda
IPC分类号： G11C7/10 , G11C11/401 , G11C11/405 , G11C11/4096
CPC分类号： G11C11/405 , G11C11/4096 , G11C7/1006
摘要： A dynamic RAM includes a memory cell comprised of a data read transistor, a data write transistor and a data storage capacitor. The data write transistor is turned on in response to a row selection signal to connect the capacitor to a write bit line. The dynamic RAM includes a structure for shifting the level of potential of internal write data to be transmitted onto the write bit line. This structure will prevent the data write transistor from being turned on by the undershoot produced on the write bit line.
摘要翻译：动态RAM包括由数据读取晶体管，数据写入晶体管和数据存储电容器构成的存储单元。数据写晶体管响应于行选择信号而导通，以将电容器连接到写位线。动态RAM包括用于将待发送的内部写入数据的电位电平移位到写入位线的结构。该结构将防止数据写入晶体管由写位线上产生的下冲导通。

3. 发明授权

US5491438A Synchronized clock generating apparatus 失效
标题翻译：同步时钟发生装置
公开(公告)号：US5491438A
公开(公告)日：1996-02-13
申请号：US289837
申请日：1994-08-12
申请人： Yukio Miyazaki , Takenori Okitaka , Makoto Hatakenaka , Junji Mano
发明人： Yukio Miyazaki , Takenori Okitaka , Makoto Hatakenaka , Junji Mano
IPC分类号： G06F1/10 , H03K5/00 , H03K5/13 , H04L7/033 , H03L7/00
CPC分类号： H04L7/0338 , G06F1/10 , H03K5/133 , H03K2005/00234
摘要： A synchronized clock generating apparatus includes a delayed clock generating circuit including a plurality of serially connected delaying elements for generating delayed clock signals delayed successively relative to an incoming basic clock signal. Storage means includes a plurality of storage elements storing therein a predetermined level in response to transitions occurring in associated ones of said basic and delayed clock signals after a trigger signal which is asynchronous with the basic clock signal is applied thereto. A clock selection logic circuit is controlled by the output signal of the storage means for detecting the clock signal transition occurring closest in time to the application of the asynchronous trigger signal, and for selecting a desired one of said clock signals, based on the result of the detection, as a synchronized clock signal output.
摘要翻译：同步时钟发生装置包括延迟时钟产生电路，其包括多个串行连接的延迟元件，用于产生相对于输入的基本时钟信号连续延迟的延迟时钟信号。存储装置包括多个存储元件，其中，在施加与基本时钟信号异步的触发信号之后，响应于在相关联的所述基本和延迟的时钟信号中发生的转换，存储其中的预定电平。时钟选择逻辑电路由存储装置的输出信号控制，用于检测在施加异步触发信号时在时间上最近发生的时钟信号转换，并且基于所述时钟信号的结果来选择期望的一个时钟信号检测，作为同步时钟信号输出。

4. 发明授权

US4806802A CMOS circuit having shoot through current control 失效
标题翻译： CMOS电路具有直通电流控制
公开(公告)号：US4806802A
公开(公告)日：1989-02-21
申请号：US91132
申请日：1987-08-31
申请人： Takenori Okitaka , Yukio Miyazaki
发明人： Takenori Okitaka , Yukio Miyazaki
IPC分类号： H03K19/00 , H03K19/003 , H03K19/094 , H03K17/16 , H03K17/26 , H03K17/687
CPC分类号： H03K19/09429 , H03K19/0013 , H03K19/00361
摘要： A complemenary MOS integrated circuit comprising an output circuit and a pre-output circuit, which is capable of reducing a penetration current which occurs upon switching of transistors in the output circuit, to thereby suppress an occurrence of spike noises in an output signal. The pre-output circuit comprises MOS transistors constituting an analog switch, "on-resistances" of which are utilized as a resistor, and MOS transistor gates. A series circuit of the analog switch and the gates are coupled in series with a power source.
摘要翻译：一种补充MOS集成电路，包括输出电路和预输出电路，其能够减少在输出电路中的晶体管切换时发生的穿透电流，从而抑制输出信号中的尖峰噪声的发生。预输出电路包括构成模拟开关的MOS晶体管，“导通电阻”用作电阻器，MOS晶体管栅极。模拟开关和栅极的串联电路与电源串联耦合。

5. 发明授权

US5206834A Semiconductor memory device performing last in-first out operation and the method for controlling the same 失效
标题翻译：执行最先进先出操作的半导体存储器件及其控制方法
公开(公告)号：US5206834A
公开(公告)日：1993-04-27
申请号：US850203
申请日：1992-03-12
申请人： Takenori Okitaka , Yasunori Maeda
发明人： Takenori Okitaka , Yasunori Maeda
IPC分类号： G06F7/78
CPC分类号： G06F7/785
摘要： A LIFO device includes a plurality of memory circuits (1), a write address pointer (2) and a read-out address pointer (3). The write address pointer (2) selects the memory circuit (1) in which data are to be written, while the read-out address pointer (3) selects the memory circuit (1) from which data are to be read out. Each of the write address pointer (2) and the read-out address pointer (3) alternately and repeatedly performs the count-up operation for selecting the memory circuits in a predetermined sequence and the count-down operation of selecting the memory circuits in a sequence which is the reverse of the predetermined sequence. Control is also so made that the selection by the read-out address pointer (3) precedes the selection by the write address pointer (2).
摘要翻译： LIFO装置包括多个存储器电路（1），写入地址指针（2）和读出地址指针（3）。写地址指针（2）选择要写入数据的存储器电路（1），而读出地址指针（3）选择要读出数据的存储电路（1）。写地址指针（2）和读出地址指针（3）中的每一个交替重复执行用于按预定顺序选择存储电路的计数操作，以及选择存储电路的递减计数操作序列与预定序列相反。控制也使得读出地址指针（3）的选择在写地址指针（2）的选择之前。

6. 发明授权

US4837463A Three-state complementary field effect integrated circuit 失效
标题翻译：三态互补场效应集成电路
公开(公告)号：US4837463A
公开(公告)日：1989-06-06
申请号：US129940
申请日：1987-12-03
申请人： Takenori Okitaka , Yukio Miyazaki
发明人： Takenori Okitaka , Yukio Miyazaki
IPC分类号： H03K19/00 , H03K19/003 , H03K19/0185 , H03K19/094
CPC分类号： H03K19/00361 , H03K19/0013 , H03K19/09429
摘要： A three-state complementary field effect integrated circuit comprises an output pre-stage circuit (11) connected to an input terminal (1) and a first and second control input (6, 5) and comprising a series connection of a first switching circuit (9), a second switching circuit (7, 8) having resistances (P5, N5) and a third switching means (10); an output circuit (12) comprising a series connection of a p type and an n type field effect transistors (P1, N1) with capacitors (C1, C2) connected between respective gates and the ground (GND). When the voltages of H and L level are applied to the first and second control input (6, 5), the resistance (P5, N5) comprised in the second switching means and the capacitors (C1, C2) connected to the gates of the transistors constitute integrating circuits. When the output voltage changes, the transistors (P1, N1) are prevented from simultaneously turning on, whereby a through current flowing into the output circuit is prevented.
摘要翻译：三态互补场效应集成电路包括连接到输入端（1）的输出前级电路（11）和第一和第二控制输入（6,5），并且包括第一开关电路 9），具有电阻（P5，N5）和第三开关装置（10）的第二开关电路（7,8）。输出电路（12），其包括p型串联连接和n型场效应晶体管（P1，N1），其中电容器（C1，C2）连接在各个栅极和地（GND）之间。当将H和L电平的电压施加到第一和第二控制输入端（6,5）时，包括在第二开关装置中的电阻（P5，N5）和连接到第二开关装置的栅极的电容器（C1，C2）晶体管构成积分电路。当输出电压变化时，防止晶体管（P1，N1）同时导通，从而防止流入输出电路的贯通电流。

7. 发明授权

US5534805A Synchronized clock generating apparatus 失效
标题翻译：同步时钟发生装置
公开(公告)号：US5534805A
公开(公告)日：1996-07-09
申请号：US449496
申请日：1995-05-24
申请人： Yukio Miyazaki , Takenori Okitaka , Makoto Hatakenaka , Junji Mano
发明人： Yukio Miyazaki , Takenori Okitaka , Makoto Hatakenaka , Junji Mano
IPC分类号： G06F1/10 , H03K5/00 , H03K5/13 , H04L7/033 , H03L7/00
CPC分类号： H04L7/0338 , G06F1/10 , H03K5/133 , H03K2005/00234
摘要： A synchronized clock generating apparatus includes a delayed clock generating circuit including a plurality of serially connected delaying elements for generating delayed clock signals delayed successively to an incoming basic clock signal. A plurality of storage elements store therein a predetermined level in response to transitions occurring in associated ones of the basic and delayed clock signals after an asynchronous trigger signal is applied thereto. A clock selection logic circuit is controlled by the output signal from the storage elements for detecting the clock signal transition occurring closest in time to the application of the asynchronous trigger signal, and for selecting a desired one of the clock signals based on the result of the detection, as a synchronized clock input signal.
摘要翻译：同步时钟产生装置包括延迟时钟产生电路，延迟时钟产生电路包括多个串行连接的延迟元件，用于产生连续延迟到输入基本时钟信号的延迟时钟信号。响应于在异步触发信号被施加到基站和延迟的时钟信号之后发生在相关联的基本和延迟时钟信号中的转换，多个存储元件存储预定电平。时钟选择逻辑电路由来自存储元件的输出信号控制，用于检测在施加异步触发信号时在时间上最近发生的时钟信号转换，并且基于时钟信号的结果来选择期望的一个时钟信号检测，作为同步时钟输入信号。

8. 发明授权

US4804867A Three-state complementary MOS integrated circuit 失效
标题翻译：三态互补MOS集成电路
公开(公告)号：US4804867A
公开(公告)日：1989-02-14
申请号：US119086
申请日：1987-11-10
申请人： Takenori Okitaka , Yukio Miyazaki
发明人： Takenori Okitaka , Yukio Miyazaki
IPC分类号： H03K19/0175 , H03K19/00 , H03K19/003 , H03K19/094 , H03K19/096 , H03K3/295 , H03K3/354 , H03K4/48 , H03K17/16
CPC分类号： H03K19/0013 , H03K19/09429
摘要： In a three-state complementary MOS integrated circuit having an output circuit comprising a P-channel MOS transistor and an N-channel MOS transistor, part of a pre-output stage circuit between the gate inputs of the P-channel MOS transistor and the N-channel MOS transistor of the output circuit comprises a parallel circuit of a first series circuit and a second series circuit, each of the first series circuits comprising a P-channel MOS transistor to which the control signal is applied and an N-channel MOS transistor to which the in inverted control signal is applied. When the control signal and the inverted control signal are at the same potential, either the P-channel MOS transistors or the N-channel MOS transistors of the parallel circuit are off. Accordingly totempole current through the pre-output stage circuit is avoided.
摘要翻译：在具有P沟道MOS晶体管和N沟道MOS晶体管的输出电路的三态互补MOS集成电路中，P沟道MOS晶体管的栅极输入端与N沟道MOS晶体管之间的预输出级电路的一部分输出电路的通道MOS晶体管包括第一串联电路和第二串联电路的并联电路，每个第一串联电路包括施加控制信号的P沟道MOS晶体管和N沟道MOS晶体管其中施加了反相控制信号。当控制信号和反相控制信号处于相同的电位时，并联电路的P沟道MOS晶体管或N沟道MOS晶体管都截止。因此避免了通过预输出级电路的电流电流。

9. 发明授权

US5424995A Static random access memory allowing reading angle rotation 失效
标题翻译：静态随机存取存储器允许读取角度旋转
公开(公告)号：US5424995A
公开(公告)日：1995-06-13
申请号：US894149
申请日：1992-06-04
申请人： Yukio Miyazaki , Takenori Okitaka
发明人： Yukio Miyazaki , Takenori Okitaka
IPC分类号： G11C11/41 , G11C8/16 , G11C11/413 , G11C8/00
CPC分类号： G11C8/16
摘要： A plurality of first word lines are connected to a first word selector, and a plurality of second word lines are connected to a second word selector. A plurality of first bit lines are connected to a first bit selector, and a plurality of second bit lines are connected to a second bit selector. Each memory cell includes two inverters and first and second access gates. Each memory cell is connected to the first word line, the second word line, the first bit line and the second bit line. In data writing, data is written to a node through the first access gate. In data reading, data at the node or node is read through either the first or the second access gate.
摘要翻译：多个第一字线连接到第一字选择器，并且多个第二字线连接到第二字选择器。多个第一位线连接到第一位选择器，并且多个第二位线连接到第二位选择器。每个存储单元包括两个反相器和第一和第二存取门。每个存储单元连接到第一字线，第二字线，第一位线和第二位线。在数据写入时，通过第一个访问门口将数据写入节点。在数据读取中，通过第一或第二访问门读取节点或节点处的数据。

10. 发明授权

US06577979B1 Semiconductor integrated circuit with IP test circuit 失效
标题翻译：具有IP测试电路的半导体集成电路
公开(公告)号：US06577979B1
公开(公告)日：2003-06-10
申请号：US09414036
申请日：1999-10-07
申请人： Takenori Okitaka
发明人： Takenori Okitaka
IPC分类号： G01R2728
CPC分类号： G01R31/319 , G01R31/31724 , G01R31/31907
摘要： A semiconductor integrated circuit with a IP test circuit having a IP test circuit, a IP6, a IP7, a COU 4, a SRAM 5. The IP test circuit has a IP test controller 21 including a register 21, a test sequencer 2, a selector 3, and a bus interface 11. Under the control of the IP test controller 1, a test program and test data in serial form are transferred from an external tester through a test data terminal 9 and then converted to the test program and the test data in parallel form. The converted test program and the test data are stored into the SRAM 5. The CPU 4 executes the test operation for the IP6 directly connected to a cpu bus 8. The test sequencer 7 executes the test operation for the IP7 that is not directly connected to the cpu bus 8. The test results are transferred to the external tester through the test data terminal.
摘要翻译：具有IP测试电路的IP半导体集成电路，IP测试电路，IP6，IP7，COU4，SRAM5。IP测试电路具有IP测试控制器21，其包括寄存器21，测试定序器2，选择器3和总线接口11.在IP测试控制器1的控制下，测试程序和串行形式的测试数据通过测试数据终端9从外部测试仪传送，然后转换为测试程序和测试并行数据。转换的测试程序和测试数据被存储到SRAM 5.CPU4执行直接连接到CPU总线8的IP6的测试操作。测试定序器7对不直接连接到 cpu总线8.测试结果通过测试数据终端传输到外部测试仪。

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