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1. 发明申请

US20100002822A1 PHASE COMPARATOR, PHASE COMPARISON DEVICE, AND CLOCK DATA RECOVERY SYSTEM 有权
标题翻译：相位比较器，相位比较器和时钟数据恢复系统
公开(公告)号：US20100002822A1
公开(公告)日：2010-01-07
申请号：US12374743
申请日：2006-11-15
申请人： Yukio Arima , Akinori Shinmyo , Toru Iwata
发明人： Yukio Arima , Akinori Shinmyo , Toru Iwata
IPC分类号： H04L7/00
CPC分类号： H03L7/089 , H03L7/0814 , H03L7/091 , H04L7/0337
摘要： A comparison period detecting unit (11) defines, as a comparison period, a period between a rising edge of a first clock signal and a rising edge of a second clock signal, and detects the presence or absence of transition of a data signal during the comparison period. A phase relationship detecting unit (12) detects a phase relationship between the data signal and a reference clock signal, and outputs a result of detection of the phase relationship when the comparison period detecting unit (11) detects transition of the data signal during the comparison period.
摘要翻译：比较周期检测单元（11）将第一时钟信号的上升沿和第二时钟信号的上升沿之间的周期定义为比较周期，并且在第一时钟信号的上升沿期间检测数据信号的转换是否存在比较期相位关系检测单元（12）检测数据信号和参考时钟信号之间的相位关系，并且当比较周期检测单元（11）在比较期间检测到数据信号的转变时，输出相位关系的检测结果期。

2. 发明授权

US08149974B2 Phase comparator, phase comparison device, and clock data recovery system 有权
标题翻译：相位比较器，相位比较器和时钟数据恢复系统
公开(公告)号：US08149974B2
公开(公告)日：2012-04-03
申请号：US12374743
申请日：2006-11-15
申请人： Yukio Arima , Akinori Shinmyo , Toru Iwata
发明人： Yukio Arima , Akinori Shinmyo , Toru Iwata
IPC分类号： H04L7/00
CPC分类号： H03L7/089 , H03L7/0814 , H03L7/091 , H04L7/0337
摘要： A comparison period detecting unit (11) defines, as a comparison period, a period between a rising edge of a first clock signal and a rising edge of a second clock signal, and detects the presence or absence of transition of a data signal during the comparison period. A phase relationship detecting unit (12) detects a phase relationship between the data signal and a reference clock signal, and outputs a result of detection of the phase relationship when the comparison period detecting unit (11) detects transition of the data signal during the comparison period.
摘要翻译：比较周期检测单元（11）将第一时钟信号的上升沿和第二时钟信号的上升沿之间的周期定义为比较周期，并且在第一时钟信号的上升沿期间检测数据信号的转换是否存在比较期相位关系检测单元（12）检测数据信号和参考时钟信号之间的相位关系，并且当比较周期检测单元（11）在比较期间检测到数据信号的转变时，输出相位关系的检测结果期。

3. 发明授权

US08063696B2 Receiving circuit and receiving system 有权
标题翻译：接收电路和接收系统
公开(公告)号：US08063696B2
公开(公告)日：2011-11-22
申请号：US12597885
申请日：2009-02-02
申请人： Akinori Shinmyo
发明人： Akinori Shinmyo
IPC分类号： G06G7/12
CPC分类号： H04L25/0264 , H03K17/005 , H04L25/0272
摘要： An output circuit (12) converts a pair of current signals supplied to a pair of common nodes (NCa and NCb) into a pair of voltage signals (VOa and VOb). In each of input buffer circuits (11, 11, . . . ), a constant current generation section (101) generates, in an output mode, a pair of constant currents in a pair of current paths going from a pair of intermediate nodes (NMa and NMb) to a reference node (VDD1), and stops the generation of the pair of constant currents in a cutoff mode. A voltage-to-current conversion section (102) generates, in the output mode, a pair of input currents corresponding to a pair of input signals (Sa and Sb) in a pair of current paths going from the pair of intermediate nodes (NMa and NMb) to a reference node (GND) to thereby generate a pair of current signals (Ia and Ib) in a pair of current paths going from the pair of intermediate nodes (NMa and NMb) to the pair of common nodes (NCa and NCb), and stops the generation of the pair of input currents in the cutoff mode.
摘要翻译：输出电路（12）将提供给一对公共节点（NCa和NCb）的一对电流信号转换为一对电压信号（VOa和VOb）。在每个输入缓冲电路（11,11等）中，恒流产生部分（101）在输出模式中产生一对电流路径中的一对恒定电流（从一对中间节点） NMa和NMb）连接到参考节点（VDD1），并且在截止模式中停止产生一对恒定电流。电压 - 电流转换部分（102）在输出模式下产生与从一对中间节点（NMa）中的一对电流路径中的一对输入信号（Sa和Sb）相对应的一对输入电流和NMb）连接到参考节点（GND），从而在从一对中间节点（NMa和NMb）到一对公共节点（NCa和Nb）的一对电流路径中产生一对电流信号（Ia和Ib） NCb），并且在截止模式下停止生成一对输入电流。

4. 发明申请

US20110210771A1 RECEIVING CIRCUIT AND RECEIVING SYSTEM 有权
标题翻译：接收电路和接收系统
公开(公告)号：US20110210771A1
公开(公告)日：2011-09-01
申请号：US12597885
申请日：2009-02-02
申请人： Akinori Shinmyo
发明人： Akinori Shinmyo
IPC分类号： H03L7/00 , H03L5/00
CPC分类号： H04L25/0264 , H03K17/005 , H04L25/0272
摘要： An output circuit (12) converts a pair of current signals supplied to a pair of common nodes (NCa and NCb) into a pair of voltage signals (VOa and VOb). In each of input buffer circuits (11, 11, . . . ), a constant current generation section (101) generates, in an output mode, a pair of constant currents in a pair of current paths going from a pair of intermediate nodes (NMa and NMb) to a reference node (VDD1), and stops the generation of the pair of constant currents in a cutoff mode. A voltage-to-current conversion section (102) generates, in the output mode, a pair of input currents corresponding to a pair of input signals (Sa and Sb) in a pair of current paths going from the pair of intermediate nodes (NMa and NMb) to a reference node (GND) to thereby generate a pair of current signals (Ia and Ib) in a pair of current paths going from the pair of intermediate nodes (NMa and NMb) to the pair of common nodes (NCa and NCb), and stops the generation of the pair of input currents in the cutoff mode.
摘要翻译：输出电路（12）将提供给一对公共节点（NCa和NCb）的一对电流信号转换为一对电压信号（VOa和VOb）。在每个输入缓冲电路（11,11等）中，恒流产生部分（101）在输出模式中产生一对电流路径中的一对恒定电流（从一对中间节点） NMa和NMb）连接到参考节点（VDD1），并且在截止模式中停止产生一对恒定电流。电压 - 电流转换部分（102）在输出模式下产生与从一对中间节点（NMa）中的一对电流路径中的一对输入信号（Sa和Sb）相对应的一对输入电流和NMb）连接到参考节点（GND），从而在从一对中间节点（NMa和NMb）到一对公共节点（NCa和Nb）的一对电流路径中产生一对电流信号（Ia和Ib） NCb），并且在截止模式下停止生成一对输入电流。

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