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1. 发明授权

US07167385B2 Method and apparatus for controlling the timing of precharge in a content addressable memory system 有权
标题翻译：用于控制内容可寻址存储器系统中的预充电时序的方法和装置
公开(公告)号：US07167385B2
公开(公告)日：2007-01-23
申请号：US11055802
申请日：2005-02-11
申请人： Yuen Hung Chan , Masood Ahmed Khan , Michael Ju Hyeok Lee , Ed Seewann
发明人： Yuen Hung Chan , Masood Ahmed Khan , Michael Ju Hyeok Lee , Ed Seewann
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A CAM system is disclosed in which compare data, for example an address translation request, is provided as input search data to a search line generator. The search line generator presents search line input data, through a buffer, to CAM and RAM array systems that include dynamically precharged and evaluated memory cells. Timing sequences in the CAM system are controlled by a series of individually triggered one shot pulse generators. The one shot pulse generators control the timing of CAM system activities, for example the precharge of CAM subsystems, so that these activities are staggered in time. This timing approach improves power consumption and evaluation time within the CAM system. By distributing precharging activities in time throughout the CAM cycle, current peaking during the CAM cycle is reduced. The CAM system latches results in an output latch that is controlled by a one shot pulse generator.
摘要翻译：公开了一种CAM系统，其中将比较数据（例如地址转换请求）作为输入搜索数据提供给搜索线发生器。搜索线生成器通过缓冲器将搜索线输入数据呈现给包括动态预充电和评估的存储器单元的CAM和RAM阵列系统。 CAM系统中的定时序列由一系列单独触发的单脉冲发生器控制。单脉冲发生器控制CAM系统活动的时间，例如CAM子系统的预充电，以便这些活动及时交错。该定时方法提高了CAM系统的功耗和评估时间。通过在整个CAM循环中及时分配预充电活动，CAM循环期间的当前峰值降低。 CAM系统锁存器产生由单触发脉冲发生器控制的输出锁存器。

2. 发明申请

US20100002525A1 Array Data Input Latch and Data Clocking Scheme 失效
标题翻译：阵列数据输入锁存器和数据时钟方案
公开(公告)号：US20100002525A1
公开(公告)日：2010-01-07
申请号：US12166421
申请日：2008-07-02
申请人： Yuen Hung Chan , Elspeth Anne Huston , Michael Ju Hyeok Lee
发明人： Yuen Hung Chan , Elspeth Anne Huston , Michael Ju Hyeok Lee
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22
摘要： A data input latch and clocking method and apparatus for high performance SRAM in which an L1 data input latch is controlled by a logical combination of the normal local clock buffer clock signal and the local array clock buffer clock signal. This logical combination of clock signals minimizes the hold time of the L1 latch provides a fast cycle time in which the SRAM macro can process successive write instructions while avoiding early mode issues.
摘要翻译：一种用于高性能SRAM的数据输入锁存和时钟方法和装置，其中L1数据输入锁存器由正常本地时钟缓冲时钟信号和本地阵列时钟缓冲时钟信号的逻辑组合控制。时钟信号的这种逻辑组合使得L1锁存器的保持时间最小化提供了快速周期时间，其中SRAM宏可以处理连续写指令，同时避免早期模式问题。

3. 发明授权

US07813189B2 Array data input latch and data clocking scheme 失效
标题翻译：阵列数据输入锁存器和数据时钟方案
公开(公告)号：US07813189B2
公开(公告)日：2010-10-12
申请号：US12166421
申请日：2008-07-02
申请人： Yuen Hung Chan , Elspeth Anne Huston , Michael Ju Hyeok Lee
发明人： Yuen Hung Chan , Elspeth Anne Huston , Michael Ju Hyeok Lee
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22
摘要： A data input latch and clocking method and apparatus for high performance SRAM in which an L1 data input latch is controlled by a logical combination of the normal local clock buffer clock signal and the local array clock buffer clock signal. This logical combination of clock signals minimizes the hold time of the L1 latch provides a fast cycle time in which the SRAM macro can process successive write instructions while avoiding early mode issues.
摘要翻译：一种用于高性能SRAM的数据输入锁存和时钟方法和装置，其中L1数据输入锁存器由正常本地时钟缓冲时钟信号和本地阵列时钟缓冲时钟信号的逻辑组合控制。时钟信号的这种逻辑组合使得L1锁存器的保持时间最小化提供了快速周期时间，其中SRAM宏可以处理连续写指令，同时避免早期模式问题。

4. 发明授权

US07936198B2 Progamable control clock circuit for arrays 有权
标题翻译：阵列控制时钟电路
公开(公告)号：US07936198B2
公开(公告)日：2011-05-03
申请号：US12345758
申请日：2008-12-30
申请人： Rolf Sautter , Michael Ju Hyeok Lee , Yuen Hung Chan , Juergen Pille
发明人： Rolf Sautter , Michael Ju Hyeok Lee , Yuen Hung Chan , Juergen Pille
IPC分类号： H03K3/00
CPC分类号： G06F1/04
摘要： A programmable clock control circuit includes a base block, a chop block, and a pulse width variation block coupled between the chop block and the base block that receives the chop block output and provides a pulse width variation output to the base block. The pulse width variation block is programmable to vary the chop block output to provide at least three different output pulse widths. The circuit also includes a clock delay block coupled an output of the base block to delay the output pulse and having a clock signal output.
摘要翻译：可编程时钟控制电路包括：接收斩波块输出的斩波块与基地块之间的基本块，斩波块和脉冲宽度变化块，并向基地块提供脉冲宽度变化输出。脉冲宽度变化块可编程以改变斩波块输出以提供至少三个不同的输出脉冲宽度。该电路还包括一个与基本块的输出相连的时钟延迟块，以延迟输出脉冲并具有时钟信号输出。

5. 发明申请

US20100164586A1 PROGAMABLE CONTROL CLOCK CIRCUIT FOR ARRAYS 有权
标题翻译：可编程控制时钟电路
公开(公告)号：US20100164586A1
公开(公告)日：2010-07-01
申请号：US12345758
申请日：2008-12-30
申请人： Rolf Sautter , Michael Ju Hyeok Lee , Yuen Hung Chan , Juergen Pille
发明人： Rolf Sautter , Michael Ju Hyeok Lee , Yuen Hung Chan , Juergen Pille
IPC分类号： H03H11/26
CPC分类号： G06F1/04
摘要： A programmable clock control circuit includes a base block, a chop block, and a pulse width variation block coupled between the chop block and the base block that receives the chop block output and provides a pulse width variation output to the base block. The pulse width variation block is programmable to vary the chop block output to provide at least three different output pulse widths. The circuit also includes a clock delay block coupled an output of the base block to delay the output pulse and having a clock signal output.
摘要翻译：可编程时钟控制电路包括：接收斩波块输出的斩波块与基地块之间的基本块，斩波块和脉冲宽度变化块，并向基地块提供脉冲宽度变化输出。脉冲宽度变化块可编程以改变斩波块输出以提供至少三个不同的输出脉冲宽度。该电路还包括一个与基本块的输出相连的时钟延迟块，以延迟输出脉冲并具有时钟信号输出。

6. 发明授权

US07099201B1 Multifunctional latch circuit for use with both SRAM array and self test device 失效
标题翻译：多功能锁存电路，用于SRAM阵列和自检装置
公开(公告)号：US07099201B1
公开(公告)日：2006-08-29
申请号：US11055043
申请日：2005-02-10
申请人： Andrew James Bianchi , Yuen Hung Chan , William Vincent Huott , Michael Ju Hyeok Lee , Edelmar Seewann , Philip George Shephard, III
发明人： Andrew James Bianchi , Yuen Hung Chan , William Vincent Huott , Michael Ju Hyeok Lee , Edelmar Seewann , Philip George Shephard, III
IPC分类号： G11C7/10
CPC分类号： G11C29/1201 , G11C11/41 , G11C11/419 , G11C29/12
摘要： An apparatus and method is provided that combines both self test and functional features in a single latch circuit, which may be used with an SRAM array and is usefully embodied as an L1-L2 latch. During partial writes from an SRAM array, data bits of unknown state are inhibited from entering the latch circuit, while data for testing is allowed to enter. In one useful embodiment of the invention the latch circuit is used with a mode control that provides mode select signals to operate the latch circuit in one of a plurality of modes, including at least full write and partial write modes. The latch circuit further includes a data hold circuit for selectively receiving and storing data coupled to the latch circuit. A first enabling circuit responsive to the mode select signals enables the hold circuit to receive all the data contained in the array during a full write mode, and further enables the hold circuit to receive only some of the data bits contained in the array during a partial write mode.
摘要翻译：提供了一种在单个锁存电路中组合自检和功能特征的装置和方法，其可以与SRAM阵列一起使用，并且被有效地实现为L1-L2锁存器。在从SRAM阵列的部分写入期间，未知状态的数据位被禁止进入锁存电路，而用于测试的数据被允许进入。在本发明的一个有用的实施例中，锁存电路与提供模式选择信号的模式控制一起使用，以便以至少全写和部分写模式的多种模式之一来操作锁存电路。锁存电路还包括数据保持电路，用于选择性地接收和存储耦合到锁存电路的数据。响应于模式选择信号的第一使能电路使得保持电路能够在完全写入模式期间接收包含在阵列中的所有数据，并且还允许保持电路仅在部分时钟期间仅接收阵列中包含的一些数据位写模式。

7. 发明授权

US6105109A System speed loading of a writable cache code array 失效
标题翻译：可写缓存代码数组的系统速度加载
公开(公告)号：US6105109A
公开(公告)日：2000-08-15
申请号：US26327
申请日：1998-02-19
申请人： Barry Watson Krumm , Charles Franklin Webb , Timothy John Slegel , Mark Steven Farrell , Yuen Hung Chan
发明人： Barry Watson Krumm , Charles Franklin Webb , Timothy John Slegel , Mark Steven Farrell , Yuen Hung Chan
IPC分类号： G06F9/38 , G06F12/08 , G06F13/00 , G06F9/28
CPC分类号： G06F9/3802 , G06F12/0802
摘要： SMP computers systems can add to the first level cache a fill mode latch and achieve straightforward, high-performance loading of a writable cache code array that is part of a hierarchical cache structure.A new code array's write control elements include a control latch called "fill mode" for the BCE controls which when fill mode is active, then a disable is also active, since reads of the code array may not give accurate data when the array is not yet filled-up/fully valid. New mode follows the sequential steps which process code by:a) purge the cache array; thenb) disable the code array; thenc) turn on fill mode with a buffer control element fill mode latch; and then processd) code increments once through a range of line addresses, where the range is at least as wide as the range(s) specified in the code array's lookup mechanism.e) turn off fill mode; thenf) purge the cache array again: and theng) enable the code array (turn off the code array disable bit).h) resume normal operation to end the sequence.
摘要翻译： SMP计算机系统可以将第一级缓存添加到填充模式锁存器中，并实现作为分层缓存结构的一部分的可写缓存代码数组的直接，高性能加载。新的代码数组的写控制元素包括称为“ 填充模式“，当填充模式处于活动状态时，禁用也是活动的，因为当数组尚未填满/完全有效时，代码数组的读取可能无法提供准确的数据。新模式遵循以下步骤处理代码的顺序步骤：a）清除缓存数组; 那么b）禁用代码数组; 然后c）用缓冲器控制元件填充模式锁存器打开填充模式; 然后处理d）通过行地址范围增加一次代码，其范围至少与代码数组查找机制中指定的范围一样宽。 e）关闭填充模式; 然后f）再次清除缓存数组：然后g）启用代码数组（关闭代码数组禁用位）。 h）恢复正常操作以结束序列。

8. 发明授权

US08325549B2 Global bit select circuit interface with simplified write bit line precharging 失效
标题翻译：全局位选择电路接口，具有简化的写位线预充电
公开(公告)号：US08325549B2
公开(公告)日：2012-12-04
申请号：US12713670
申请日：2010-02-26
申请人： Yuen Hung Chan , Antonia R. Pelella
发明人： Yuen Hung Chan , Antonia R. Pelella
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/1048 , G11C8/14 , G11C11/413
摘要： A global to local bit line interface circuit for domino SRAM devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through local write bit lines, the global write bit lines configured to write a selected SRAM cell with data presented on a pair of write data input lines; a pair of complementary global read bit lines in selective communication with the array through local read bit lines, the global read bit lines configured to read data stored in a selected cell and present the read data on a pair of read data output lines; and write control logic configured to control precharging of the global write bit lines independently with respect to the global read bit lines, and wherein a pulse width of write data on the global write bit lines is determined only by a global column select signal.
摘要翻译：用于多米诺骨架SRAM器件的全局到本地位线接口电路包括一对互补的全局写入位线，其通过本地写入位线与SRAM单元阵列选择性地通信，所述全局写入位线被配置为将所选择的SRAM单元写入数据呈现在一对写入数据输入线上; 一对互补的全局读位线，其通过本地读位线与阵列选择性地通信，全局读位线被配置为读取存储在所选单元中的数据，并将读数据呈现在一对读数据输出线上; 以及写入控制逻辑，被配置为相对于全局读位线独立地控制全局写入位线的预充电，并且其中，全局写入位线上的写入数据的脉冲宽度仅由全局列选择信号确定。

9. 发明申请

US20110211401A1 GLOBAL BIT SELECT CIRCUIT INTERFACE WITH SIMPLIFIED WRITE BIT LINE PRECHARGING 失效
标题翻译：全球位选择电路接口，具有简化的写位线预加载
公开(公告)号：US20110211401A1
公开(公告)日：2011-09-01
申请号：US12713670
申请日：2010-02-26
申请人： Yuen Hung Chan , Antonia R. Pelella
发明人： Yuen Hung Chan , Antonia R. Pelella
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C7/18 , G11C7/1048 , G11C8/14 , G11C11/413
摘要： A global to local bit line interface circuit for domino SRAM devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through local write bit lines, the global write bit lines configured to write a selected SRAM cell with data presented on a pair of write data input lines; a pair of complementary global read bit lines in selective communication with the array through local read bit lines, the global read bit lines configured to read data stored in a selected cell and present the read data on a pair of read data output lines; and write control logic configured to control precharging of the global write bit lines independently with respect to the global read bit lines, and wherein a pulse width of write data on the global write bit lines is determined only by a global column select signal.
摘要翻译：用于多米诺骨架SRAM器件的全局到本地位线接口电路包括一对互补的全局写入位线，其通过本地写入位线与SRAM单元阵列选择性地通信，所述全局写入位线被配置为将所选择的SRAM单元写入数据呈现在一对写入数据输入线上; 一对互补的全局读位线，其通过本地读位线与阵列选择性地通信，全局读位线被配置为读取存储在所选单元中的数据，并将读数据呈现在一对读数据输出线上; 以及写入控制逻辑，被配置为相对于全局读位线独立地控制全局写入位线的预充电，并且其中，全局写入位线上的写入数据的脉冲宽度仅由全局列选择信号确定。

10. 发明申请

US20080298137A1 METHOD AND STRUCTURE FOR DOMINO READ BIT LINE AND SET RESET LATCH 审中-公开
标题翻译：多米诺读取线和设置复位锁的方法和结构
公开(公告)号：US20080298137A1
公开(公告)日：2008-12-04
申请号：US12053128
申请日：2008-03-21
申请人： Yuen Hung Chan , Robert Maurice Houle , Rolf Sautter , Pascal Witte
发明人： Yuen Hung Chan , Robert Maurice Houle , Rolf Sautter , Pascal Witte
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/12 , G11C11/41 , G11C2029/1204
摘要： A domino read bit line structure (20) integral to an SRAM array (1, 2) with thirty-two word lines or less to access SRAM cells divided into two groups (3, 4, 90, 100) is described. The bit line structure (20) includes a dynamic bit decode multiplexer (11, 40) and two NAND circuits (5, 80) used to combine the two groups (3, 4, 90, 100), wherein in order to reduce power consumption the two NANDS (80) drive the dynamic bit decode multiplexer (40) directly, such that true and complement dynamic outputs (rt, rc) drive a set-reset latch (50) to convert the dynamic outputs (rt, rc) to a single static signal (doc), wherein the output of the set-reset latch (50) is already static so that the set-reset latch (50) acts as an effective array output latch (7).
摘要翻译：描述了与具有32个字线或更少的SRAM阵列（1,2）积分的多米诺读取位线结构（20），以访问分成两组（3,4,90,100）的SRAM单元。位线结构（20）包括动态位解码多路复用器（11,40）和用于组合两组（3,490,100）的两个NAND电路（5,80），其中为了降低功耗两个NANDS（80）直接驱动动态位解码多路复用器（40），使得真实和补充动态输出（rt，rc）驱动设置复位锁存器（50）以将动态输出（rt，rc）转换为单个静态信号（doc），其中所述设置复位锁存器（50）的输出已经是静态的，使得所述设置复位锁存器（50）用作有效阵列输出锁存器（7）。

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