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1. 发明授权

US07973549B2 Method and apparatus for calibrating internal pulses in an integrated circuit 有权
标题翻译：用于校准集成电路中的内部脉冲的方法和装置
公开(公告)号：US07973549B2
公开(公告)日：2011-07-05
申请号：US11761610
申请日：2007-06-12
申请人： Rajiv V. Joshi , Robert L. Franch , Robert Maurice Houle , Kevin A. Batson
发明人： Rajiv V. Joshi , Robert L. Franch , Robert Maurice Houle , Kevin A. Batson
IPC分类号： G01R31/02
CPC分类号： G01R31/31725 , G01R31/31726
摘要： A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence.
摘要翻译：用于测量内部脉冲的方法和电路包括使能电路，其被配置为从片上内置测试器接收控制信号以使得能够测量内部电路。延迟链被配置为从片上电路部件接收脉冲信号。采样锁存器各自包括耦合在延迟链的相邻延迟元件之间并与时钟信号同步的数据输入，使得通过比较输出序列中的相邻数字值来指示脉冲信号中的转变。

2. 发明授权

US07701801B2 Programmable pulsewidth and delay generating circuit for integrated circuits 失效
标题翻译：用于集成电路的可编程脉冲宽度和延迟发生电路
公开(公告)号：US07701801B2
公开(公告)日：2010-04-20
申请号：US11761655
申请日：2007-06-12
申请人： Rajiv V. Joshi , Robert Maurice Houle , Kevin A. Batson
发明人： Rajiv V. Joshi , Robert Maurice Houle , Kevin A. Batson
IPC分类号： G11C8/00
CPC分类号： G11C11/413 , G11C11/41 , G11C29/12015 , G11C29/50 , G11C29/50012 , G11C2029/1202 , G11C2029/1208 , H03K5/06 , H03K5/13 , H03K5/1565
摘要： A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.
摘要翻译：本地片上可编程脉冲宽度和延迟产生电路包括被配置为接收全局时钟信号并输出本地时钟信号的时钟产生电路。时钟产生电路包括脉冲整形部分，其根据后沿延迟和前沿延迟中的至少一个调整全局时钟信号的脉冲宽度。前沿延迟由前沿延迟电路产生，并且后沿延迟由后沿延迟电路产生，后沿延迟电路被配置为对脉冲的后沿施加延迟。后沿延迟电路包括具有可编程级的延迟元件的延迟链，每个级都使用从地址锁存器解码的控制位独立控制。

3. 发明申请

US20090309622A1 METHOD AND APPARATUS FOR CALIBRATING INTERNAL PULSES IN AN INTEGRATED CIRCUIT 有权
标题翻译：用于在集成电路中校准内部脉冲的方法和装置
公开(公告)号：US20090309622A1
公开(公告)日：2009-12-17
申请号：US12543215
申请日：2009-08-18
申请人： Rajiv V. Joshi , Robert L. Franch , Robert Maurice Houle , Kevin A. Batson
发明人： Rajiv V. Joshi , Robert L. Franch , Robert Maurice Houle , Kevin A. Batson
IPC分类号： G01R31/02
CPC分类号： G01R31/31725 , G01R31/31726
摘要： A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence.
摘要翻译：用于测量内部脉冲的方法和电路包括使能电路，其被配置为从片上内置测试器接收控制信号以使得能够测量内部电路。延迟链被配置为从片上电路部件接收脉冲信号。采样锁存器各自包括耦合在延迟链的相邻延迟元件之间并与时钟信号同步的数据输入，使得通过比较输出序列中的相邻数字值来指示脉冲信号中的转变。

4. 发明申请

US20080298137A1 METHOD AND STRUCTURE FOR DOMINO READ BIT LINE AND SET RESET LATCH 审中-公开
标题翻译：多米诺读取线和设置复位锁的方法和结构
公开(公告)号：US20080298137A1
公开(公告)日：2008-12-04
申请号：US12053128
申请日：2008-03-21
申请人： Yuen Hung Chan , Robert Maurice Houle , Rolf Sautter , Pascal Witte
发明人： Yuen Hung Chan , Robert Maurice Houle , Rolf Sautter , Pascal Witte
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/12 , G11C11/41 , G11C2029/1204
摘要： A domino read bit line structure (20) integral to an SRAM array (1, 2) with thirty-two word lines or less to access SRAM cells divided into two groups (3, 4, 90, 100) is described. The bit line structure (20) includes a dynamic bit decode multiplexer (11, 40) and two NAND circuits (5, 80) used to combine the two groups (3, 4, 90, 100), wherein in order to reduce power consumption the two NANDS (80) drive the dynamic bit decode multiplexer (40) directly, such that true and complement dynamic outputs (rt, rc) drive a set-reset latch (50) to convert the dynamic outputs (rt, rc) to a single static signal (doc), wherein the output of the set-reset latch (50) is already static so that the set-reset latch (50) acts as an effective array output latch (7).
摘要翻译：描述了与具有32个字线或更少的SRAM阵列（1,2）积分的多米诺读取位线结构（20），以访问分成两组（3,4,90,100）的SRAM单元。位线结构（20）包括动态位解码多路复用器（11,40）和用于组合两组（3,490,100）的两个NAND电路（5,80），其中为了降低功耗两个NANDS（80）直接驱动动态位解码多路复用器（40），使得真实和补充动态输出（rt，rc）驱动设置复位锁存器（50）以将动态输出（rt，rc）转换为单个静态信号（doc），其中所述设置复位锁存器（50）的输出已经是静态的，使得所述设置复位锁存器（50）用作有效阵列输出锁存器（7）。

5. 发明授权

US07830727B2 Apparatus and method for low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines 有权
标题翻译：在使用预放电位线的多端口SRAM中进行低功耗，单端检测的装置和方法
公开(公告)号：US07830727B2
公开(公告)日：2010-11-09
申请号：US12135237
申请日：2008-06-09
申请人： Igor Arsovski , Michael Thomas Fragano , Robert Maurice Houle
发明人： Igor Arsovski , Michael Thomas Fragano , Robert Maurice Houle
IPC分类号： G11C7/06
CPC分类号： G11C7/12 , G11C11/412 , G11C11/413
摘要： An apparatus and method for low power, single-ended sensing in a multi-port static random access memory (SRAM) using pre-discharged bit lines includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; releasing the bit line from being held at a zero voltage potential when the memory cell is being accessed; charging the bit line to a first voltage potential greater in value than the zero voltage potential during an access of the memory cell, wherein charging the bit line to a first voltage potential occurs for a first predetermined period of time after access to the memory cell has begun; and sensing the memory cell contents during an access of the memory cell, wherein sensing of the memory cell contents occurs for a second predetermined period of time after access to the memory cell has begun.
摘要翻译：在使用预放电位线的多端口静态随机存取存储器（SRAM）中用于低功率，单端感测的装置和方法包括：当存储器单元为存储单元时，将与存储器单元相关联的位线保持在零电压电位没有被访问当存储器单元被访问时，释放位线保持在零电压电位; 在存储单元访问期间将位线充电到比零电压电位大的第一电压电位，其中在访问存储器单元之后的第一预定时间段内将位线充电到第一电压电位，开始了以及在所述存储器单元的访问期间感测所述存储器单元的内容，其中在开始访问所述存储器单元之后的第二预定时间段内存储单元内容的感测发生。

6. 发明授权

US07859921B2 Apparatus and method for low power sensing in a multi-port SRAM using pre-discharged bit lines 有权
标题翻译：使用预放电位线的多端口SRAM中的低功率感测的装置和方法
公开(公告)号：US07859921B2
公开(公告)日：2010-12-28
申请号：US12135229
申请日：2008-06-09
申请人： Igor Arsovski , Michael Thomas Fragano , Robert Maurice Houle
发明人： Igor Arsovski , Michael Thomas Fragano , Robert Maurice Houle
IPC分类号： G11C7/12 , G11C7/06
CPC分类号： G11C8/16 , G11C11/419
摘要： A method for sensing the contents of a memory cell within a static random access memory (SRAM) includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; energizing the bit line to a first voltage potential different than the zero voltage potential during an access of the memory cell; and sensing the memory cell contents when the associated bit line has reached the first voltage potential.
摘要翻译：一种用于感测静态随机存取存储器（SRAM）内的存储单元的内容的方法包括当存储单元未被访问时，将与存储单元相关联的位线保持在零电压电位; 在存储器单元的访问期间将位线激励到不同于零电压电位的第一电压电位; 以及当相关联的位线已经达到第一电压电位时感测存储器单元的内容。

7. 发明申请

US20100309740A1 Low Power, Single-Ended Sensing in a Multi-Port SRAM Using Pre-Discharged Bit Lines 有权
标题翻译：使用预放电位线的多端口SRAM中的低功耗，单端感测
公开(公告)号：US20100309740A1
公开(公告)日：2010-12-09
申请号：US12858499
申请日：2010-08-18
申请人： Igor Arsovski , Michael Thomas Fragano , Robert Maurice Houle
发明人： Igor Arsovski , Michael Thomas Fragano , Robert Maurice Houle
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/412 , G11C11/413
摘要： An apparatus and method for low power, single-ended sensing in a multi-port static random access memory (SRAM) using pre-discharged bit lines includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; releasing the bit line from being held at a zero voltage potential when the memory cell is being accessed; charging the bit line to a first voltage potential greater in value than the zero voltage potential during an access of the memory cell, wherein charging the bit line to a first voltage potential occurs for a first predetermined period of time after access to the memory cell has begun; and sensing the memory cell contents during an access of the memory cell, wherein sensing of the memory cell contents occurs for a second predetermined period of time after access to the memory cell has begun.
摘要翻译：在使用预放电位线的多端口静态随机存取存储器（SRAM）中用于低功率，单端感测的装置和方法包括：当存储器单元为存储单元时，将与存储器单元相关联的位线保持在零电压电位没有被访问当存储器单元被访问时，释放位线保持在零电压电位; 在存储单元访问期间将位线充电到比零电压电位大的第一电压电位，其中在访问存储器单元之后的第一预定时间段内对位线进行充电到第一电压电位，开始了以及在所述存储器单元的访问期间感测所述存储器单元的内容，其中在开始访问所述存储器单元之后的第二预定时间段内存储单元内容的感测发生。

8. 发明申请

US20090303821A1 Apparatus and Method for Low Power, Single-Ended Sensing in a Multi-Port SRAM Using Pre-Discharged Bit Lines 有权
标题翻译：使用预放电位线的多端口SRAM中低功耗，单端检测的装置和方法
公开(公告)号：US20090303821A1
公开(公告)日：2009-12-10
申请号：US12135237
申请日：2008-06-09
申请人： Igor Arsovski , Michael Thomas Fragano , Robert Maurice Houle
发明人： Igor Arsovski , Michael Thomas Fragano , Robert Maurice Houle
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/12 , G11C11/412 , G11C11/413
摘要： An apparatus and method for low power, single-ended sensing in a multi-port static random access memory (SRAM) using pre-discharged bit lines includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; releasing the bit line from being held at a zero voltage potential when the memory cell is being accessed; charging the bit line to a first voltage potential greater in value than the zero voltage potential during an access of the memory cell, wherein charging the bit line to a first voltage potential occurs for a first predetermined period of time after access to the memory cell has begun; and sensing the memory cell contents during an access of the memory cell, wherein sensing of the memory cell contents occurs for a second predetermined period of time after access to the memory cell has begun.
摘要翻译：在使用预放电位线的多端口静态随机存取存储器（SRAM）中用于低功率，单端感测的装置和方法包括：当存储器单元为存储单元时，将与存储器单元相关联的位线保持在零电压电位没有被访问当存储器单元被访问时，释放位线保持在零电压电位; 在存储单元访问期间将位线充电到比零电压电位大的第一电压电位，其中在访问存储器单元之后的第一预定时间段内将位线充电到第一电压电位，开始了以及在所述存储器单元的访问期间感测所述存储器单元的内容，其中在开始访问所述存储器单元之后的第二预定时间段内存储单元内容的感测。

9. 发明申请

US20090303812A1 PROGRAMMABLE PULSEWIDTH AND DELAY GENERATING CIRCUIT FOR INTEGRATED CIRCUITS 有权
标题翻译：集成电路的可编程脉宽调制和延迟发生电路
公开(公告)号：US20090303812A1
公开(公告)日：2009-12-10
申请号：US12543256
申请日：2009-08-18
申请人： Rajiv V. Joshi , Robert Maurice Houle , Kevin A. Batson
发明人： Rajiv V. Joshi , Robert Maurice Houle , Kevin A. Batson
IPC分类号： G11C7/00 , G11C8/10 , G11C8/00
CPC分类号： G11C11/413 , G11C11/41 , G11C29/12015 , G11C29/50 , G11C29/50012 , G11C2029/1202 , G11C2029/1208 , H03K5/06 , H03K5/13 , H03K5/1565
摘要： A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.
摘要翻译：本地片上可编程脉冲宽度和延迟产生电路包括被配置为接收全局时钟信号并输出本地时钟信号的时钟产生电路。时钟产生电路包括脉冲整形部分，其根据后沿延迟和前沿延迟中的至少一个调整全局时钟信号的脉冲宽度。前沿延迟由前沿延迟电路产生，并且后沿延迟由后沿延迟电路产生，后沿延迟电路被配置为对脉冲的后沿施加延迟。后沿延迟电路包括具有可编程级的延迟元件的延迟链，每个级都使用从地址锁存器解码的控制位独立控制。

10. 发明授权

US5668983A Precise stopping of a high speed microprocessor clock 失效
标题翻译：精确停止高速微处理器时钟
公开(公告)号：US5668983A
公开(公告)日：1997-09-16
申请号：US359233
申请日：1994-12-19
申请人： Robert Maurice Houle , Kenneth Michael Zick
发明人： Robert Maurice Houle , Kenneth Michael Zick
IPC分类号： G01R31/30 , G06F1/04 , G06F11/267
CPC分类号： G06F11/2236 , G01R31/30 , G06F1/04
摘要： A method and means for selectively stopping the internal clock of a microprocessor on any of 16 phases using functional components which include: a clock multiplier circuit, that receives a clock signal input from an external oscillator or other appropriate source, and outputs the internal clock signal for the microprocessor; control logic circuitry for processing and inputting stop signals to the clock multiplier; and a clock special purpose register, which provides control signals to the control logic circuitry to determine when stopping of the internal clock signal should occur.
摘要翻译：一种用于使用功能部件选择性地停止微处理器的内部时钟的方法和装置，所述功能部件包括：时钟乘法器电路，其接收从外部振荡器或其他适当的源输入的时钟信号，并输出内部时钟信号用于微处理器; 用于处理和输入停止信号到时钟倍增器的控制逻辑电路; 以及时钟专用寄存器，其向控制逻辑电路提供控制信号，以确定何时应该停止内部时钟信号。

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