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    • 3. 发明授权
    • Magnetic random access memory with field compensating layer and multi-level cell
    • 具有场补偿层和多级单元的磁随机存取存储器
    • US08565010B2
    • 2013-10-22
    • US13099321
    • 2011-05-02
    • Yuchen ZhouYiming HuaiRajiv Yadav RanjanJing Zhang
    • Yuchen ZhouYiming HuaiRajiv Yadav RanjanJing Zhang
    • G11C11/15
    • G11C11/16G11C11/161H01L43/02
    • A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A spacer layer is formed on top of the free layer and a fixed layer is formed on top of the spacer layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field.
    • 自旋转矩磁性随机存取存储器(STTMRAM)元件包括形成在基板上的参考层,具有固定的垂直磁性分量。 接合层形成在参考层的顶部,并且在接合层的顶部上以自由层的大致中心位置处具有垂直磁性取向形成自由层。 间隔层形成在自由层的顶部,固定层形成在间隔层的顶部,固定层具有与基准层相反的固定的垂直磁性部件。 自由层的磁性取向相对于固定层的磁性取向。 固定层和参考层的垂直磁性分量基本相互抵消,自由层具有面内边缘磁化场。
    • 7. 发明授权
    • MRAM fabrication method with sidewall cleaning
    • MRAM制造方法与侧壁清洁
    • US08574928B2
    • 2013-11-05
    • US13443818
    • 2012-04-10
    • Kimihiro SatohYiming HuaiYuchen ZhouJing ZhangDong Ha JungEbrahim AbedifardRajiv Yadav RanjanParviz Keshtbod
    • Kimihiro SatohYiming HuaiYuchen ZhouJing ZhangDong Ha JungEbrahim AbedifardRajiv Yadav RanjanParviz Keshtbod
    • H01L21/00
    • H01L27/222H01L43/12
    • Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.
    • 描述了用于MRAM的制造方法,其中在互连过程开始之前清洁存储元件柱的侧壁上的任何重新沉积的金属。 在实施例中,首先制造柱,然后将介电材料沉积在侧壁上的再沉积金属上的柱上。 电介质材料基本上覆盖任何暴露的金属,因此在随后的蚀刻期间减少再沉积的来源。 然后进行蚀刻以将电介质材料从顶部电极和柱的侧壁向下移动到至少阻挡层的底部边缘。 结果是可能导致在屏障的侧壁上导致电短路的先前重新沉积的金属被去除。 本发明的各种实施方案包括增强或优化方法的方法。 如所描述的那样,在侧壁被蚀刻清洁之后,进行位线互连处理。
    • 8. 发明授权
    • Magnetoresistive logic cell and method of use
    • 磁阻逻辑单元及其使用方法
    • US08885395B2
    • 2014-11-11
    • US13402123
    • 2012-02-22
    • Yuchen ZhouZihui WangYiming HuaiRajiv Yadav RanjanRoger K. Malmhall
    • Yuchen ZhouZihui WangYiming HuaiRajiv Yadav RanjanRoger K. Malmhall
    • G11C11/00
    • G11C11/00G11C11/161G11C11/1673H01L27/222H01L43/08
    • A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable reference layer (SRL) in MTJ-1 dominate the overall resistance of the MRLC without regard to the fixed magnetization orientation of the nonswitchable reference layer in MTJ-2. The high resistance state of the MRLC occurs when the switchable reference and common free layers have opposite magnetization orientations. The low resistance state occurs when the orientations are the same. This behavior allows the MRLC to be used as a logical comparator. The CFL is switched by STT effect by application of selected relatively short voltage pulses that do not switch the SRL. The SRL is switched with reference to the CFL by a voltage effect generated by a selected longer voltage pulse that does not switch the CFL.
    • 描述了包含共享共同自由层(CFL)的两个串联MTJ的磁阻逻辑单元(MRLC)。 MTJ-1中CFL和可切换参考层(SRL)的相对磁化取向主导了MRLC的总体电阻,而不考虑MTJ-2中不可切换参考层的固定磁化方向。 当可切换参考和公共自由层具有相反的磁化方向时,MRLC的高电阻状态发生。 当取向相同时,发生低电阻状态。 此行为允许将MRLC用作逻辑比较器。 通过施加不切换SRL的选定的相对较短的电压脉冲,通过STT效应来切换CFL。 通过由不会切换CFL的选定的较长电压脉冲产生的电压效应,SRL将根据CFL进行切换。