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1. 发明授权

US08574928B2 MRAM fabrication method with sidewall cleaning 有权
标题翻译： MRAM制造方法与侧壁清洁
公开(公告)号：US08574928B2
公开(公告)日：2013-11-05
申请号：US13443818
申请日：2012-04-10
申请人： Kimihiro Satoh , Yiming Huai , Yuchen Zhou , Jing Zhang , Dong Ha Jung , Ebrahim Abedifard , Rajiv Yadav Ranjan , Parviz Keshtbod
发明人： Kimihiro Satoh , Yiming Huai , Yuchen Zhou , Jing Zhang , Dong Ha Jung , Ebrahim Abedifard , Rajiv Yadav Ranjan , Parviz Keshtbod
IPC分类号： H01L21/00
CPC分类号： H01L27/222 , H01L43/12
摘要： Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.
摘要翻译：描述了用于MRAM的制造方法，其中在互连过程开始之前清洁存储元件柱的侧壁上的任何重新沉积的金属。在实施例中，首先制造柱，然后将介电材料沉积在侧壁上的再沉积金属上的柱上。电介质材料基本上覆盖任何暴露的金属，因此在随后的蚀刻期间减少再沉积的来源。然后进行蚀刻以将电介质材料从顶部电极和柱的侧壁向下移动到至少阻挡层的底部边缘。结果是可能导致在屏障的侧壁上导致电短路的先前重新沉积的金属被去除。本发明的各种实施方案包括增强或优化方法的方法。如所描述的那样，在侧壁被蚀刻清洁之后，进行位线互连处理。

2. 发明申请

US20130267042A1 MRAM Fabrication Method with Sidewall Cleaning 有权
标题翻译： MRAM制造方法与侧壁清洁
公开(公告)号：US20130267042A1
公开(公告)日：2013-10-10
申请号：US13443818
申请日：2012-04-10
申请人： Kimihiro Satoh , Yiming Huai , Yuchen Zhou , Jing Zhang , Dong Ha Jung , Ebrahim Abedifard , Rajiv Yadav Ranjan , Parviz Keshtbod
发明人： Kimihiro Satoh , Yiming Huai , Yuchen Zhou , Jing Zhang , Dong Ha Jung , Ebrahim Abedifard , Rajiv Yadav Ranjan , Parviz Keshtbod
IPC分类号： H01L21/02
CPC分类号： H01L27/222 , H01L43/12
摘要： Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.
摘要翻译：描述了用于MRAM的制造方法，其中在互连过程开始之前清洁存储元件柱的侧壁上的任何重新沉积的金属。在实施例中，首先制造柱，然后将介电材料沉积在侧壁上的再沉积金属上的柱上。电介质材料基本上覆盖任何暴露的金属，因此在随后的蚀刻期间减少再沉积的来源。然后进行蚀刻以将电介质材料从顶部电极和柱的侧壁向下移动到至少阻挡层的底部边缘。结果是可能导致在屏障的侧壁上导致电短路的先前重新沉积的金属被去除。本发明的各种实施方案包括增强或优化方法的方法。如所描述的那样，在侧壁被蚀刻清洁之后，进行位线互连处理。

3. 发明授权

US08883520B2 Redeposition control in MRAM fabrication process 有权
标题翻译： MRAM制造工艺中的再沉积控制
公开(公告)号：US08883520B2
公开(公告)日：2014-11-11
申请号：US13530381
申请日：2012-06-22
申请人： Kimihiro Satoh , Dong Ha Jung , Ebrahim Abedifard , Parviz Keshtbod , Yiming Huai , Jing Zhang
发明人： Kimihiro Satoh , Dong Ha Jung , Ebrahim Abedifard , Parviz Keshtbod , Yiming Huai , Jing Zhang
IPC分类号： H01L21/00
CPC分类号： H01L43/02 , H01L27/222 , H01L43/12
摘要： Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.
摘要翻译：描述了方法和结构以在柱蚀刻期间减少存储器单元（例如MTJ电池）中的金属沉积材料。一个实施例在位于晶片上暴露的金属表面的电介质层中的着陆焊盘的顶部上形成金属螺柱。另一个实施例分别对MTJ和底部电极进行图案化。底部电极掩模然后覆盖底部电极下面的金属。另一实施例将柱蚀刻工艺分为两个阶段。第一阶段蚀刻到较低的磁性层，然后阻挡层的侧壁被电介质材料覆盖，然后将其垂直蚀刻。蚀刻的第二阶段然后对剩余的层进行图案化。另一个实施例使用顶部电极上方的硬掩模来蚀刻MTJ柱直到靠近底部电极的端点，沉积电介质，然后垂直蚀刻剩余的底部电极。

4. 发明申请

US20130341801A1 Redeposition Control in MRAM Fabrication Process 有权
公开(公告)号：US20130341801A1
公开(公告)日：2013-12-26
申请号：US13530381
申请日：2012-06-22
申请人： Kimihiro Satoh , Dong Ha Jung , Ebrahim Abedifard , Parviz Keshtbod , Yiming Huai , Jing Zhang
发明人： Kimihiro Satoh , Dong Ha Jung , Ebrahim Abedifard , Parviz Keshtbod , Yiming Huai , Jing Zhang
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L43/02 , H01L27/222 , H01L43/12
摘要： Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.

5. 发明授权

US08536063B2 MRAM etching processes 有权
公开(公告)号：US08536063B2
公开(公告)日：2013-09-17
申请号：US13199490
申请日：2011-08-30
申请人： Kimihiro Satoh , Yiming Huai , Jing Zhang , Rajiv Yadav Ranjan , Parviz Keshtbod , Roger K. Malmhall
发明人： Kimihiro Satoh , Yiming Huai , Jing Zhang , Rajiv Yadav Ranjan , Parviz Keshtbod , Roger K. Malmhall
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L43/12 , H01L29/00
摘要： Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes.

6. 发明申请

US20130052752A1 Mram etching processes 有权
标题翻译：摩擦蚀刻工艺
公开(公告)号：US20130052752A1
公开(公告)日：2013-02-28
申请号：US13199490
申请日：2011-08-30
申请人： Kimihiro Satoh , Yiming Huai , Jing Zhang , Rajiv Yadav Ranjan , Parviz Keshtbod , Roger K. Malmhall
发明人： Kimihiro Satoh , Yiming Huai , Jing Zhang , Rajiv Yadav Ranjan , Parviz Keshtbod , Roger K. Malmhall
IPC分类号： H01L21/8246
CPC分类号： H01L43/12 , H01L29/00
摘要： Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes.
摘要翻译：本发明的各种实施例涉及用于制造MRAM装置中的MTJ电池的蚀刻工艺。各种实施例可以彼此组合使用。第一实施例在硬掩模和顶电极之间添加硬掩模缓冲层。第二实施例使用多层蚀刻硬掩模。第三实施例使用包括第二层如Ta之下的第一Cu层的多层顶电极结构。第四实施例是用于底部电极去除再沉积材料同时保持更垂直侧壁蚀刻轮廓的两相蚀刻工艺。在第一阶段中，使用碳质反应离子蚀刻去除底部电极层直到端点。在第二阶段中，使用惰性气体和/或氧等离子体去除在先前蚀刻工艺期间沉积的聚合物。

7. 发明申请

US20130244344A1 METHOD FOR MANUFACTURING HIGH DENSITY NON-VOLATILE MAGNETIC MEMORY 有权
标题翻译：制造高密度非挥发性磁记忆的方法
公开(公告)号：US20130244344A1
公开(公告)日：2013-09-19
申请号：US13610587
申请日：2012-09-11
申请人： Roger Klas Malmhall , Kimihiro Satoh , Jing Zhang , Parviz Keshtbod , Rajiv Yadav Ranjan
发明人： Roger Klas Malmhall , Kimihiro Satoh , Jing Zhang , Parviz Keshtbod , Rajiv Yadav Ranjan
IPC分类号： H01L43/12
CPC分类号： H01L43/12 , B82Y10/00 , B82Y25/00 , G11C11/161 , H01L27/228
摘要： Methods of fabricating MTJ arrays using two orthogonal line patterning steps are described. Embodiments are described that use a self-aligned double patterning method for one or both orthogonal line patterning steps to achieve dense arrays of MTJs with feature dimensions one half of the minimum photo lithography feature size (F). In one set of embodiments, the materials and thicknesses of the stack of layers that provide the masking function are selected so that after the initial set of mask pads have been patterned, a sequence of etching steps progressively transfers the mask pad shape through the multiple mask layer and down through all of the MTJ cell layers to the form the complete MTJ pillars. In another set of embodiments, the MTJ/BE stack is patterned into parallel lines before the top electrode layer is deposited.
摘要翻译：描述了使用两个正交线图案化步骤制造MTJ阵列的方法。描述了使用用于一个或两个正交线图案化步骤的自对准双图案化方法来实现特征尺寸为最小光刻特征尺寸（F）的一半的MTJ的致密阵列的实施例。在一组实施例中，选择提供掩模功能的层叠层的材料和厚度，使得在初始掩模焊盘组被图案化之后，一系列蚀刻步骤逐渐地将掩模焊盘形状传递通过多个掩模通过所有的MTJ单元层的层和下层形成完整的MTJ柱。在另一组实施例中，在沉积顶部电极层之前，将MTJ / BE叠层图案化成平行线。

8. 发明授权

US08802451B2 Method for manufacturing high density non-volatile magnetic memory 有权
标题翻译：高密度非挥发性磁记忆体的制造方法
公开(公告)号：US08802451B2
公开(公告)日：2014-08-12
申请号：US13610587
申请日：2012-09-11
申请人： Roger Klas Malmhall , Kimihiro Satoh , Jing Zhang , Parviz Keshtbod , Rajiv Yadav Ranjan
发明人： Roger Klas Malmhall , Kimihiro Satoh , Jing Zhang , Parviz Keshtbod , Rajiv Yadav Ranjan
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , B82Y10/00 , B82Y25/00 , G11C11/161 , H01L27/228
摘要： Methods of fabricating MTJ arrays using two orthogonal line patterning steps are described. Embodiments are described that use a self-aligned double patterning method for one or both orthogonal line patterning steps to achieve dense arrays of MTJs with feature dimensions one half of the minimum photo lithography feature size (F). In one set of embodiments, the materials and thicknesses of the stack of layers that provide the masking function are selected so that after the initial set of mask pads have been patterned, a sequence of etching steps progressively transfers the mask pad shape through the multiple mask layer and down through all of the MTJ cell layers to the form the complete MTJ pillars. In another set of embodiments, the MTJ/BE stack is patterned into parallel lines before the top electrode layer is deposited.
摘要翻译：描述使用两个正交线图案化步骤制造MTJ阵列的方法。描述了使用用于一个或两个正交线图案化步骤的自对准双图案化方法来实现特征尺寸为最小光刻特征尺寸（F）的一半的MTJ的致密阵列的实施例。在一组实施例中，选择提供掩模功能的层叠层的材料和厚度，使得在初始掩模焊盘组被图案化之后，一系列蚀刻步骤逐渐地将掩模焊盘形状传递通过多个掩模通过所有的MTJ单元层的层和下层形成完整的MTJ柱。在另一组实施例中，在沉积顶部电极层之前，将MTJ / BE叠层图案化成平行线。

9. 发明授权

US08687418B1 Flash memory with nano-pillar charge trap 有权
标题翻译：闪存与纳米柱电荷陷阱
公开(公告)号：US08687418B1
公开(公告)日：2014-04-01
申请号：US12623369
申请日：2009-11-20
申请人： Rajiv Yadav Ranjan , Ebrahim Abedifard , Petro Estakhri , Parviz Keshtbod
发明人： Rajiv Yadav Ranjan , Ebrahim Abedifard , Petro Estakhri , Parviz Keshtbod
IPC分类号： G11C11/34
CPC分类号： H01F41/303 , B82Y10/00 , B82Y25/00 , B82Y40/00 , G11C11/161 , H01F10/3236 , H01F10/3254 , H01F10/3272 , H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L29/42332 , H01L29/7881
摘要： An embodiment of the present invention includes a non-volatile storage unit comprising a first and second N-diffusion well separated by a distance of P-substrate. A first isolation layer is formed upon the first and second N-diffusion wells and the P-substrate. A nano-pillar charge trap layer is formed upon the first isolation layer and includes conductive nano-pillars interspersed between non-conducting regions. The storage unit further includes a second isolation layer formed upon the nano-pillar charge trap layer; and at least one word line formed upon the second isolation layer and above a region of nano-pillar charge trap layer. The nano-pillar charge trap layer is operative to trap charge upon application of a threshold voltage. Subsequently, the charge trap layer may be read to determine any charge stored in the non-volatile storage unit, where presence or absence of stored charge in the charge trap layer corresponds to a bit value.
摘要翻译：本发明的实施例包括非易失性存储单元，其包括以P基底间隔开的第一和第二N-扩散阱。在第一和第二N-扩散阱和P-基底上形成第一隔离层。纳米柱电荷陷阱层形成在第一隔离层上，并且包括散布在非导电区域之间的导电纳米柱。存储单元还包括形成在纳米柱电荷陷阱层上的第二隔离层; 以及形成在第二隔离层上方和纳米柱电荷陷阱层的区域上方的至少一个字线。纳米柱电荷陷阱层可用于在施加阈值电压时捕获电荷。随后，可以读取电荷陷阱层以确定存储在非易失性存储单元中的任何电荷，其中电荷陷阱层中存在或不存在电荷对应于位值。

10. 发明授权

US08488376B2 Non-volatile magnetic memory element with graded layer 有权
标题翻译：带分级层的非易失性磁记忆元件
公开(公告)号：US08488376B2
公开(公告)日：2013-07-16
申请号：US13476879
申请日：2012-05-21
申请人： Rajiv Yadav Ranjan , Parviz Keshtbod , Roger Klas Malmhall
发明人： Rajiv Yadav Ranjan , Parviz Keshtbod , Roger Klas Malmhall
IPC分类号： G11C11/14
CPC分类号： B82Y25/00 , B82Y40/00 , G11C11/161 , H01F10/3236 , H01F10/3254 , H01F10/3272 , H01F41/303 , H01L27/228 , H01L43/08
摘要： A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.
摘要翻译：非易失性磁存储元件包括多个层，其中之一是分级的自由层。分级自由层可以包括各种元素，其中每个元素具有不同的各向异性，或者其可以包括非磁性化合物和磁性区域，其中非磁性化合物形成梯度含量形成独特的形状，例如锥形，菱形或其它形状，并且其厚度是基于磁性化合物的反应性。

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