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1. 发明授权

US07492815B2 Reduced parallel and pipelined high-order MIMO LMMSE receiver architecture 有权
标题翻译：降低并行和流水线高阶MIMO LMMSE接收机架构
公开(公告)号：US07492815B2
公开(公告)日：2009-02-17
申请号：US10997397
申请日：2004-11-24
申请人： Yuanbin Guo , Jianzhong Zhang , Dennis McCain , Joseph R. Cavallaro
发明人： Yuanbin Guo , Jianzhong Zhang , Dennis McCain , Joseph R. Cavallaro
IPC分类号： H04B1/707 , H03H7/30
CPC分类号： H04L25/03038 , H04B1/71055 , H04L25/0204 , H04L25/021 , H04L25/0242 , H04L25/0328 , H04L2025/03375 , H04L2025/03426 , H04L2025/03477 , H04L2025/03605
摘要： Disclosed is a LMMSE receiver that restores orthogonality of spreading codes in the downlink channel for a spread spectrum signal received over N receive antennas. The FFT-based chip equalizer tap solver reduces the direct matrix inverse of the prior art to the inverse of some submatrices of size N×N with the dimension of the receive antennas, and most efficiently reduces matrix inverses to no larger than 2×2. Complexity is further reduced over a conventional Fast Fourier Transform approach by Hermitian optimization to the inverse of submatrices and tree pruning. For a receiver with N=4 or N=2 with double oversampling, the resulting 4×4 matrices are partitioned into 2×2 block sub-matrices, inverted, and rebuilt into a 4×4 matrix. Common computations are found and repeated computations are eliminated to improve efficiency. Generic design architecture is derived from the special design blocks to eliminate redundancies in complex operations. Optimally, the architecture is parallel and pipelined.
摘要翻译：公开了一种用于在N个接收天线上接收的扩频信号的下行链路信道中恢复扩频码的正交性的LMMSE接收机。基于FFT的码片均衡器抽头解算器将现有技术的直接矩阵逆减少为具有接收天线的尺寸的尺寸为N×N的一些子矩阵的倒数，并且最有效地将矩阵反转减小到不大于2×2。通过Hermitian优化，传统的快速傅立叶变换方法，复杂度进一步降低到子矩阵和树剪枝的倒数。对于具有N = 4或N = 2的具有双重过采样的接收机，所得到的4×4矩阵被划分为2x2块子矩阵，被反转并重建为4×4矩阵。发现常规计算，消除重复计算以提高效率。通用设计架构源于特殊的设计模块，以消除复杂操作中的冗余。最佳的架构是并行和流水线的。

2. 发明授权

US07706430B2 System, apparatus, and method for adaptive weighted interference cancellation using parallel residue compensation 有权
标题翻译：使用并行残差补偿的自适应加权干扰消除的系统，装置和方法
公开(公告)号：US07706430B2
公开(公告)日：2010-04-27
申请号：US11067498
申请日：2005-02-25
申请人： Yuanbin Guo , Dennis McCain , Joseph R. Cavallaro
发明人： Yuanbin Guo , Dennis McCain , Joseph R. Cavallaro
IPC分类号： H04L27/06
CPC分类号： H04B1/71075 , H04B2001/71077 , H04B2201/70707
摘要： A system, apparatus and method for a multi-stage Parallel Residue Compensation (PRC) receiver for enhanced suppression of the Multiple Access Interference (MAI) in Code Division Multiple Access (CDMA) systems. The accuracy of the interference estimation is improved with a set of weights computed from an adaptive Normalized Least Mean Square (NLMS) algorithm. In order to reduce complexity, the commonality of the multi-code processing is extracted and used to derive a structure of PRC to avoid direct interference cancellation. The derived PRC structure reduces the interference cancellation architecture from a complexity that is proportional to the square of the number of users to a complexity that is linear with respect to the number of users. The complexity is further reduced by replacing dedicated multiplier circuits with simple combinational logic.
摘要翻译：一种用于增强抑制码分多址（CDMA）系统中的多址干扰（MAI）的多级并行残差补偿（PRC）接收机的系统，装置和方法。通过从自适应归一化最小二乘法（NLMS）算法计算的一组权重，改善了干扰估计的准确性。为了降低复杂度，提取多码处理的通用性，并用于导出PRC的结构，以避免直接干扰消除。导出的PRC结构从与用户数量的平方成正比于与用户数量相关的复杂度的复杂度降低了干扰消除架构。通过用简单的组合逻辑替换专用乘法电路，进一步降低了复杂度。

3. 发明授权

US07483480B2 FFT accelerated iterative MIMO equalizer receiver architecture 失效
标题翻译： FFT加速迭代MIMO均衡器接收机架构
公开(公告)号：US07483480B2
公开(公告)日：2009-01-27
申请号：US10997442
申请日：2004-11-24
申请人： Yuanbin Guo , Dennis McCain , Joseph R Cavallaro
发明人： Yuanbin Guo , Dennis McCain , Joseph R Cavallaro
IPC分类号： H03K5/159 , H04B1/10
CPC分类号： H04L25/03044 , H04L2025/03426 , H04L2025/03643
摘要： A receiver, such as a CDMA MIMO receiver, includes a LMMSE-based chip-level equalizer constructed so as to implement a FFT accelerated iterative algorithm having a complexity of order O(N log2(N)), where N is the dimension of a covariance matrix. The equalizer uses one of an overlap-save or an over-lap add FFT architecture.
摘要翻译：诸如CDMA MIMO接收机的接收机包括基于LMMSE的码片级均衡器，其被构造为实现具有阶数O（N log2（N））的复杂度的FFT加速迭代算法，其中N是协方差矩阵。均衡器使用重叠保存或重叠加法FFT架构之一。

4. 发明授权

US08767849B2 Method and device for inter-chip and inter-antenna interference cancellation 有权
标题翻译：用于芯片间和天线间干扰消除的方法和装置
公开(公告)号：US08767849B2
公开(公告)日：2014-07-01
申请号：US13405134
申请日：2012-02-24
申请人： Bei Yin , Kiarash Amiri , Joseph R. Cavallaro , Yuanbin Guo
发明人： Bei Yin , Kiarash Amiri , Joseph R. Cavallaro , Yuanbin Guo
IPC分类号： H04K1/10 , H04L27/28 , H04L25/03 , H04J11/00 , H04B1/7107
CPC分类号： H04J11/004 , H04B1/71072 , H04L25/03159
摘要： A wireless receiver is constructed to equalize a time-domain received signal, detect a plurality of symbols of the equalized time-domain received signal, and perform interference cancellation on the time-domain received signal. The interference cancellation can be performed using a partial result produced by an IDFT, and may use only neighboring symbols in a detected plurality of symbols. The resulting wireless receiver can be constructed to operate efficiently under a plurality of wireless standards.
摘要翻译：构造无线接收机以均衡时域接收信号，检测均衡的时域接收信号的多个符号，并对时域接收信号执行干扰消除。可以使用由IDFT产生的部分结果来执行干扰消除，并且可以仅使用检测到的多个符号中的相邻符号。所得到的无线接收机可被构造成在多种无线标准下有效地工作。

5. 发明授权

US08621160B2 System and method for contention-free memory access 有权
标题翻译：无竞争内存访问的系统和方法
公开(公告)号：US08621160B2
公开(公告)日：2013-12-31
申请号：US13329065
申请日：2011-12-16
申请人： Guohui Wang , Yang Sun , Joseph R. Cavallaro , Yuanbin Guo
发明人： Guohui Wang , Yang Sun , Joseph R. Cavallaro , Yuanbin Guo
IPC分类号： G06F12/06 , G06F13/376
CPC分类号： H03M13/2957 , H03M13/395 , H03M13/3972 , H03M13/6561 , H03M13/6566
摘要： A memory control unit of a turbo code decoder includes a buffer having a plurality of storage slots, a buffer control operatively coupled to the buffer, a router operatively coupled to the buffer control and to a plurality of data sources, and a conflict detection unit operatively coupled to the router, to the buffer control, and to the plurality of data sources. The buffer temporarily stores information intended for storage in a memory bank. The buffer control determines a number of available storage slots in the buffer. The router routes data from the data sources to the buffer control. The conflict detection unit initiates a temporary halt of some of the data sources when the number of available storage slots is insufficient to store all of the data from data sources attempting to access the memory bank.
摘要翻译： turbo码解码器的存储器控制单元包括具有多个存储槽的缓冲器，可操作地耦合到缓冲器的缓冲器控制器，可操作地耦合到缓冲器控制和多个数据源的路由器，以及可操作地与冲突检测单元耦合到路由器，到缓冲器控制和多个数据源。缓冲器临时存储用于存储在存储体中的信息。缓冲器控制确定缓冲器中可用的存储槽数。路由器将数据源从数据源路由到缓冲区控制。当可用存储时隙的数量不足以存储尝试访问存储体的数据源的所有数据时，冲突检测单元发起暂时停止某些数据源。

6. 发明申请

US20120219051A1 Method and Device for Inter-Chip and Inter-Antenna Interference Cancellation 有权
标题翻译：用于片间和天线间干扰消除的方法和装置
公开(公告)号：US20120219051A1
公开(公告)日：2012-08-30
申请号：US13405134
申请日：2012-02-24
申请人： Bei Yin , Kiarash Amiri , Joseph R. Cavallaro , Yuanbin Guo
发明人： Bei Yin , Kiarash Amiri , Joseph R. Cavallaro , Yuanbin Guo
IPC分类号： H03H7/30
CPC分类号： H04J11/004 , H04B1/71072 , H04L25/03159
摘要： A wireless receiver is constructed to equalize a time-domain received signal, detect a plurality of symbols of the equalized time-domain received signal, and perform interference cancellation on the time-domain received signal. The interference cancellation can be performed using a partial result produced by an IDFT, and may use only neighboring symbols in a detected plurality of symbols. The resulting wireless receiver can be constructed to operate efficiently under a plurality of wireless standards.
摘要翻译：构造无线接收机以均衡时域接收信号，检测均衡的时域接收信号的多个符号，并对时域接收信号执行干扰消除。可以使用IDFT产生的部分结果来执行干扰消除，并且可以仅使用检测到的多个符号中的相邻符号。所得到的无线接收机可被构造成在多种无线标准下有效地工作。

7. 发明申请

US20120166742A1 System and Method for Contention-Free Memory Access 有权
标题翻译：无内存访问的系统和方法
公开(公告)号：US20120166742A1
公开(公告)日：2012-06-28
申请号：US13329065
申请日：2011-12-16
申请人： Guohui Wang , Yang Sun , Joseph R. Cavallaro , Yuanbin Guo
发明人： Guohui Wang , Yang Sun , Joseph R. Cavallaro , Yuanbin Guo
IPC分类号： G06F12/00
CPC分类号： H03M13/2957 , H03M13/395 , H03M13/3972 , H03M13/6561 , H03M13/6566
摘要： A memory control unit of a turbo code decoder includes a buffer having a plurality of storage slots, a buffer control operatively coupled to the buffer, a router operatively coupled to the buffer control and to a plurality of data sources, and a conflict detection unit operatively coupled to the router, to the buffer control, and to the plurality of data sources. The buffer temporarily stores information intended for storage in a memory bank. The buffer control determines a number of available storage slots in the buffer. The router routes data from the data sources to the buffer control. The conflict detection unit initiates a temporary halt of some of the data sources when the number of available storage slots is insufficient to store all of the data from data sources attempting to access the memory bank.
摘要翻译： turbo码解码器的存储器控制单元包括具有多个存储槽的缓冲器，可操作地耦合到缓冲器的缓冲器控制器，可操作地耦合到缓冲器控制和多个数据源的路由器，以及可操作地与冲突检测单元耦合到路由器，到缓冲器控制和多个数据源。缓冲器临时存储用于存储在存储体中的信息。缓冲器控制确定缓冲器中可用的存储槽数。路由器将数据源从数据源路由到缓冲区控制。当可用存储时隙的数量不足以存储尝试访问存储体的数据源的所有数据时，冲突检测单元发起暂时停止某些数据源。

8. 发明申请

US20060146759A1 MIMO Kalman equalizer for CDMA wireless communication 审中-公开
标题翻译：用于CDMA无线通信的MIMO卡尔曼均衡器
公开(公告)号：US20060146759A1
公开(公告)日：2006-07-06
申请号：US11029900
申请日：2005-01-04
申请人： Yuanbin Guo , Jianzhong Zhang , Dennis McCain , Joseph Cavallaro
发明人： Yuanbin Guo , Jianzhong Zhang , Dennis McCain , Joseph Cavallaro
IPC分类号： H04B7/216
CPC分类号： H04L25/03057 , H04B1/707 , H04L2025/03426 , H04L2025/03522 , H04L2025/0363
摘要： An apparatus and corresponding method for receiving a MIMO cellular communication signal, the apparatus including: a Kalman filter type of equalizer, responsive to a received signal, for providing a corresponding processed signal indicating information conveyed by the received signal, responsive to a set of values indicating predicted state error correlation at a first instant of time given all noise estimates up through the first instant, for providing ta set of values indicating a product of measurement values and predicted state error correlation at a later instant of time given all process noise estimates up through the later instant. The filter is implemented so as to make use of the displacement structure of the state transition matrix of the Kalman filter allowing shifting operations in place of vector and matrix multiplications. The filter typically includes a transition and common data path that provides to both a Kalman gain processor and a Riccati processor the set of values indicating a product of measurement values and predicted state error correlation at a later instant of time given all process noise estimates up through the later instant.
摘要翻译：一种用于接收MIMO蜂窝通信信号的装置和相应方法，所述装置包括：响应于接收信号的卡尔曼滤波器类型的均衡器，用于响应于一组值提供指示由接收信号传送的信息的相应处理信号指示在第一时刻给出所有噪声估计值的第一时刻的预测状态误差相关性，以便在给定所有过程噪声估计上升的情况下提供指示测量值的乘积的值和在稍后时刻的预测状态误差相关性的值通过后来的时刻。滤波器被实现为利用卡尔曼滤波器的状态转移矩阵的位移结构，允许移位操作代替矢量和矩阵乘法。该滤波器通常包括一个转换和公共数据路径，向卡尔曼增益处理器和Riccati处理器提供一组值，该值指示在所有过程噪声估计值通过的时间点的测量值和预测状态误差相关的乘积后来的时刻。

9. 发明申请

US20060109897A1 FFT accelerated iterative MIMO equalizer receiver architecture 失效
标题翻译： FFT加速迭代MIMO均衡器接收机架构
公开(公告)号：US20060109897A1
公开(公告)日：2006-05-25
申请号：US10997442
申请日：2004-11-24
申请人： Yuanbin Guo , Dennis McCain , Joseph Cavallaro
发明人： Yuanbin Guo , Dennis McCain , Joseph Cavallaro
IPC分类号： H03K5/159 , H04B1/10
CPC分类号： H04L25/03044 , H04L2025/03426 , H04L2025/03643
摘要： A receiver, such as a CDMA MIMO receiver, includes a LMMSE-based chip-level equalizer constructed so as to implement a FFT accelerated iterative algorithm having a complexity of order O(Nlog2(N)), where N is the dimension of a covariance matrix. The equalizer uses one of an overlap-save or an over-lap add FFT architecture.
摘要翻译：诸如CDMA MIMO接收机的接收机包括基于LMMSE的码片级均衡器，其被构造为实现具有阶数O（Nlog 2（N））的复杂度的FFT加速迭代算法，其中N是协方差矩阵的维数。均衡器使用重叠保存或重叠加法FFT架构之一。

10. 发明申请

US20060109891A1 Reduced parallel and pipelined high-order MIMO LMMSE receiver architecture 有权
公开(公告)号：US20060109891A1
公开(公告)日：2006-05-25
申请号：US10997397
申请日：2004-11-24
申请人： Yuanbin Guo , Jianzhong Zhang , Dennis McCain , Joseph Cavallaro
发明人： Yuanbin Guo , Jianzhong Zhang , Dennis McCain , Joseph Cavallaro
IPC分类号： H04B1/707 , H03H7/30 , H04K1/10
CPC分类号： H04L25/03038 , H04B1/71055 , H04L25/0204 , H04L25/021 , H04L25/0242 , H04L25/0328 , H04L2025/03375 , H04L2025/03426 , H04L2025/03477 , H04L2025/03605
摘要： Disclosed is a LMMSE receiver that restores orthogonality of spreading codes in the downlink channel for a spread spectrum signal received over N receive antennas. The FFT-based chip equalizer tap solver reduces the direct matrix inverse of the prior art to the inverse of some submatrices of size N×N with the dimension of the receive antennas, and most efficiently reduces matrix inverses to no larger than 2×2. Complexity is further reduced over a conventional Fast Fourier Transform approach by Hermitian optimization to the inverse of submatrices and tree pruning. For a receiver with N=4 or N=2 with double oversampling, the resulting 4×4 matrices are partitioned into 2×2 block sub-matrices, inverted, and rebuilt into a 4×4 matrix. Common computations are found and repeated computations are eliminated to improve efficiency. Generic design architecture is derived from the special design blocks to eliminate redundancies in complex operations. Optimally, the architecture is parallel and pipelined.

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