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1. 发明授权

US07492815B2 Reduced parallel and pipelined high-order MIMO LMMSE receiver architecture 有权
标题翻译：降低并行和流水线高阶MIMO LMMSE接收机架构
公开(公告)号：US07492815B2
公开(公告)日：2009-02-17
申请号：US10997397
申请日：2004-11-24
申请人： Yuanbin Guo , Jianzhong Zhang , Dennis McCain , Joseph R. Cavallaro
发明人： Yuanbin Guo , Jianzhong Zhang , Dennis McCain , Joseph R. Cavallaro
IPC分类号： H04B1/707 , H03H7/30
CPC分类号： H04L25/03038 , H04B1/71055 , H04L25/0204 , H04L25/021 , H04L25/0242 , H04L25/0328 , H04L2025/03375 , H04L2025/03426 , H04L2025/03477 , H04L2025/03605
摘要： Disclosed is a LMMSE receiver that restores orthogonality of spreading codes in the downlink channel for a spread spectrum signal received over N receive antennas. The FFT-based chip equalizer tap solver reduces the direct matrix inverse of the prior art to the inverse of some submatrices of size N×N with the dimension of the receive antennas, and most efficiently reduces matrix inverses to no larger than 2×2. Complexity is further reduced over a conventional Fast Fourier Transform approach by Hermitian optimization to the inverse of submatrices and tree pruning. For a receiver with N=4 or N=2 with double oversampling, the resulting 4×4 matrices are partitioned into 2×2 block sub-matrices, inverted, and rebuilt into a 4×4 matrix. Common computations are found and repeated computations are eliminated to improve efficiency. Generic design architecture is derived from the special design blocks to eliminate redundancies in complex operations. Optimally, the architecture is parallel and pipelined.
摘要翻译：公开了一种用于在N个接收天线上接收的扩频信号的下行链路信道中恢复扩频码的正交性的LMMSE接收机。基于FFT的码片均衡器抽头解算器将现有技术的直接矩阵逆减少为具有接收天线的尺寸的尺寸为N×N的一些子矩阵的倒数，并且最有效地将矩阵反转减小到不大于2×2。通过Hermitian优化，传统的快速傅立叶变换方法，复杂度进一步降低到子矩阵和树剪枝的倒数。对于具有N = 4或N = 2的具有双重过采样的接收机，所得到的4×4矩阵被划分为2x2块子矩阵，被反转并重建为4×4矩阵。发现常规计算，消除重复计算以提高效率。通用设计架构源于特殊的设计模块，以消除复杂操作中的冗余。最佳的架构是并行和流水线的。

2. 发明授权

US07706430B2 System, apparatus, and method for adaptive weighted interference cancellation using parallel residue compensation 有权
标题翻译：使用并行残差补偿的自适应加权干扰消除的系统，装置和方法
公开(公告)号：US07706430B2
公开(公告)日：2010-04-27
申请号：US11067498
申请日：2005-02-25
申请人： Yuanbin Guo , Dennis McCain , Joseph R. Cavallaro
发明人： Yuanbin Guo , Dennis McCain , Joseph R. Cavallaro
IPC分类号： H04L27/06
CPC分类号： H04B1/71075 , H04B2001/71077 , H04B2201/70707
摘要： A system, apparatus and method for a multi-stage Parallel Residue Compensation (PRC) receiver for enhanced suppression of the Multiple Access Interference (MAI) in Code Division Multiple Access (CDMA) systems. The accuracy of the interference estimation is improved with a set of weights computed from an adaptive Normalized Least Mean Square (NLMS) algorithm. In order to reduce complexity, the commonality of the multi-code processing is extracted and used to derive a structure of PRC to avoid direct interference cancellation. The derived PRC structure reduces the interference cancellation architecture from a complexity that is proportional to the square of the number of users to a complexity that is linear with respect to the number of users. The complexity is further reduced by replacing dedicated multiplier circuits with simple combinational logic.
摘要翻译：一种用于增强抑制码分多址（CDMA）系统中的多址干扰（MAI）的多级并行残差补偿（PRC）接收机的系统，装置和方法。通过从自适应归一化最小二乘法（NLMS）算法计算的一组权重，改善了干扰估计的准确性。为了降低复杂度，提取多码处理的通用性，并用于导出PRC的结构，以避免直接干扰消除。导出的PRC结构从与用户数量的平方成正比于与用户数量相关的复杂度的复杂度降低了干扰消除架构。通过用简单的组合逻辑替换专用乘法电路，进一步降低了复杂度。

3. 发明授权

US07483480B2 FFT accelerated iterative MIMO equalizer receiver architecture 失效
标题翻译： FFT加速迭代MIMO均衡器接收机架构
公开(公告)号：US07483480B2
公开(公告)日：2009-01-27
申请号：US10997442
申请日：2004-11-24
申请人： Yuanbin Guo , Dennis McCain , Joseph R Cavallaro
发明人： Yuanbin Guo , Dennis McCain , Joseph R Cavallaro
IPC分类号： H03K5/159 , H04B1/10
CPC分类号： H04L25/03044 , H04L2025/03426 , H04L2025/03643
摘要： A receiver, such as a CDMA MIMO receiver, includes a LMMSE-based chip-level equalizer constructed so as to implement a FFT accelerated iterative algorithm having a complexity of order O(N log2(N)), where N is the dimension of a covariance matrix. The equalizer uses one of an overlap-save or an over-lap add FFT architecture.
摘要翻译：诸如CDMA MIMO接收机的接收机包括基于LMMSE的码片级均衡器，其被构造为实现具有阶数O（N log2（N））的复杂度的FFT加速迭代算法，其中N是协方差矩阵。均衡器使用重叠保存或重叠加法FFT架构之一。

4. 发明申请

US20060193374A1 System, apparatus, and method for adaptive weighted interference cancellation using parallel residue compensation 有权
标题翻译：使用并行残差补偿的自适应加权干扰消除的系统，装置和方法
公开(公告)号：US20060193374A1
公开(公告)日：2006-08-31
申请号：US11067498
申请日：2005-02-25
申请人： Yuanbin Guo , Dennis McCain , Joseph Cavallaro
发明人： Yuanbin Guo , Dennis McCain , Joseph Cavallaro
IPC分类号： H04L27/06 , H03D1/04 , H04B1/707
CPC分类号： H04B1/71075 , H04B2001/71077 , H04B2201/70707
摘要： A system, apparatus and method for a multi-stage Parallel Residue Compensation (PRC) receiver for enhanced suppression of the Multiple Access Interference (MAI) in Code Division Multiple Access (CDMA) systems. The accuracy of the interference estimation is improved with a set of weights computed from an adaptive Normalized Least Mean Square (NLMS) algorithm. In order to reduce complexity, the commonality of the multi-code processing is extracted and used to derive a structure of PRC to avoid direct interference cancellation. The derived PRC structure reduces the interference cancellation architecture from a complexity that is proportional to the square of the number of users to a complexity that is linear with respect to the number of users. The complexity is further reduced by replacing dedicated multiplier circuits with simple combinational logic.
摘要翻译：一种用于增强抑制码分多址（CDMA）系统中的多址干扰（MAI）的多级并行残差补偿（PRC）接收机的系统，装置和方法。通过从自适应归一化最小二乘法（NLMS）算法计算的一组权重，改善了干扰估计的准确性。为了降低复杂度，提取多码处理的通用性，并用于导出PRC的结构，以避免直接干扰消除。导出的PRC结构从与用户数量的平方成正比于与用户数量相关的复杂度的复杂度降低了干扰消除架构。通过用简单的组合逻辑替换专用乘法电路，进一步降低了复杂度。

5. 发明申请

US20060146759A1 MIMO Kalman equalizer for CDMA wireless communication 审中-公开
标题翻译：用于CDMA无线通信的MIMO卡尔曼均衡器
公开(公告)号：US20060146759A1
公开(公告)日：2006-07-06
申请号：US11029900
申请日：2005-01-04
申请人： Yuanbin Guo , Jianzhong Zhang , Dennis McCain , Joseph Cavallaro
发明人： Yuanbin Guo , Jianzhong Zhang , Dennis McCain , Joseph Cavallaro
IPC分类号： H04B7/216
CPC分类号： H04L25/03057 , H04B1/707 , H04L2025/03426 , H04L2025/03522 , H04L2025/0363
摘要： An apparatus and corresponding method for receiving a MIMO cellular communication signal, the apparatus including: a Kalman filter type of equalizer, responsive to a received signal, for providing a corresponding processed signal indicating information conveyed by the received signal, responsive to a set of values indicating predicted state error correlation at a first instant of time given all noise estimates up through the first instant, for providing ta set of values indicating a product of measurement values and predicted state error correlation at a later instant of time given all process noise estimates up through the later instant. The filter is implemented so as to make use of the displacement structure of the state transition matrix of the Kalman filter allowing shifting operations in place of vector and matrix multiplications. The filter typically includes a transition and common data path that provides to both a Kalman gain processor and a Riccati processor the set of values indicating a product of measurement values and predicted state error correlation at a later instant of time given all process noise estimates up through the later instant.
摘要翻译：一种用于接收MIMO蜂窝通信信号的装置和相应方法，所述装置包括：响应于接收信号的卡尔曼滤波器类型的均衡器，用于响应于一组值提供指示由接收信号传送的信息的相应处理信号指示在第一时刻给出所有噪声估计值的第一时刻的预测状态误差相关性，以便在给定所有过程噪声估计上升的情况下提供指示测量值的乘积的值和在稍后时刻的预测状态误差相关性的值通过后来的时刻。滤波器被实现为利用卡尔曼滤波器的状态转移矩阵的位移结构，允许移位操作代替矢量和矩阵乘法。该滤波器通常包括一个转换和公共数据路径，向卡尔曼增益处理器和Riccati处理器提供一组值，该值指示在所有过程噪声估计值通过的时间点的测量值和预测状态误差相关的乘积后来的时刻。

6. 发明申请

US20060109897A1 FFT accelerated iterative MIMO equalizer receiver architecture 失效
标题翻译： FFT加速迭代MIMO均衡器接收机架构
公开(公告)号：US20060109897A1
公开(公告)日：2006-05-25
申请号：US10997442
申请日：2004-11-24
申请人： Yuanbin Guo , Dennis McCain , Joseph Cavallaro
发明人： Yuanbin Guo , Dennis McCain , Joseph Cavallaro
IPC分类号： H03K5/159 , H04B1/10
CPC分类号： H04L25/03044 , H04L2025/03426 , H04L2025/03643
摘要： A receiver, such as a CDMA MIMO receiver, includes a LMMSE-based chip-level equalizer constructed so as to implement a FFT accelerated iterative algorithm having a complexity of order O(Nlog2(N)), where N is the dimension of a covariance matrix. The equalizer uses one of an overlap-save or an over-lap add FFT architecture.
摘要翻译：诸如CDMA MIMO接收机的接收机包括基于LMMSE的码片级均衡器，其被构造为实现具有阶数O（Nlog 2（N））的复杂度的FFT加速迭代算法，其中N是协方差矩阵的维数。均衡器使用重叠保存或重叠加法FFT架构之一。

7. 发明授权

US07443909B2 Weighted autocorrelation method for downlink CDMA LMMSE equalizers 有权
标题翻译：下行CDMA LMMSE均衡器的加权自相关方法
公开(公告)号：US07443909B2
公开(公告)日：2008-10-28
申请号：US11020055
申请日：2004-12-21
申请人： Hoang Nguyen , Jianzhong Zhang , Yuanbin Guo , Dennis McCain , Joe Dowling
发明人： Hoang Nguyen , Jianzhong Zhang , Yuanbin Guo , Dennis McCain , Joe Dowling
IPC分类号： H04B1/707
CPC分类号： H04B1/71052 , H04B1/71055
摘要： Receiving downlink CDMA signals in a fast-fading environment is facilitated at higher receiver velocities by updating the block-adaptive linear minimum mean square error (LMMSE) downlink CDMA equalizer. The autocorrelation matrix of the observed data is updated by passing block-wise autocorrelation slides through a filter. Each autocorrelation slide is an autocorrelation matrix estimated from a short block of observed data over which the channel can be considered constant. This method achieves a reliable estimate for the autocorrelation matrix when the block size must be small to ensure that the block-wise stationarity assumption holds in cases of fast fading channels. In addition, small block sizes make it possible to satisfy the equalizer delay constraint imposed by hardware and certain voice transmission standards such as CDMA2000 1X where demodulated data must be delivered within only several symbol periods of the signal arrival time.
摘要翻译：通过更新块自适应线性最小均方误差（LMMSE）下行链路CDMA均衡器，在更高的接收机速度下，在快衰落环境中接收下行链路CDMA信号。观察数据的自相关矩阵通过通过滤波器的块自相关滑块来更新。每个自相关幻灯片是从观测数据的短块估计的自相关矩阵，其中信道可以被认为是恒定的。当块大小必须小时，该方法实现了自相关矩阵的可靠估计，以确保在快速衰落信道的情况下保持块状平稳性假设。此外，小块大小使得可以满足由硬件和某些语音传输标准（例如CDMA2000 1X）施加的均衡器延迟约束，其中必须在信号到达时间的几个符号周期内传送解调数据。

8. 发明申请

US20060133462A1 Weighted autocorrelation method for downlink CDMA LMMSE equalizers 有权
标题翻译：下行CDMA LMMSE均衡器的加权自相关方法
公开(公告)号：US20060133462A1
公开(公告)日：2006-06-22
申请号：US11020055
申请日：2004-12-21
申请人： Hoang Nguyen , Jianzhong Zhang , Yuanbin Guo , Dennis McCain , Joe Dowling
发明人： Hoang Nguyen , Jianzhong Zhang , Yuanbin Guo , Dennis McCain , Joe Dowling
IPC分类号： H04B1/707
CPC分类号： H04B1/71052 , H04B1/71055
摘要： Receiving downlink CDMA signals in a fast-fading environment is facilitated at higher receiver velocities by updating the block-adaptive linear minimum mean square error (LMMSE) downlink CDMA equalizer. The autocorrelation matrix of the observed data is updated by passing block-wise autocorrelation slides through a filter. Each autocorrelation slide is an autocorrelation matrix estimated from a short block of observed data over which the channel can be considered constant. This method achieves a reliable estimate for the autocorrelation matrix when the block size must be small to ensure that the block-wise stationarity assumption holds in cases of fast fading channels. In addition, small block sizes make it possible to satisfy the equalizer delay constraint imposed by hardware and certain voice transmission standards such as CDMA2000 1× where demodulated data must be delivered within only several symbol periods of the signal arrival time. Preliminary simulation results obtained under the 1× standard show that the proposed method outperforms the Rake receiver and the ordinary block LMMSE equalizer in the presence of filtering delay. The improvement over the ordinary block LMMSE equalizer is substantial in cases of high mobility.
摘要翻译：通过更新块自适应线性最小均方误差（LMMSE）下行链路CDMA均衡器，在更高的接收机速度下，在快衰落环境中接收下行链路CDMA信号。观察数据的自相关矩阵通过通过滤波器的块自相关滑块来更新。每个自相关幻灯片是从观测数据的短块估计的自相关矩阵，其中信道可以被认为是恒定的。当块大小必须小时，该方法实现了自相关矩阵的可靠估计，以确保在快速衰落信道的情况下保持块状平稳性假设。此外，小块大小使得可以满足由硬件和某些语音传输标准（例如CDMA2000 1x）施加的均衡器延迟约束，其中必须在信号到达时间的几个符号周期内传送解调数据。在1x标准下获得的初步仿真结果表明，所提出的方法在存在滤波延迟的情况下优于Rake接收机和普通块LMMSE均衡器。在高移动性的情况下，对普通块LMMSE均衡器的改进是显着的。

9. 发明申请

US20060109891A1 Reduced parallel and pipelined high-order MIMO LMMSE receiver architecture 有权
公开(公告)号：US20060109891A1
公开(公告)日：2006-05-25
申请号：US10997397
申请日：2004-11-24
申请人： Yuanbin Guo , Jianzhong Zhang , Dennis McCain , Joseph Cavallaro
发明人： Yuanbin Guo , Jianzhong Zhang , Dennis McCain , Joseph Cavallaro
IPC分类号： H04B1/707 , H03H7/30 , H04K1/10
CPC分类号： H04L25/03038 , H04B1/71055 , H04L25/0204 , H04L25/021 , H04L25/0242 , H04L25/0328 , H04L2025/03375 , H04L2025/03426 , H04L2025/03477 , H04L2025/03605
摘要： Disclosed is a LMMSE receiver that restores orthogonality of spreading codes in the downlink channel for a spread spectrum signal received over N receive antennas. The FFT-based chip equalizer tap solver reduces the direct matrix inverse of the prior art to the inverse of some submatrices of size N×N with the dimension of the receive antennas, and most efficiently reduces matrix inverses to no larger than 2×2. Complexity is further reduced over a conventional Fast Fourier Transform approach by Hermitian optimization to the inverse of submatrices and tree pruning. For a receiver with N=4 or N=2 with double oversampling, the resulting 4×4 matrices are partitioned into 2×2 block sub-matrices, inverted, and rebuilt into a 4×4 matrix. Common computations are found and repeated computations are eliminated to improve efficiency. Generic design architecture is derived from the special design blocks to eliminate redundancies in complex operations. Optimally, the architecture is parallel and pipelined.

10. 发明申请

US20070089016A1 Block serial pipelined layered decoding architecture for structured low-density parity-check (LDPC) codes 审中-公开
标题翻译：用于结构化低密度奇偶校验（LDPC）码的块串行流水线分层解码架构
公开(公告)号：US20070089016A1
公开(公告)日：2007-04-19
申请号：US11253207
申请日：2005-10-18
申请人： Tejas Bhatt , Vishwas Sundaramurthy , Victor Stolpman , Dennis McCain
发明人： Tejas Bhatt , Vishwas Sundaramurthy , Victor Stolpman , Dennis McCain
IPC分类号： H03M13/00
CPC分类号： H03M13/1145 , H03M13/1111 , H03M13/1117 , H03M13/1122 , H03M13/1131
摘要： An error correction decoder for block serial pipelined layered decoding of block codes includes primary and mirror memories that are each capable of storing log-likelihood ratios (LLRs) for one or more iterations of an iterative decoding technique. The decoder also includes a plurality of elements capable of processing, for one or more iterations, one or more layers of a parity-check matrix. The elements include an iterative decoder element capable of calculating, for one or more iterations or layers, a LLR adjustment based upon the LLR for a previous iteration/layer, the LLR for the previous iteration/layer being read from the primary memory. The decoder further includes a summation element capable of reading the LLR for the previous iteration/layer from the mirror memory, and calculating the LLR for the iteration/layer based upon the LLR adjustment for the iteration/layer and the previous iteration/layer LLR for the previous iteration/layer.
摘要翻译：用于块码的块串行流水线分层解码的纠错解码器包括主存储器和镜像存储器，每个存储器能够存储用于迭代解码技术的一次或多次迭代的对数似然比（LLR）。解码器还包括能够对一个或多个迭代处理奇偶校验矩阵的一个或多个层的多个元件。元素包括迭代解码器元件，其能够针对一个或多个迭代或层来计算基于先前迭代/层的LLR的LLR调整，从主存储器读取先前迭代/层的LLR。解码器还包括能够从镜像存储器读取先前迭代/层的LLR并且基于迭代/层和先前的迭代/层LLR的LLR调整来计算迭代/层的LLR的求和元素，用于以前的迭代/层。

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