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1. 发明授权

US07145763B2 High-voltage electric double layer capacitor 有权
标题翻译：高压双电层电容器
公开(公告)号：US07145763B2
公开(公告)日：2006-12-05
申请号：US11240373
申请日：2005-10-03
申请人： Yu-Tack Kim , Moon-Bae Lee , Sang-Hyun Lee , Sang-Ick Lee , Chul-Wan Park , Jin-Bae Park , Kwang-Chul Roh , Jin-Hyoung Son , Seung-Hwan Song
发明人： Yu-Tack Kim , Moon-Bae Lee , Sang-Hyun Lee , Sang-Ick Lee , Chul-Wan Park , Jin-Bae Park , Kwang-Chul Roh , Jin-Hyoung Son , Seung-Hwan Song
IPC分类号： H01G9/00 , H01G9/02
CPC分类号： H01G9/155 , H01G9/151 , Y02E60/13
摘要： The present invention relates to a high-voltage electric double layer capacitor (EDLC), and more particularly, to an EDLC in which a surge voltage and an operating voltage are enhanced by improving the structure of a unit cell. The EDLC according to the present invention includes a unit cell having at least three electrodes. According to a preferred embodiment of the present invention, the unit cell has a structure constructed by sequentially laminating a first insulating paper layer with a sheet of insulating paper, a first electrode layer with at least two electrodes, a second insulating paper layer with a sheet of insulating paper, and a second electrode layer with at least one electrode. In accordance with the present invention, the number of electrode-facing surfaces increases, and a surge voltage and an operating voltage increase in proportion to the increased number of the electrode-facing surfaces, resulting in a high energy storage density. Accordingly, the present invention has advantages in that an EDLC with a single cell can be applied to products, an EDLC module can be miniaturized, and there is no need for a protection circuit for maintaining voltage balance on a unit cell basis upon fabrication of the module.
摘要翻译：高电压双层电容器（EDLC）技术领域本发明涉及一种高压双电层电容器（EDLC），更具体地说，涉及一种通过改善晶胞结构来提高浪涌电压和工作电压的EDLC。根据本发明的EDLC包括具有至少三个电极的单元电池。根据本发明的优选实施例，单元电池具有通过依次层叠第一绝缘纸层与绝缘纸片，具有至少两个电极的第一电极层，具有片材的第二绝缘纸层而构成的结构的绝缘纸，以及具有至少一个电极的第二电极层。根据本发明，面向电极的表面的数量增加，并且浪涌电压和工作电压与增加的电极面对表面的数量成比例地增加，导致高的储能密度。因此，本发明的优点在于，具有单个电池的EDLC可以应用于产品，EDLC模块可以被小型化，并且不需要保护电路，用于在制造基于单元的基础上保持基于单元电池的电压平衡模块。

2. 发明申请

US20060221551A1 HIGH-VOLTAGE ELECTRIC DOUBLE LAYER CAPACITOR 有权
标题翻译：高压双电层电容器
公开(公告)号：US20060221551A1
公开(公告)日：2006-10-05
申请号：US11240373
申请日：2005-10-03
申请人： Yu-Tack Kim , Jin-Hyoung Son , Moon-Bae Lee , Sang-Hyun Lee , Kwang-Chul Roh , Seung-Hwan Song , Chul-Wan Park , Sang-Ick Lee , Jin-Bae Park
发明人： Yu-Tack Kim , Jin-Hyoung Son , Moon-Bae Lee , Sang-Hyun Lee , Kwang-Chul Roh , Seung-Hwan Song , Chul-Wan Park , Sang-Ick Lee , Jin-Bae Park
IPC分类号： H01G9/00
CPC分类号： H01G9/155 , H01G9/151 , Y02E60/13
摘要： The present invention relates to a high-voltage electric double layer capacitor (EDLC), and more particularly, to an EDLC in which a surge voltage and an operating voltage are enhanced by improving the structure of a unit cell. The EDLC according to the present invention includes a unit cell having at least three electrodes. According to a preferred embodiment of the present invention, the unit cell has a structure constructed by sequentially laminating a first insulating paper layer with a sheet of insulating paper, a first electrode layer with at least two electrodes, a second insulating paper layer with a sheet of insulating paper, and a second electrode layer with at least one electrode. In accordance with the present invention, the number of electrode-facing surfaces increases, and a surge voltage and an operating voltage increase in proportion to the increased number of the electrode-facing surfaces, resulting in a high energy storage density. Accordingly, the present invention has advantages in that an EDLC with a single cell can be applied to products, an EDLC module can be miniaturized, and there is no need for a protection circuit for maintaining voltage balance on a unit cell basis upon fabrication of the module.
摘要翻译：高电压双层电容器（EDLC）技术领域本发明涉及一种高压双电层电容器（EDLC），更具体地说，涉及一种通过改善晶胞结构来提高浪涌电压和工作电压的EDLC。根据本发明的EDLC包括具有至少三个电极的单元电池。根据本发明的优选实施例，单元电池具有通过依次层叠第一绝缘纸层与绝缘纸片，具有至少两个电极的第一电极层，具有片材的第二绝缘纸层而构成的结构的绝缘纸，以及具有至少一个电极的第二电极层。根据本发明，面向电极的表面的数量增加，并且浪涌电压和工作电压与增加的电极面对表面的数量成比例地增加，导致高的储能密度。因此，本发明的优点在于，具有单个电池的EDLC可以应用于产品，EDLC模块可以被小型化，并且不需要保护电路，用于在制造基于单元的基础上维持基于单元电池的电压平衡模块。

3. 发明授权

US08422307B2 Nonvolatile memory device and read method using dynamically determined read voltages 有权
标题翻译：非易失性存储器件和使用动态确定的读取电压的读取方法
公开(公告)号：US08422307B2
公开(公告)日：2013-04-16
申请号：US12797668
申请日：2010-06-10
申请人： Han Woong Yoo , Seung-Hwan Song , Hee seok Eun , Jun jin Kong
发明人： Han Woong Yoo , Seung-Hwan Song , Hee seok Eun , Jun jin Kong
IPC分类号： G11C16/04
CPC分类号： G11C16/34 , G11C11/5642
摘要： A method of reading a nonvolatile memory device comprises measuring threshold voltage distributions of a plurality of memory cells, combining the measured threshold voltage distributions, and determining local minimum points in the combined threshold voltage distributions to determine read voltages for a predetermined group of memory cells.
摘要翻译：读取非易失性存储器件的方法包括测量多个存储器单元的阈值电压分布，组合测量的阈值电压分布，以及确定组合阈值电压分布中的局部最小点，以确定预定组的存储器单元的读取电压。

4. 发明授权

US08274840B2 Nonvolatile memory devices having built-in memory cell recovery during block erase and methods of operating same 有权
标题翻译：在块擦除期间具有内置存储器单元恢复的非易失性存储器件及其操作方法
公开(公告)号：US08274840B2
公开(公告)日：2012-09-25
申请号：US12498508
申请日：2009-07-07
申请人： Yong-June Kim , Jae-Hong Kim , Kyoung-Lae Cho , Seung-Hwan Song , Jun-Jin Kong
发明人： Yong-June Kim , Jae-Hong Kim , Kyoung-Lae Cho , Seung-Hwan Song , Jun-Jin Kong
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased.
摘要翻译：非易失性存储器件包括在擦除非易失性（例如闪存）存储器单元块的操作期间的支持存储器单元恢复。非易失性存储器系统包括闪存器件和电耦合到闪速存储器件的存储器控制器。存储器控制器被配置为通过向闪存器件发出第一指令来控制闪存器件内的存储器单元恢复操作，该第一指令使存储器块中的擦除存储器单元变成至少部分被编程的存储器单元，然后发出使闪存器件的至少部分编程的存储器单元完全被擦除的第二指令。

5. 发明授权

US08116141B2 Method analyzing threshold voltage distribution in nonvolatile memory 有权
标题翻译：方法分析非易失性存储器中的阈值电压分布
公开(公告)号：US08116141B2
公开(公告)日：2012-02-14
申请号：US12558627
申请日：2009-09-14
申请人： Han Woong Yoo , Seung-Hwan Song , Junjin Kong , Jaehong Kim
发明人： Han Woong Yoo , Seung-Hwan Song , Junjin Kong , Jaehong Kim
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C16/3427
摘要： A distribution analyzing method for a nonvolatile memory device having memory cells exhibiting overlapping first and second threshold voltage distributions includes; detecting a degree of overlap between the first and second threshold voltage distributions by reading data stored in the memory cells and determining read index data from the read data, and estimating a distribution characteristic for at least one of the overlapping threshold voltage distributions using the read index data.
摘要翻译：一种具有显示重叠的第一和第二阈值电压分布的存储单元的非易失性存储器件的分布分析方法包括：通过读取存储在存储单元中的数据并根据读取的数据确定读取的索引数据来检测第一和第二阈值电压分布之间的重叠程度，并且使用读取的索引来估计至少一个重叠阈值电压分布的分布特性数据。

6. 发明申请

US20100091578A1 Nonvolatile Memory Devices Having Built-in Memory Cell Recovery During Block Erase and Methods of Operating Same 有权
标题翻译：在块擦除期间具有内置存储器单元恢复的非易失性存储器件和操作方法相同
公开(公告)号：US20100091578A1
公开(公告)日：2010-04-15
申请号：US12498508
申请日：2009-07-07
申请人： Yong-June Kim , Jae-Hong Kim , Kyoung-Lae Cho , Seung-Hwan Song , Jun-Jin Kong
发明人： Yong-June Kim , Jae-Hong Kim , Kyoung-Lae Cho , Seung-Hwan Song , Jun-Jin Kong
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/16
摘要： Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased.
摘要翻译：非易失性存储器件包括在擦除非易失性（例如闪存）存储器单元块的操作期间的支持存储器单元恢复。非易失性存储器系统包括闪存器件和电耦合到闪速存储器件的存储器控制器。存储器控制器被配置为通过向闪存器件发出第一指令来控制闪存器件内的存储器单元恢复操作，该第一指令使存储器块中的擦除存储器单元变成至少部分被编程的存储器单元，然后发出使闪存器件的至少部分编程的存储器单元完全被擦除的第二指令。

7. 发明申请

US20090222701A1 Apparatus for determining number of bits to be stored in memory cell 失效
标题翻译：用于确定要存储在存储单元中的位数的装置
公开(公告)号：US20090222701A1
公开(公告)日：2009-09-03
申请号：US12219103
申请日：2008-07-16
申请人： Seung-Hwan Song , Kyoung Lae Cho , Jun Jin Kong , Jae Hong Kim
发明人： Seung-Hwan Song , Kyoung Lae Cho , Jun Jin Kong , Jae Hong Kim
IPC分类号： G06F11/00 , G06F12/16
CPC分类号： G11C11/56 , G06F11/1012 , G11C29/00
摘要： Example embodiments relate to an apparatus which may determine a length of data to be stored in a memory cell, and may store the data in a memory based on the determined length. A memory data storage apparatus according to example embodiments may, include: a determination unit that may determine a number of bits of data and a number of bits of data detection information to be stored in a memory cell; a data receiving unit that may receive data corresponding to the determined number of bits; an error correction coding unit that may perform an error correction coding with respect to the received data and generate data detection information corresponding to the number of bits of the data detection information; and a data storage unit that may store the received data and generated data detection information in the memory cell.
摘要翻译：示例性实施例涉及可以确定要存储在存储器单元中的数据的长度的装置，并且可以基于所确定的长度将数据存储在存储器中。根据示例实施例的存储器数据存储装置可以包括：确定单元，其可以确定要存储在存储器单元中的数据的位数和数据检测信息的位数; 数据接收单元，其可以接收与所确定的位数相对应的数据; 纠错编码单元，其可以对所接收的数据执行纠错编码，并生成与数据检测信息的位数相对应的数据检测信息; 以及数据存储单元，其可以将所接收的数据和生成的数据检测信息存储在存储单元中。

8. 发明申请

US20090190396A1 Memory device and method of reading memory data 有权
标题翻译：存储器件和读取存储器数据的方法
公开(公告)号：US20090190396A1
公开(公告)日：2009-07-30
申请号：US12219264
申请日：2008-07-18
申请人： Kyoung Lae Cho , Dong Hun Yu , Jun Jin Kong , Seung-Hwan Song , Yoon Dong Park , Jong Han Kim , Young Hwan Lee
发明人： Kyoung Lae Cho , Dong Hun Yu , Jun Jin Kong , Seung-Hwan Song , Yoon Dong Park , Jong Han Kim , Young Hwan Lee
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/34 , G11C11/5642 , G11C2211/5634
摘要： A memory device and a method of reading multi-bit data stored in a multi-bit cell array may be provided. The memory device may include a multi-bit cell array including a least one memory page with each memory page having a plurality of multi-bit cells, and a determination unit to divide the plurality of multi-bit cells into a first group and second group. The first group may include multi-bit cells with a threshold voltage higher than a reference voltage. The second group may include multi-bit cells with a threshold voltage lower than the reference voltage. The determination unit may sequentially update the first group and second group while changing the reference voltage.
摘要翻译：可以提供存储器件和读取存储在多位单元阵列中的多位数据的方法。存储器件可以包括多比特单元阵列，其包括至少一个存储器页，每个存储器页具有多个多位单元，以及确定单元，用于将多个多位单元划分成第一组和第二组。第一组可以包括具有高于参考电压的阈值电压的多位单元。第二组可以包括阈值电压低于参考电压的多位单元。确定单元可以在改变参考电压的同时顺序地更新第一组和第二组。

9. 发明申请

US20090177931A1 Memory device and error control codes decoding method 有权
标题翻译：存储器件和错误控制代码解码方法
公开(公告)号：US20090177931A1
公开(公告)日：2009-07-09
申请号：US12153121
申请日：2008-05-14
申请人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Kyoung Lae Cho , Sung Chung Park
发明人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Kyoung Lae Cho , Sung Chung Park
IPC分类号： G06F11/07 , G06F11/00
CPC分类号： G06F11/141 , G06F11/1012 , G06F11/1072 , G11C11/5642 , G11C16/10 , G11C29/00
摘要： Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.
摘要翻译：可以提供存储器件和/或错误控制代码（ECC）解码方法。存储器件可以包括存储单元阵列和解码器，以通过第一读取方案对从存储器单元阵列读取的第一数据进行硬判决解码，并且生成输出数据和输出数据的输出数据和错误信息。存储器装置还可以包括和控制单元，用于基于错误信息确定输出数据的错误率，并且基于错误率来确定是否向存储器单元阵列发送用于软判决解码的附加读命令。可以通过这样的存储器件来减少ECC解码时间。

10. 发明申请

US20090046510A1 Apparatus and method for multi-bit programming 审中-公开
标题翻译：多位编程的装置和方法
公开(公告)号：US20090046510A1
公开(公告)日：2009-02-19
申请号：US12007775
申请日：2008-01-15
申请人： Seung-Hwan Song , Jun Jin Kong , Sung Chung Park , Heeseok Eun , Dong Hyuk Chae , Kyoung Lae Cho
发明人： Seung-Hwan Song , Jun Jin Kong , Sung Chung Park , Heeseok Eun , Dong Hyuk Chae , Kyoung Lae Cho
IPC分类号： G11C7/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2211/5641
摘要： Multi-bit programming apparatuses and methods are provided. A multi-bit programming apparatus may include: a first programming unit that stores data corresponding to a number of first bits in at least one first memory cell that may be connected to at least one first bit line; and a second programming unit that stores data corresponding to a number of second bits in at least one second memory cell that may be connected to at least one second bit line. Through this, it may be possible to improve data reliability and increase a number of bits to be stored in the entire memory cell.
摘要翻译：提供了多位编程设备和方法。一种多位编程设备可以包括：第一编程单元，其存储对应于可连接到至少一个第一位线的至少一个第一存储器单元中的多个第一位的数据; 以及第二编程单元，其将可能连接到至少一个第二位线的至少一个第二存储器单元中的与第二位数相对应的数据存储。由此，可以提高数据可靠性并增加要存储在整个存储单元中的位数。

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