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1. 发明授权

US08769354B2 Memory architecture and associated serial direct access circuit 有权
标题翻译：内存架构和相关的串行直接访问电路
公开(公告)号：US08769354B2
公开(公告)日：2014-07-01
申请号：US13536139
申请日：2012-06-28
申请人： Yu-Hsiung Tsai , Po-Hao Huang , Chiun-Chi Shen , Jie-Hau Huang
发明人： Yu-Hsiung Tsai , Po-Hao Huang , Chiun-Chi Shen , Jie-Hau Huang
IPC分类号： G11C29/00
CPC分类号： G11C29/32
摘要： The present invention provides a memory architecture and associated serial direct access (SDA) circuit. The memory architecture includes a memory of a parallel interface and a serial direct access (SDA) circuit. The SDA circuit includes an enable pin, a serial pin and an auto-test module. The enable pin receives an enable bit, wherein the SDA circuit is selectively enabled and disabled in response to the enable bit. When the SDA circuit is enabled, the serial pin sequentially relaying a plurality of serial bits, such that each of the serial bits is associated with one of parallel pins of the parallel interface; in addition, the auto-test module can perform a built-in test of the memory associated with the serial bits.
摘要翻译：本发明提供了存储器架构和相关联的串行直接访问（SDA）电路。存储器架构包括并行接口和串行直接访问（SDA）电路的存储器。 SDA电路包括一个使能引脚，一个串行引脚和一个自动测试模块。使能引脚接收使能位，其中响应于使能位选择性地使能和禁止SDA电路。当SDA电路使能时，串行引脚顺序中继多个串行位，使得每个串行位与并行接口的并行引脚之一相关联; 此外，自动测试模块可以对与串行位相关联的存储器执行内置测试。

2. 发明申请

US20140006885A1 MEMORY ARCHITECTURE AND ASSOCIATED SERIAL DIRECT ACCESS CIRCUIT 有权
标题翻译：存储器架构和相关的串行直接访问电路
公开(公告)号：US20140006885A1
公开(公告)日：2014-01-02
申请号：US13536139
申请日：2012-06-28
申请人： Yu-Hsiung Tsai , Po-Hao Huang , Chiun-Chi Shen , Jie-Hau Huang
发明人： Yu-Hsiung Tsai , Po-Hao Huang , Chiun-Chi Shen , Jie-Hau Huang
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/32
摘要： The present invention provides a memory architecture and associated serial direct access (SDA) circuit. The memory architecture includes a memory of a parallel interface and a serial direct access (SDA) circuit. The SDA circuit includes an enable pin, a serial pin and an auto-test module. The enable pin receives an enable bit, wherein the SDA circuit is selectively enabled and disabled in response to the enable bit. When the SDA circuit is enabled, the serial pin sequentially relaying a plurality of serial bits, such that each of the serial bits is associated with one of parallel pins of the parallel interface; in addition, the auto-test module can perform a built-in test of the memory associated with the serial bits.
摘要翻译：本发明提供了存储器架构和相关联的串行直接访问（SDA）电路。存储器架构包括并行接口和串行直接访问（SDA）电路的存储器。 SDA电路包括一个使能引脚，一个串行引脚和一个自动测试模块。使能引脚接收使能位，其中响应于使能位选择性地使能和禁止SDA电路。当SDA电路使能时，串行引脚顺序中继多个串行位，使得每个串行位与并行接口的并行引脚之一相关联; 此外，自动测试模块可以对与串行位相关联的存储器执行内置测试。

3. 发明授权

US08363477B2 Method of setting trim codes for a flash memory and related device 有权
标题翻译：设置闪存和相关设备的修剪代码的方法
公开(公告)号：US08363477B2
公开(公告)日：2013-01-29
申请号：US13044458
申请日：2011-03-09
申请人： Yu-Hsiung Tsai , Chih-Bin Kuo , Chiun-Chi Shen
发明人： Yu-Hsiung Tsai , Chih-Bin Kuo , Chiun-Chi Shen
IPC分类号： G11C16/04
CPC分类号： G11C16/349 , G11C16/0483
摘要： A flash memory device with auto-trimming functionality includes a memory cell array comprising first memory cells and a fuse sector, a read circuit for reading a memory state of the first memory cells, an offset circuit for outputting offset current values, and an auto-trimming circuit. The auto-trimming circuit has a register for storing a current characteristic, a current control module for modifying input current applied to a first memory cell under test at a first address according to the memory state, and updating the current characteristic to the modified input current, an address counter for starting application of the modified input current to a second memory cell at a second address for test when reading the first memory cell passes, and a programming circuit for programming the fuse sector according to the current characteristic and the offset current values.
摘要翻译：具有自动修整功能的闪速存储器件包括：存储单元阵列，包括第一存储器单元和熔丝扇区;读出电路，用于读取第一存储单元的存储状态;偏移电路，用于输出偏移电流值; 微调电路。自动微调电路具有用于存储电流特性的寄存器，用于根据存储器状态在第一地址处修改施加到被测试的第一存储单元的输入电流的电流控制模块，并将电流特性更新为修改的输入电流用于在读取第一存储单元时通过用于开始将修改的输入电流施加到用于测试的第二地址的第二存储器单元的地址计数器，以及用于根据当前特性和偏移电流值对熔丝扇区进行编程的编程电路。

4. 发明申请

US20120230109A1 Method of Setting Trim Codes for a Flash Memory and Related Device 有权
标题翻译：设置闪存和相关设备的修剪代码的方法
公开(公告)号：US20120230109A1
公开(公告)日：2012-09-13
申请号：US13044458
申请日：2011-03-09
申请人： Yu-Hsiung Tsai , Chih-Bin Kuo , Chiun-Chi Shen
发明人： Yu-Hsiung Tsai , Chih-Bin Kuo , Chiun-Chi Shen
IPC分类号： G11C16/04
CPC分类号： G11C16/349 , G11C16/0483
摘要： A flash memory device with auto-trimming functionality includes a memory cell array comprising first memory cells and a fuse sector, a read circuit for reading a memory state of the first memory cells, an offset circuit for outputting offset current values, and an auto-trimming circuit. The auto-trimming circuit has a register for storing a current characteristic, a current control module for modifying input current applied to a first memory cell under test at a first address according to the memory state, and updating the current characteristic to the modified input current, an address counter for starting application of the modified input current to a second memory cell at a second address for test when reading the first memory cell passes, and a programming circuit for programming the fuse sector according to the current characteristic and the offset current values.
摘要翻译：具有自动修整功能的闪速存储器件包括：存储单元阵列，包括第一存储器单元和熔丝扇区;读出电路，用于读取第一存储单元的存储状态;偏移电路，用于输出偏移电流值; 微调电路。自动微调电路具有用于存储电流特性的寄存器，用于根据存储器状态在第一地址处修改施加到被测试的第一存储单元的输入电流的电流控制模块，并将电流特性更新为修改的输入电流用于在读取第一存储单元时通过用于开始将修改的输入电流施加到用于测试的第二地址的第二存储器单元的地址计数器，以及用于根据当前特性和偏移电流值对熔丝扇区进行编程的编程电路。

5. 发明授权

US07889550B1 Control driver for memory and related method 有权
标题翻译：内存控制驱动程序及相关方法
公开(公告)号：US07889550B1
公开(公告)日：2011-02-15
申请号：US12541976
申请日：2009-08-17
申请人： Yu-Hsiung Tsai , Po-Hao Huang , Yin-Chang Chen
发明人： Yu-Hsiung Tsai , Po-Hao Huang , Yin-Chang Chen
IPC分类号： G11C16/00
CPC分类号： G11C16/12
摘要： A control driver for non-volatile memory includes a driving circuit, a level shift up circuit, and a select circuit. The select circuit receives a plurality of decoding signals, asserts a select signal when all of the decoding signals are asserted, and does not assert the select signal when any of the decoding signals is not asserted. The level shift up circuit receives the select signal, outputs the pull-up signal at a first voltage when the select signal is asserted, and outputs the pull-up signal at a second voltage when the select signal is not asserted. The driving circuit has a pull-up transistor for pulling up a control line signal according to the pull-up signal, and a pull-down transistor for pulling down the control line signal according to the pull-up signal.
摘要翻译：用于非易失性存储器的控制驱动器包括驱动电路，电平转换上升电路和选择电路。选择电路接收多个解码信号，当所有解码信号被断言时断言选择信号，并且当任何解码信号没有被断言时，不选择选择信号。电平上升电路接收选择信号，当选择信号被置位时，以第一电压输出上拉信号，并且当选择信号未被置位时，输出上拉信号为第二电压。驱动电路具有用于根据上拉信号提升控制线信号的上拉晶体管，以及用于根据上拉信号拉下控制线信号的下拉晶体管。

6. 发明申请

US20110038202A1 CONTROL DRIVER FOR MEMORY AND RELATED METHOD 有权
标题翻译：用于存储器和相关方法的控制驱动器
公开(公告)号：US20110038202A1
公开(公告)日：2011-02-17
申请号：US12541976
申请日：2009-08-17
申请人： Yu-Hsiung Tsai , Po-Hao Huang , Yin-Chang Chen
发明人： Yu-Hsiung Tsai , Po-Hao Huang , Yin-Chang Chen
IPC分类号： G11C16/04 , G11C16/06 , G11C7/00 , G11C8/00
CPC分类号： G11C16/12
摘要： A control driver for non-volatile memory includes a driving circuit, a level shift up circuit, and a select circuit. The select circuit receives a plurality of decoding signals, asserts a select signal when all of the decoding signals are asserted, and does not assert the select signal when any of the decoding signals is not asserted. The level shift up circuit receives the select signal, outputs the pull-up signal at a first voltage when the select signal is asserted, and outputs the pull-up signal at a second voltage when the select signal is not asserted. The driving circuit has a pull-up transistor for pulling up a control line signal according to the pull-up signal, and a pull-down transistor for pulling down the control line signal according to the pull-up signal.
摘要翻译：用于非易失性存储器的控制驱动器包括驱动电路，电平转换上升电路和选择电路。选择电路接收多个解码信号，当所有解码信号被断言时断言选择信号，并且当任何解码信号没有被断言时，不选择选择信号。电平上升电路接收选择信号，当选择信号被置位时，以第一电压输出上拉信号，并且当选择信号未被置位时，输出上拉信号为第二电压。驱动电路具有用于根据上拉信号提升控制线信号的上拉晶体管，以及用于根据上拉信号拉下控制线信号的下拉晶体管。

7. 发明申请

US20130343126A1 FLASH MEMORY APPARATUS WITH REFERENCE WORD LINES 有权
标题翻译：闪存存储器与参考字线
公开(公告)号：US20130343126A1
公开(公告)日：2013-12-26
申请号：US13530083
申请日：2012-06-21
申请人： Yu-Hsiung Tsai , Wei-Wu Liao
发明人： Yu-Hsiung Tsai , Wei-Wu Liao
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/26
摘要： The invention provides a flash memory apparatus including at least one flash memory array block and a sense amplifying module. The flash memory array block comprises N storage columns, N reference word-line cell units and a reference storage column, wherein N is a positive integer. Each of the reference word-line cell units disposed in each of the storage columns, wherein, the reference word-line cell units further coupled to a reference word line and a dummy word line. The reference storage column includes a plurality of reference bit-line cells, the reference word line and the dummy word line, one of the reference bit-line cells which coupled to the reference word line is coupled to a reference bit line. The sense amplifying module compares currents from one of the bit lines and the corresponding reference bit line to generate at least one sensing result.
摘要翻译：本发明提供了一种包括至少一个闪速存储器阵列块和感测放大模块的闪存装置。闪存阵列块包括N个存储列，N个参考字线单元单元和参考存储列，其中N是正整数。设置在每个存储列中的每个参考字线单元单元，其中，参考字线单元单元还耦合到参考字线和虚拟字线。参考存储列包括多个参考位线单元，参考字线和虚拟字线，耦合到参考字线的参考位线单元之一耦合到参考位线。感测放大模块比较来自位线之一和相应的参考位线的电流以产生至少一个感测结果。

8. 发明申请

US20130176808A1 WORD LINE BOOST CIRCUIT 有权
标题翻译： WORD LINE BOOST电路
公开(公告)号：US20130176808A1
公开(公告)日：2013-07-11
申请号：US13346734
申请日：2012-01-10
申请人： Yu-Hsiung Tsai , Po-Hao Lee
发明人： Yu-Hsiung Tsai , Po-Hao Lee
IPC分类号： G11C8/08
CPC分类号： G11C8/08
摘要： A word line boost circuit including a first address transfer detector, a second address transfer detector and a boost operation unit is provided. The first address transfer detector generates a first detection pulse in response to variation of a row address signal. The second address transfer detector generates a second detection pulse in response to variation of a column address signal. Moreover, the boost operation unit generates a selection voltage by using a boost voltage according to the first detection pulse, and determines whether or not to use the boost voltage to generate the selection voltage according to a delay time between the first detection pulse and the second detection pulse.
摘要翻译：提供包括第一地址传送检测器，第二地址传送检测器和升压操作单元的字线升压电路。第一地址传送检测器响应于行地址信号的变化产生第一检测脉冲。第二地址传送检测器响应于列地址信号的变化产生第二检测脉冲。此外，升压操作单元通过使用根据第一检测脉冲的升压电压来生成选择电压，并且根据第一检测脉冲和第二检测脉冲之间的延迟时间来判定是否使用升压电压来生成选择电压检测脉冲。

9. 发明授权

US08467245B2 Non-volatile memory device with program current clamp and related method 有权
标题翻译：具有程序电流钳的非易失性存储器件及相关方法
公开(公告)号：US08467245B2
公开(公告)日：2013-06-18
申请号：US13315299
申请日：2011-12-09
申请人： Shang-Wei Fang , Ying-Je Chen , Hong-Yi Liao , Wein-Town Sun , Yu-Hsiung Tsai , Cheng-Jye Liu
发明人： Shang-Wei Fang , Ying-Je Chen , Hong-Yi Liao , Wein-Town Sun , Yu-Hsiung Tsai , Cheng-Jye Liu
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C16/3468
摘要： A method of programming a nonvolatile memory cell which comprises a select transistor and a memory transistor includes applying a preset limit current to a first input of the memory cell, applying a limit voltage to a current limiting circuit electrically connected to a second input of the memory cell, applying a limit voltage to stabilize a voltage drop of the memory cell, and applying a ramped gate voltage to the memory cell to program the memory cell with a preset limited current determined by the current limiting circuit.
摘要翻译：一种对包括选择晶体管和存储晶体管的非易失性存储单元进行编程的方法包括：将预设极限电流施加到存储单元的第一输入端，向限流电路施加极限电压，该限流电路电连接到存储器的第二输入端施加限制电压以稳定存储器单元的电压降，以及将斜坡栅极电压施加到存储器单元，以由由限流电路确定的预置限制电流对存储单元进行编程。

10. 发明授权

US08867279B2 Flash memory apparatus with reference word lines 有权
标题翻译：具有参考字线的闪存设备
公开(公告)号：US08867279B2
公开(公告)日：2014-10-21
申请号：US13530083
申请日：2012-06-21
申请人： Yu-Hsiung Tsai , Wei-Wu Liao
发明人： Yu-Hsiung Tsai , Wei-Wu Liao
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/26
摘要： The invention provides a flash memory apparatus including at least one flash memory array block and a sense amplifying module. The flash memory array block comprises N storage columns, N reference word-line cell units and a reference storage column, wherein N is a positive integer. Each of the reference word-line cell units disposed in each of the storage columns, wherein, the reference word-line cell units further coupled to a reference word line and a dummy word line. The reference storage column includes a plurality of reference bit-line cells, the reference word line and the dummy word line, one of the reference bit-line cells which coupled to the reference word line is coupled to a reference bit line. The sense amplifying module compares currents from one of the bit lines and the corresponding reference bit line to generate at least one sensing result.
摘要翻译：本发明提供了一种包括至少一个闪速存储器阵列块和感测放大模块的闪存装置。闪存阵列块包括N个存储列，N个参考字线单元单元和参考存储列，其中N是正整数。设置在每个存储列中的每个参考字线单元单元，其中，参考字线单元单元还耦合到参考字线和虚拟字线。参考存储列包括多个参考位线单元，参考字线和虚拟字线，耦合到参考字线的参考位线单元之一耦合到参考位线。感测放大模块比较来自位线之一和相应的参考位线的电流以产生至少一个感测结果。

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