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1. 发明授权

US07916371B2 Actuator for holographic information storing apparatus 失效
标题翻译：全息信息存储装置用致动器
公开(公告)号：US07916371B2
公开(公告)日：2011-03-29
申请号：US12391569
申请日：2009-02-24
申请人： Young-min Cheong , Kyoung-woo Lee , Jae-hwan Kwon , Hyoung-jong So , Hong-hee Kim
发明人： Young-min Cheong , Kyoung-woo Lee , Jae-hwan Kwon , Hyoung-jong So , Hong-hee Kim
IPC分类号： G02B26/08
CPC分类号： G02B26/0858
摘要： An actuator to drive a mirror of a holographic information storing apparatus, the actuator including: piezoelectric cells; support members mounted on the piezoelectric cells; a hinge member mounted on the support member; and a post mounted on the hinge member, to support the mirror. The hinge member includes a bar disposed parallel to a rotation axis of the mirror, and a curved portion that extends from the bar.
摘要翻译：一种用于驱动全息信息存储装置的反射镜的致动器，所述致动器包括：压电单元; 安装在压电单元上的支撑构件; 安装在所述支撑构件上的铰链构件; 以及安装在所述铰链构件上的支撑所述反射镜的柱。铰链构件包括平行于反射镜的旋转轴线设置的杆和从杆延伸的弯曲部分。

2. 发明申请

US20090323150A1 ACTUATOR FOR HOLOGRAPHIC INFORMATION STORING APPARATUS 失效
标题翻译：用于全息信息存储设备的执行器
公开(公告)号：US20090323150A1
公开(公告)日：2009-12-31
申请号：US12391569
申请日：2009-02-24
申请人： Young-min Cheong , Kyoung-woo Lee , Jae-hwan Kwon , Hyoung-jong So , Hong-hee Kim
发明人： Young-min Cheong , Kyoung-woo Lee , Jae-hwan Kwon , Hyoung-jong So , Hong-hee Kim
IPC分类号： G02B26/08
CPC分类号： G02B26/0858
摘要： An actuator to drive a mirror of a holographic information storing apparatus, the actuator including: piezoelectric cells; support members mounted on the piezoelectric cells; a hinge member mounted on the support member; and a post mounted on the hinge member, to support the mirror. The hinge member includes a bar disposed parallel to a rotation axis of the mirror, and a curved portion that extends from the bar.
摘要翻译：一种用于驱动全息信息存储装置的反射镜的致动器，所述致动器包括：压电单元; 安装在压电单元上的支撑构件; 安装在所述支撑构件上的铰链构件; 以及安装在所述铰链构件上的支柱，以支撑所述反射镜。铰链构件包括平行于反射镜的旋转轴线设置的杆和从杆延伸的弯曲部分。

3. 发明申请

US20100060966A1 ACTUATOR USING PIEZOELECTRIC ELEMENT AND METHOD OF DRIVING THE SAME 审中-公开
标题翻译：使用压电元件的致动器及其驱动方法
公开(公告)号：US20100060966A1
公开(公告)日：2010-03-11
申请号：US12556793
申请日：2009-09-10
申请人： Young-min Cheong , Kyoung-woo Lee , Jae-hwan Kwon , Hyoung-Jong So , Hong-hee Kim
发明人： Young-min Cheong , Kyoung-woo Lee , Jae-hwan Kwon , Hyoung-Jong So , Hong-hee Kim
IPC分类号： G02B26/08 , G05B1/02 , G03H1/00
CPC分类号： H01L41/0825 , G02B26/0858 , H01L41/042
摘要： An actuator using a piezoelectric element and a method of driving the same. The actuator includes at least one piezoelectric cell moving by displacement according to an input voltage, at least one piezoelectric sensor sensing the displacement of the at least one piezoelectric cell, an error detector detecting an error in the at least one piezoelectric sensor, and a feedback signal generator generating a feedback signal corresponding to the error, thereby performing micromirror driving and sensing.
摘要翻译：使用压电元件的致动器及其驱动方法。致动器包括至少一个根据输入电压移动的压电单元，至少一个感测至少一个压电单元的位移的压电传感器，检测至少一个压电传感器中的误差的误差检测器和反馈信号发生器产生对应于该误差的反馈信号，由此执行微镜驱动和感测。

4. 发明授权

US07687915B2 Semiconductor device having crack stop structure 有权
标题翻译：具有裂纹停止结构的半导体器件
公开(公告)号：US07687915B2
公开(公告)日：2010-03-30
申请号：US12216097
申请日：2008-06-30
申请人： Kyoung-woo Lee , Hong-jae Shin
发明人： Kyoung-woo Lee , Hong-jae Shin
IPC分类号： H01L23/522
CPC分类号： H01L23/585 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： Example embodiments relate to semiconductor devices having a single body crack stop structure configured to reduce or prevent crack propagation and/or moisture penetration. A semiconductor substrate according to example embodiments may include an active region and a crack stop region surrounding the active region. Interlayer insulating layers may be sequentially stacked on the semiconductor substrate. The interlayer insulating layers may include first dual damascene patterns and a first opening. The first dual damascene patterns may be formed in the interlayer insulating layers so as to be perpendicular to the surface of the semiconductor substrate while exposing a first portion of the semiconductor substrate. The first opening may be formed in the crack stop region and may extend through the interlayer insulating layers to expose a second portion of the semiconductor substrate. First dual damascene metal wirings may be formed in the first dual damascene patterns and may contact the exposed first portion of the semiconductor substrate. A single body first crack stop structure may be formed in the first opening so as to contact the exposed second portion of the semiconductor substrate.
摘要翻译：示例实施例涉及具有单体裂纹停止结构的半导体器件，其被配置为减少或防止裂纹扩展和/或湿气穿透。根据示例性实施例的半导体衬底可以包括有源区和围绕有源区的裂纹停止区。层间绝缘层可以顺序堆叠在半导体衬底上。层间绝缘层可以包括第一双镶嵌图案和第一开口。可以在层间绝缘层中形成第一双镶嵌图案，以便在暴露半导体基板的第一部分的同时垂直于半导体基板的表面。第一开口可以形成在裂纹停止区域中并且可以延伸穿过层间绝缘层以暴露半导体衬底的第二部分。第一双镶嵌金属布线可以形成在第一双镶嵌图案中并且可以接触半导体基板的暴露的第一部分。可以在第一开口中形成单体第一裂纹阻挡结构，以与半导体衬底的暴露的第二部分接触。

5. 发明授权

US07598168B2 Method of fabricating dual damascene interconnection and etchant for stripping sacrificial layer 失效
标题翻译：制造双镶嵌互连的方法和用于剥离牺牲层的蚀刻剂
公开(公告)号：US07598168B2
公开(公告)日：2009-10-06
申请号：US11033208
申请日：2005-01-11
申请人： Sang-cheol Han , Kyoung-woo Lee , Mi-young Kim
发明人： Sang-cheol Han , Kyoung-woo Lee , Mi-young Kim
IPC分类号： H01L21/4763 , H01L21/461
CPC分类号： H01L21/76808 , H01L21/31111 , H01L21/31144 , H01L21/76829
摘要： A method of forming a dual damascene semiconductor interconnection and an etchant composition specially adapted for stripping a sacrificial layer in a dual damascene fabrication process without profile damage to a dual damascene pattern are provided. The method includes sequentially forming a first etch stop layer, a first intermetal dielectric, a second intermetal dielectric, and a capping layer on a surface of a semiconductor substrate on which a lower metal wiring is formed; etching the first intermetal dielectric, the second intermetal dielectric, and the capping layer to form a via; forming a sacrificial layer within the via; etching the sacrificial layer, the second intermetal dielectric, and the capping layer to form a trench; removing the sacrificial layer remaining around the via using an etchant composition including NH4F, HF, H2O and a surfactant; and forming an upper metal wiring within the thus formed dual damascene pattern including the via and the trench. The preferred etchant composition for stripping a sacrificial layer in the foregoing dual damascene process consists essentially of NH4F, HF, H2O and a surfactant.
摘要翻译：提供了形成双镶嵌半导体互连的方法和特别适于在双镶嵌制造工艺中剥离牺牲层而不对双镶嵌图案造成损伤的蚀刻剂组合物。该方法包括在其上形成有下金属布线的半导体衬底的表面上顺序地形成第一蚀刻停止层，第一金属间电介质，第二金属间电介质和覆盖层; 蚀刻第一金属间电介质，第二金属间电介质和封盖层以形成通孔; 在通孔内形成牺牲层; 蚀刻牺牲层，第二金属间电介质和覆盖层以形成沟槽; 使用包括NH 4 F，HF，H 2 O和表面活性剂的蚀刻剂组合物除去残留在通孔周围的牺牲层; 以及在由此形成的包括通孔和沟槽的双镶嵌图案中形成上金属布线。用于剥离前述双镶嵌工艺中的牺牲层的优选蚀刻剂组合物基本上由NH 4 F，HF，H 2 O和表面活性剂组成。

6. 发明申请

US20090096104A1 Semiconductor device having crack stop structure 有权
标题翻译：具有裂纹停止结构的半导体器件
公开(公告)号：US20090096104A1
公开(公告)日：2009-04-16
申请号：US12216097
申请日：2008-06-30
申请人： Kyoung-woo Lee , Hong-jae Shin
发明人： Kyoung-woo Lee , Hong-jae Shin
IPC分类号： H01L23/532
CPC分类号： H01L23/585 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： Example embodiments relate to semiconductor devices having a single body crack stop structure configured to reduce or prevent crack propagation and/or moisture penetration. A semiconductor substrate according to example embodiments may include an active region and a crack stop region surrounding the active region. Interlayer insulating layers may be sequentially stacked on the semiconductor substrate. The interlayer insulating layers may include first dual damascene patterns and a first opening. The first dual damascene patterns may be formed in the interlayer insulating layers so as to be perpendicular to the surface of the semiconductor substrate while exposing a first portion of the semiconductor substrate. The first opening may be formed in the crack stop region and may extend through the interlayer insulating layers to expose a second portion of the semiconductor substrate. First dual damascene metal wirings may be formed in the first dual damascene patterns and may contact the exposed first portion of the semiconductor substrate. A single body first crack stop structure may be formed in the first opening so as to contact the exposed second portion of the semiconductor substrate.
摘要翻译：示例实施例涉及具有单体裂纹停止结构的半导体器件，其被配置为减少或防止裂纹扩展和/或湿气穿透。根据示例性实施例的半导体衬底可以包括有源区和围绕有源区的裂纹停止区。层间绝缘层可以顺序堆叠在半导体衬底上。层间绝缘层可以包括第一双镶嵌图案和第一开口。可以在层间绝缘层中形成第一双镶嵌图案，以便在暴露半导体基板的第一部分的同时垂直于半导体基板的表面。第一开口可以形成在裂纹停止区域中并且可以延伸穿过层间绝缘层以暴露半导体衬底的第二部分。第一双镶嵌金属布线可以形成在第一双镶嵌图案中并且可以接触半导体基板的暴露的第一部分。可以在第一开口中形成单体第一裂纹阻挡结构，以与半导体衬底的暴露的第二部分接触。

7. 发明申请

US20070184610A1 INTEGRATED CIRCUIT CAPACITOR STRUCTURE 失效
公开(公告)号：US20070184610A1
公开(公告)日：2007-08-09
申请号：US11733711
申请日：2007-04-10
申请人： Kyoung-woo Lee , Wan-jae Park , Jeong-hoon Ahn , Kyung-tae Lee , Mu-kyeng Jung , Yong-jun Lee , Il-goo Kim , Soo-geun Lee
发明人： Kyoung-woo Lee , Wan-jae Park , Jeong-hoon Ahn , Kyung-tae Lee , Mu-kyeng Jung , Yong-jun Lee , Il-goo Kim , Soo-geun Lee
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L28/40 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

8. 发明授权

US06627540B2 Method for forming dual damascene structure in semiconductor device 失效
标题翻译：在半导体器件中形成双镶嵌结构的方法
公开(公告)号：US06627540B2
公开(公告)日：2003-09-30
申请号：US10233812
申请日：2002-09-03
申请人： Kyoung-woo Lee
发明人： Kyoung-woo Lee
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76811 , H01L21/76813
摘要： A method for forming a dual damascene structure in a semiconductor device, which is capable of preventing defects in node segregation between damascene interconnections and reducing parasitic capacitance, is provided. The method includes sequentially depositing an insulating structure layer including a via level insulating layer and a trench level insulating layer and a hard mask layer on a semiconductor substrate on which an underlying layer including a contact plug is formed, forming a via hole on the via level insulating layer using the hard mask layer, add forming a trench connected to the via hole in the insulating structure layer using the hard mask layer. A predetermined upper portion of the insulating structure layer and the hard mask layer are removed when the trench and the via hole are formed.
摘要翻译：提供了一种在半导体器件中形成双镶嵌结构的方法，其能够防止镶嵌互连之间的节点偏离和减小寄生电容的缺陷。该方法包括在其上形成有包括接触塞的下层的半导体衬底上依次沉积包括通孔层绝缘层和沟槽级绝缘层和硬掩模层的绝缘结构层，在通孔级上形成通孔使用硬掩模层的绝缘层，使用硬掩模层在绝缘结构层中形成连接到通孔的沟槽。当形成沟槽和通孔时，去除绝缘结构层和硬掩模层的预定上部。

9. 发明授权

US07605472B2 Interconnections having double capping layer and method for forming the same 有权
标题翻译：具有双层覆盖层的互连及其形成方法
公开(公告)号：US07605472B2
公开(公告)日：2009-10-20
申请号：US11706885
申请日：2007-02-15
申请人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
发明人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
IPC分类号： H01L29/40
CPC分类号： H01L21/76832 , H01L21/76807 , H01L21/76834 , H01L21/76843 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76883 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.
摘要翻译：提供了包括封盖层和形成互连的方法的半导体器件的互连。半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

10. 发明申请

US20090124093A1 Methods of Forming CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities 有权
标题翻译：使用具有高应力特性的绝缘层的CMOS集成电路的形成方法来改善NMOS和PMOS晶体管载体的迁移率
公开(公告)号：US20090124093A1
公开(公告)日：2009-05-14
申请号：US12353519
申请日：2009-01-14
申请人： Kyoung-woo Lee , Ja-hum Ku , Seung-man Choi
发明人： Kyoung-woo Lee , Ja-hum Ku , Seung-man Choi
IPC分类号： H01L21/469
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.
摘要翻译： CMOS集成电路在其中具有NMOS和PMOS晶体管，并且在NMOS晶体管上延伸绝缘层。提供绝缘层以向NMOS晶体管施加相对较大的拉伸应力。特别地，绝缘层被形成为具有足够高的内部应力特性，其在NMOS晶体管的沟道区域中赋予约2千兆帕（2GPa）至约4千兆帕（4GPa）的范围内的拉伸应力。

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