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1. 发明申请

US20070184610A1 INTEGRATED CIRCUIT CAPACITOR STRUCTURE 失效
公开(公告)号：US20070184610A1
公开(公告)日：2007-08-09
申请号：US11733711
申请日：2007-04-10
申请人： Kyoung-woo Lee , Wan-jae Park , Jeong-hoon Ahn , Kyung-tae Lee , Mu-kyeng Jung , Yong-jun Lee , Il-goo Kim , Soo-geun Lee
发明人： Kyoung-woo Lee , Wan-jae Park , Jeong-hoon Ahn , Kyung-tae Lee , Mu-kyeng Jung , Yong-jun Lee , Il-goo Kim , Soo-geun Lee
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L28/40 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

2. 发明授权

US07229875B2 Integrated circuit capacitor structure 失效
标题翻译：集成电路电容器结构
公开(公告)号：US07229875B2
公开(公告)日：2007-06-12
申请号：US10688077
申请日：2003-10-16
申请人： Kyoung-woo Lee , Wan-jae Park , Jeong-hoon Ahn , Kyung-tae Lee , Mu-kyeng Jung , Yong-jun Lee , Il-goo Kim , Soo-geun Lee
发明人： Kyoung-woo Lee , Wan-jae Park , Jeong-hoon Ahn , Kyung-tae Lee , Mu-kyeng Jung , Yong-jun Lee , Il-goo Kim , Soo-geun Lee
IPC分类号： H01L21/8234
CPC分类号： H01L28/40 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention include a MIM capacitor having a high capacitance with improved manufacturability. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.
摘要翻译：本发明的实施例包括具有高电容且具有改进的可制造性的MIM电容器。这种电容器包括上电极，下电极和位于上电极和下电极之间的电介质层。可以将第一电压施加到上电极，并且可以将不同于第一电压的第二电压施加到下电极。将第一电压施加到上电极的线层位于与下电极相同的水平或比下电极低的水平位置。

3. 发明申请

US20050029010A1 Void-free metal interconnection steucture and method of forming the same 有权
标题翻译：无孔金属互连结构及其形成方法
公开(公告)号：US20050029010A1
公开(公告)日：2005-02-10
申请号：US10891062
申请日：2004-07-15
申请人： Jeong-hoon Ahn , Hyo-jong Lee , Kyung-tae Lee , Kyoung-woo Lee , Soo-geun Lee , Bong-seok Suh
发明人： Jeong-hoon Ahn , Hyo-jong Lee , Kyung-tae Lee , Kyoung-woo Lee , Soo-geun Lee , Bong-seok Suh
IPC分类号： H01L21/768 , H01L21/28 , H01L21/3205 , H01L21/4763 , H01L23/52 , H05K1/11
CPC分类号： H01L21/76877 , H01L21/76847
摘要： A metal interconnection structure includes a lower metal interconnection layer disposed in a first inter-layer dielectric layer. An inter-metal dielectric layer having a via contact hole that exposes a portion of surface of the lower metal layer pattern is disposed on the first inter-layer dielectric layer and the lower metal layer pattern. A second inter-layer dielectric layer having a trench that exposes the via contact hole is formed on the inter-metal dielectric layer. A barrier metal layer is formed on a vertical surface of the via contact and the exposed surface of the second lower metal interconnection layer pattern. A first upper metal interconnection layer pattern is disposed on the barrier metal layer, thereby filling the via contact hole and a portion of the trench. A void diffusion barrier layer is disposed on the first metal interconnection layer pattern and a second upper metal interconnection layer pattern is disposed on the void diffusion barrier layer to completely fill the trench.
摘要翻译：金属互连结构包括设置在第一层间电介质层中的下金属互连层。具有暴露下部金属层图案的一部分表面的通孔接触孔的金属间介电层设置在第一层间电介质层和下部金属层图案上。在金属间电介质层上形成具有暴露通孔接触孔的沟槽的第二层间电介质层。在通孔接触件的垂直表面和第二下部金属互连层图案的暴露表面上形成阻挡金属层。第一上金属互连层图案设置在阻挡金属层上，从而填充通孔接触孔和沟槽的一部分。空隙扩散阻挡层设置在第一金属互连层图案上，并且第二上金属互连层图案设置在空隙扩散阻挡层上以完全填充沟槽。

4. 发明授权

US06953745B2 Void-free metal interconnection structure and method of forming the same 有权
标题翻译：无孔金属互连结构及其形成方法
公开(公告)号：US06953745B2
公开(公告)日：2005-10-11
申请号：US10891062
申请日：2004-07-15
申请人： Jeong-hoon Ahn , Hyo-jong Lee , Kyung-tae Lee , Kyoung-woo Lee , Soo-geun Lee , Bong-seok Suh
发明人： Jeong-hoon Ahn , Hyo-jong Lee , Kyung-tae Lee , Kyoung-woo Lee , Soo-geun Lee , Bong-seok Suh
IPC分类号： H01L21/768 , H01L21/28 , H01L21/3205 , H01L21/4763 , H01L23/52 , H05K1/11
CPC分类号： H01L21/76877 , H01L21/76847
摘要： A metal interconnection structure includes a lower metal interconnection layer disposed in a first inter-layer dielectric layer. An inter-metal dielectric layer having a via contact hole that exposes a portion of surface of the lower metal layer pattern is disposed on the first inter-layer dielectric layer and the lower metal layer pattern. A second inter-layer dielectric layer having a trench that exposes the via contact hole is formed on the inter-metal dielectric layer. A barrier metal layer is formed on a vertical surface of the via contact and the exposed surface of the second lower metal interconnection layer pattern. A first upper metal interconnection layer pattern is disposed on the barrier metal layer, thereby filling the via contact hole and a portion of the trench. A void diffusion barrier layer is disposed on the first metal interconnection layer pattern and a second upper metal interconnection layer pattern is disposed on the void diffusion barrier layer to completely fill the trench.
摘要翻译：金属互连结构包括设置在第一层间电介质层中的下金属互连层。具有暴露下部金属层图案的一部分表面的通孔接触孔的金属间介电层设置在第一层间电介质层和下部金属层图案上。在金属间电介质层上形成具有暴露通孔接触孔的沟槽的第二层间电介质层。在通孔接触件的垂直表面和第二下部金属互连层图案的暴露表面上形成阻挡金属层。第一上金属互连层图案设置在阻挡金属层上，从而填充通孔接触孔和沟槽的一部分。空隙扩散阻挡层设置在第一金属互连层图案上，并且第二上金属互连层图案设置在空隙扩散阻挡层上以完全填充沟槽。

5. 发明授权

US07183195B2 Method of fabricating dual damascene interconnections of microelectronic device using hybrid low k-dielectric and carbon-free inorganic filler 有权
标题翻译：使用混合低k电介质和无碳无机填料制造微电子器件的双镶嵌互连的方法
公开(公告)号：US07183195B2
公开(公告)日：2007-02-27
申请号：US10625007
申请日：2003-07-23
申请人： Kyoung-woo Lee , Soo-geun Lee , Wan-jae Park , Jae-hak Kim , Hong-jae Shin
发明人： Kyoung-woo Lee , Soo-geun Lee , Wan-jae Park , Jae-hak Kim , Hong-jae Shin
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808
摘要： A method of fabricating dual damascene interconnections is provided. A dual damascene region is formed in a hybrid dielectric layer having a dielectric constant of 3.3 or less, and a carbon-free inorganic material is used as a via filler. The present invention improves electrical properties of dual damascene interconnections and minimizes defects.
摘要翻译：提供了一种制造双镶嵌互连的方法。在具有3.3或更小的介电常数的混合电介质层中形成双镶嵌区域，并且使用无碳无机材料作为通孔填料。本发明改进了双镶嵌互连的电性能并使缺陷最小化。

6. 发明授权

US07605472B2 Interconnections having double capping layer and method for forming the same 有权
标题翻译：具有双层覆盖层的互连及其形成方法
公开(公告)号：US07605472B2
公开(公告)日：2009-10-20
申请号：US11706885
申请日：2007-02-15
申请人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
发明人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
IPC分类号： H01L29/40
CPC分类号： H01L21/76832 , H01L21/76807 , H01L21/76834 , H01L21/76843 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76883 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.
摘要翻译：提供了包括封盖层和形成互连的方法的半导体器件的互连。半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

7. 发明授权

US07279733B2 Dual damascene interconnection with metal-insulator-metal-capacitor and method of fabricating the same 失效
标题翻译：金属绝缘体 - 金属电容器的双镶嵌互连及其制造方法
公开(公告)号：US07279733B2
公开(公告)日：2007-10-09
申请号：US10799292
申请日：2004-03-12
申请人： Kyoung-woo Lee , Soo-geun Lee
发明人： Kyoung-woo Lee , Soo-geun Lee
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L21/76807 , H01L23/5223 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： Provided are a dual damascene interconnection with a metal-insulator-metal (MIM) capacitor and a method of fabricating the same. In this structure, an MIM capacitor is formed on a via-level IMD. After the via-level IMD is formed, while an alignment key used for patterning the MIM capacitor is being formed, a via hole is formed to connect a lower electrode of the MIM capacitor and an interconnection disposed under the via-level IMD. Also, an upper electrode of the MIM capacitor is directly connected to an upper metal interconnection during a dual damascene process.
摘要翻译：提供了一种与金属 - 绝缘体 - 金属（MIM）电容器的双镶嵌互连及其制造方法。在该结构中，在通孔级IMD上形成MIM电容器。在形成通孔级IMD之后，当形成MIM电容器图形化的对准键时，形成通孔，以连接MIM电容器的下电极和配置在通孔级IMD下的互连。此外，在双镶嵌工艺期间，MIM电容器的上电极直接连接到上金属互连。

8. 发明申请

US20070138642A1 Interconnections having double capping layer and method for forming the same 有权
标题翻译：具有双层覆盖层的互连及其形成方法
公开(公告)号：US20070138642A1
公开(公告)日：2007-06-21
申请号：US11706885
申请日：2007-02-15
申请人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
发明人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L21/76832 , H01L21/76807 , H01L21/76834 , H01L21/76843 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76883 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.
摘要翻译：提供了包括封盖层和形成互连的方法的半导体器件的互连。半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

9. 发明授权

US07205666B2 Interconnections having double capping layer and method for forming the same 有权
公开(公告)号：US07205666B2
公开(公告)日：2007-04-17
申请号：US11367790
申请日：2006-03-03
申请人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
发明人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
IPC分类号： H01L29/40
CPC分类号： H01L21/76832 , H01L21/76807 , H01L21/76834 , H01L21/76843 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76883 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

10. 发明授权

US07951712B2 Interconnections having double capping layer and method for forming the same 有权
标题翻译：具有双层覆盖层的互连及其形成方法
公开(公告)号：US07951712B2
公开(公告)日：2011-05-31
申请号：US12556094
申请日：2009-09-09
申请人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
发明人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
IPC分类号： H01L21/44
CPC分类号： H01L21/76832 , H01L21/76807 , H01L21/76834 , H01L21/76843 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76883 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.
摘要翻译：提供了包括封盖层和形成互连的方法的半导体器件的互连。半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

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