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1. 发明申请

US20080073787A1 Method forming metal interconnection filling recessed region using electro-plating technique 审中-公开
标题翻译：使用电镀技术形成金属互连填充凹陷区域的方法
公开(公告)号：US20080073787A1
公开(公告)日：2008-03-27
申请号：US11655156
申请日：2007-01-19
申请人： Jun-Hwan Oh , Hyoung-Sik Kim , Il-Goo Kim , Ju-Hyuck Chung
发明人： Jun-Hwan Oh , Hyoung-Sik Kim , Il-Goo Kim , Ju-Hyuck Chung
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/2885 , H01L21/32134 , H01L21/76843 , H01L21/76865 , H01L21/76873 , H01L21/76877
摘要： A metal (e.g., copper) interconnect and related method of fabrication are disclosed in which the metal interconnect is formed by electro-plating a seed layer formed on a recess in a substrate before a metal layer is electro-plated to fill the recess.
摘要翻译：公开了一种金属（例如铜）互连和相关的制造方法，其中通过在金属层被电镀以填充凹部之前，通过电镀电镀在形成于基板的凹部上的种子层来形成金属互连。

2. 发明申请

US20070184610A1 INTEGRATED CIRCUIT CAPACITOR STRUCTURE 失效
公开(公告)号：US20070184610A1
公开(公告)日：2007-08-09
申请号：US11733711
申请日：2007-04-10
申请人： Kyoung-woo Lee , Wan-jae Park , Jeong-hoon Ahn , Kyung-tae Lee , Mu-kyeng Jung , Yong-jun Lee , Il-goo Kim , Soo-geun Lee
发明人： Kyoung-woo Lee , Wan-jae Park , Jeong-hoon Ahn , Kyung-tae Lee , Mu-kyeng Jung , Yong-jun Lee , Il-goo Kim , Soo-geun Lee
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L28/40 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

3. 发明授权

US07176126B2 Method of fabricating dual damascene interconnection 有权
标题翻译：双镶嵌互连方法
公开(公告)号：US07176126B2
公开(公告)日：2007-02-13
申请号：US11157363
申请日：2005-06-21
申请人： Hyeok-sang Oh , Ju-hyuck Chung , Il-goo Kim
发明人： Hyeok-sang Oh , Ju-hyuck Chung , Il-goo Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76807
摘要： In a method of fabricating a dual damascene interconnection, a reliable trench profile is secured. The method includes forming a lower interconnect feature on a substrate, forming a dielectric layer on the lower interconnect feature, forming a hard mask on the dielectric layer, forming a via in the dielectric layer using the hard mask as an etch mask, forming a trench hard mask defining a trench by patterning the hard mask, forming a trench, which is connected with the via and in which an upper interconnection line is formed, by partially etching the dielectric layer using the trench hard mask as an etch mask, removing the trench hard mask using wet etch, and forming an upper interconnection line by filling the trench and the via with an interconnection material.
摘要翻译：在制造双镶嵌互连的方法中，确保可靠的沟槽轮廓。该方法包括在衬底上形成下部互连特征，在下互连特征上形成电介质层，在电介质层上形成硬掩模，使用硬掩模作为蚀刻掩模在电介质层中形成通孔，形成沟槽硬掩模通过图案化硬掩模来形成沟槽，通过使用沟槽硬掩模作为蚀刻掩模部分地蚀刻介电层，形成与通孔连接并且其中形成上互连线的沟槽，去除沟槽硬掩模，并且通过用互连材料填充沟槽和通孔来形成上互连线。

4. 发明授权

US06924228B2 Method of forming a via contact structure using a dual damascene technique 有权
标题翻译：使用双镶嵌技术形成通孔接触结构的方法
公开(公告)号：US06924228B2
公开(公告)日：2005-08-02
申请号：US10748900
申请日：2003-12-30
申请人： Il-Goo Kim , Sang-Rok Hah
发明人： Il-Goo Kim , Sang-Rok Hah
IPC分类号： H01L21/28 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76829
摘要： A method of forming a via contact structure using a dual damascene technique is provided. The method includes forming a lower interconnection line on a semiconductor substrate and sequentially forming an inter-metal dielectric layer and a hard mask layer on the semiconductor substrate having the lower interconnection line. The hard mask layer and the inter-metal dielectric layer are successivley patterned to form a via hole that exposes the lower interconnnection line. A sacrificial layer filling the via hole is formed on the hard mask layer. The sacrificial layer and the hard mask layer are patterned to form a first sacrificial layer pattern having an opening that crosses over the via hole and a second sacrificial layer pattern that remains in the via hole and to simultaneously form a hard mask pattern underneath the first sacrificial layer pattern. The inter-metal dielectric layer is partially etched using the hard mask pattern as an etching mask, thereby forming a trench in the inter-metal dielectric layer. The second sacrificial layer pattern is selectively removed to expose the the lower interconnection line.
摘要翻译：提供了一种使用双镶嵌技术形成通孔接触结构的方法。该方法包括在半导体衬底上形成下互连线，并且在具有下互连线的半导体衬底上依次形成金属间介电层和硬掩模层。硬掩模层和金属间介电层被成功地图案化以形成暴露下部连接线的通孔。在硬掩模层上形成填充通孔的牺牲层。牺牲层和硬掩模层被图案化以形成具有穿过通孔的开口的第一牺牲层图案和保留在通孔中的第二牺牲层图案，并且同时在第一牺牲层下方形成硬掩模图案层图案。使用硬掩模图案作为蚀刻掩模来部分地蚀刻金属间介电层，从而在金属间介电层中形成沟槽。选择性地去除第二牺牲层图案以暴露下部互连线。

5. 发明授权

US06699749B1 Method for manufacturing a metal-insulator-metal capacitor 失效
标题翻译：金属 - 绝缘体 - 金属电容器的制造方法
公开(公告)号：US06699749B1
公开(公告)日：2004-03-02
申请号：US10429321
申请日：2003-05-05
申请人： Seung-Gun Lee , Il-Goo Kim , Ho-Sen Chang , Ju-Hyuk Chang , Sang-Rok Hah
发明人： Seung-Gun Lee , Il-Goo Kim , Ho-Sen Chang , Ju-Hyuk Chang , Sang-Rok Hah
IPC分类号： H01L218242
CPC分类号： H01L21/02071 , H01L21/32136 , H01L28/60
摘要： A method of manufacturing a MIM capacitor having a bottom electrode is provided by forming a metal wire including copper on a substrate. After the metal wire is formed on the substrate, a dielectric film is formed on the metal wire. A top electrode film is formed on the dielectric film, and then the top electrode film is etched to form a top electrode. A hard metallic polymer formed during the etching of the top electrode film is removed using a mixture of an oxygen gas and a fluorocarbon based gas. The lifting of the thin films is effectively prevented, and the yield of the manufacturing process for manufacturing a MIM capacitor is increased. Additionally, the MIM capacitor has a uniform capacitance because the damage to the dielectric film is prevented, and the oxidation of the bottom electrode is also prevented.
摘要翻译：通过在基板上形成包含铜的金属线来提供制造具有底部电极的MIM电容器的方法。在基板上形成金属线之后，在金属线上形成电介质膜。在电介质膜上形成顶部电极膜，然后蚀刻顶部电极膜以形成顶部电极。使用氧气和碳氟化合物气体的混合物除去在顶部电极膜的蚀刻期间形成的硬质金属聚合物。有效地防止薄膜的提升，并且制造MIM电容器的制造工艺的成品率提高。此外，MIM电容器具有均匀的电容，因为防止对电介质膜的损坏，并且还防止了底部电极的氧化。

6. 发明授权

US07229875B2 Integrated circuit capacitor structure 失效
标题翻译：集成电路电容器结构
公开(公告)号：US07229875B2
公开(公告)日：2007-06-12
申请号：US10688077
申请日：2003-10-16
申请人： Kyoung-woo Lee , Wan-jae Park , Jeong-hoon Ahn , Kyung-tae Lee , Mu-kyeng Jung , Yong-jun Lee , Il-goo Kim , Soo-geun Lee
发明人： Kyoung-woo Lee , Wan-jae Park , Jeong-hoon Ahn , Kyung-tae Lee , Mu-kyeng Jung , Yong-jun Lee , Il-goo Kim , Soo-geun Lee
IPC分类号： H01L21/8234
CPC分类号： H01L28/40 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention include a MIM capacitor having a high capacitance with improved manufacturability. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.
摘要翻译：本发明的实施例包括具有高电容且具有改进的可制造性的MIM电容器。这种电容器包括上电极，下电极和位于上电极和下电极之间的电介质层。可以将第一电压施加到上电极，并且可以将不同于第一电压的第二电压施加到下电极。将第一电压施加到上电极的线层位于与下电极相同的水平或比下电极低的水平位置。

7. 发明申请

US20060148264A1 Method of fabricating semiconductor device 失效
公开(公告)号：US20060148264A1
公开(公告)日：2006-07-06
申请号：US11325087
申请日：2006-01-04
申请人： Il-Goo Kim , Ju-Hyuck Chung
发明人： Il-Goo Kim , Ju-Hyuck Chung
IPC分类号： H01L21/302 , H01L21/4763
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/76808
摘要： A method of fabricating a semiconductor device is provided. The method includes forming a low-k dielectric layer on a semiconductor substrate, forming a mask pattern on the low-k dielectric layer, and dry etching the low-k dielectric layer using the mask pattern as an etch mask. A dry etching gas is used for the dry etching of the low-k dielectric layer. The dry etching gas includes a mixture of a gas containing chlorine atoms and at least one gas selected from a group consisting of a gas containing oxygen atoms, a gas containing nitrogen atoms, and an inert gas. The dry etching gas does not contain fluorine atoms.

8. 发明授权

US07033944B2 Dual damascene process 有权
标题翻译：双镶嵌工艺
公开(公告)号：US07033944B2
公开(公告)日：2006-04-25
申请号：US10654770
申请日：2003-09-04
申请人： Wan-Jae Park , Il-Goo Kim , Sang-Rok Hah , Kyoung-Woo Lee
发明人： Wan-Jae Park , Il-Goo Kim , Sang-Rok Hah , Kyoung-Woo Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/76808
摘要： A dual damascene process is disclosed. According to the dual damascene process of the present invention, a first recessed region through an intermetal dielectric layer is filled with a bottom protecting layer, and the bottom protecting layer and the intermetal dielectric layer are simultaneously etched to form a second recessed region that has a shallower depth and wider width than the first recessed region on the first recessed region by using an etch gas selectively etches the intermetal dielectric layer with respect to the bottom protecting layer. In other words, the etch selectivity ratio, the intermetal dielectric layer with respect to the bottom protecting layer, is preferably about 0.5 to about 1.5. Thus, it is possible to form a dual damascene structure without the formation of a byproduct or an oxide fence.
摘要翻译：公开了一种双镶嵌工艺。根据本发明的双镶嵌工艺，通过金属间电介质层的第一凹陷区域填充有底部保护层，同时蚀刻底部保护层和金属间电介质层，以形成第二凹陷区域，该凹陷区域具有通过使用蚀刻气体相对于底部保护层选择性地蚀刻金属间电介质层，比第一凹陷区域上的第一凹陷区域更浅的深度和更宽的宽度。换句话说，相对于底部保护层的蚀刻选择比，金属间电介质层优选为约0.5至约1.5。因此，可以形成双重镶嵌结构而不形成副产物或氧化物栅栏。

9. 发明申请

US20050037605A1 Method of forming metal interconnection layer of semiconductor device 有权
标题翻译：形成半导体器件金属互连层的方法
公开(公告)号：US20050037605A1
公开(公告)日：2005-02-17
申请号：US10888577
申请日：2004-07-09
申请人： Il-Goo Kim , Sang-Rok Hah , Sae-il Son , Kyoung-Woo Lee
发明人： Il-Goo Kim , Sang-Rok Hah , Sae-il Son , Kyoung-Woo Lee
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76813
摘要： Various methods are provided for forming metal interconnection layers of semiconductor devices. One exemplary method for forming a metal interconnection layer of a semiconductor device includes forming an interlayer dielectric layer on a substrate, forming a hard mask layer on the interlayer dielectric layer, wherein the hard mask layer serves as an anti-reflection layer, depositing and patterning a first photoresist layer to form a first photoresist pattern on the hard mask layer, forming a partial via hole in the interlayer dielectric layer by etching the hard mask layer and the interlayer dielectric layer using the first photoresist pattern as an etching mask, removing the first photoresist pattern, depositing a second photoresist layer to fill the partial via hole with photoresist material and patterning the second photoresist layer to form a second photoresist pattern that defines a trench interconnection area which overlaps at least portion of the partial via hole, etching the hard mask layer using the second photoresist pattern as an etching mask to form a hard mask pattern, completely removing the second photoresist pattern and the photoresist material in the partial via hole, etching the interlayer dielectric layer using the hard mask pattern as an etching mask to form the trench interconnection area and to extend the partial via hole to form a full via hole, and filling the full via hole and the trench interconnection area with a conductive material.
摘要翻译：提供用于形成半导体器件的金属互连层的各种方法。用于形成半导体器件的金属互连层的一种示例性方法包括在衬底上形成层间电介质层，在层间介质层上形成硬掩模层，其中硬掩模层用作抗反射层，沉积和图案化第一光致抗蚀剂层，以在硬掩模层上形成第一光致抗蚀剂图案，通过使用第一光致抗蚀剂图案作为蚀刻掩模蚀刻硬掩模层和层间电介质层，在层间电介质层中形成部分通孔，沉积第二光致抗蚀剂层以用光致抗蚀剂材料填充部分通孔并且图案化第二光致抗蚀剂层以形成第二光致抗蚀剂图案，其限定与部分通孔的至少部分重叠的沟槽互连区域，蚀刻硬掩模层，使用第二光致抗蚀剂图案作为蚀刻掩模以形成硬掩模图案 n，完全去除部分通孔中的第二光致抗蚀剂图案和光致抗蚀剂材料，使用硬掩模图案作为蚀刻掩模蚀刻层间介电层，以形成沟槽互连区域并延伸部分通孔以形成完整通孔并且用导电材料填充整个通孔和沟槽互连区域。

10. 发明授权

US07157366B2 Method of forming metal interconnection layer of semiconductor device 有权
标题翻译：形成半导体器件金属互连层的方法
公开(公告)号：US07157366B2
公开(公告)日：2007-01-02
申请号：US10888577
申请日：2004-07-09
申请人： Il-Goo Kim , Sang-Rok Hah , Sae-il Son , Kyoung-Woo Lee
发明人： Il-Goo Kim , Sang-Rok Hah , Sae-il Son , Kyoung-Woo Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76813
摘要： Various methods are provided for forming metal interconnection layers of semiconductor devices. One exemplary method for forming a metal interconnection layer of a semiconductor device includes forming an interlayer dielectric layer on a substrate, forming a hard mask layer on the interlayer dielectric layer, wherein the hard mask layer serves as an anti-reflection layer, depositing and patterning a first photoresist layer to form a first photoresist pattern on the hard mask layer, forming a partial via hole in the interlayer dielectric layer by etching the hard mask layer and the interlayer dielectric layer using the first photoresist pattern as an etching mask, removing the first photoresist pattern, depositing a second photoresist layer to fill the partial via hole with photoresist material and patterning the second photoresist layer to form a second photoresist pattern that defines a trench interconnection area which overlaps at least portion of the partial via hole, etching the hard mask layer using the second photoresist pattern as an etching mask to form a hard mask pattern, completely removing the second photoresist pattern and the photoresist material in the partial via hole, etching the interlayer dielectric layer using the hard mask pattern as an etching mask to form the trench interconnection area and to extend the partial via hole to form a full via hole, and filling the full via hole and the trench interconnection area with a conductive material.
摘要翻译：提供用于形成半导体器件的金属互连层的各种方法。用于形成半导体器件的金属互连层的一种示例性方法包括在衬底上形成层间电介质层，在层间介质层上形成硬掩模层，其中硬掩模层用作抗反射层，沉积和图案化第一光致抗蚀剂层，以在硬掩模层上形成第一光致抗蚀剂图案，通过使用第一光致抗蚀剂图案作为蚀刻掩模蚀刻硬掩模层和层间电介质层，在层间电介质层中形成部分通孔，沉积第二光致抗蚀剂层以用光致抗蚀剂材料填充部分通孔并且图案化第二光致抗蚀剂层以形成第二光致抗蚀剂图案，其限定与部分通孔的至少部分重叠的沟槽互连区域，蚀刻硬掩模层，使用第二光致抗蚀剂图案作为蚀刻掩模以形成硬掩模图案 n，完全去除部分通孔中的第二光致抗蚀剂图案和光致抗蚀剂材料，使用硬掩模图案作为蚀刻掩模蚀刻层间介电层，以形成沟槽互连区域并延伸部分通孔以形成完整通孔并且用导电材料填充整个通孔和沟槽互连区域。

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