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1. 发明申请

US20080112214A1 Electronic assembly having magnetic tunnel junction voltage sensors and method for forming the same 审中-公开
标题翻译：具有磁隧道结电压传感器的电子组件及其形成方法
公开(公告)号：US20080112214A1
公开(公告)日：2008-05-15
申请号：US11590276
申请日：2006-10-30
申请人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Pon Sung Ku
发明人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Pon Sung Ku
IPC分类号： G11C11/00 , G11C11/14 , G11C7/02
CPC分类号： H01L27/088 , B82Y25/00 , G11C11/16 , H01L27/0623 , H01L27/228
摘要： A method and assembly for sensing a voltage with a memory cell (88) is provided. The memory cell includes first and second electrodes (96,112), first and second ferromagnetic bodies (104,108) positioned between the first and second electrodes and an insulating body (94) positioned between the first and second ferromagnetic bodies. The first electrode is electrically connected to a first portion of a microelectronic assembly (47). The second electrode is electrically connected to a second portion of the microelectronic assembly. The voltage across the first and second portions of the microelectronic assembly is determined based on an electrical resistance of the memory cell. The memory cell may be a magnetoresistive random access memory (MRAM) cell. In one embodiment, the memory cell is a magnetic tunnel junction (MTJ) memory cell.
摘要翻译：提供了一种用于利用存储单元（88）感测电压的方法和组件。存储单元包括位于第一和第二电极之间的第一和第二电极（96,112），第一和第二铁磁体（104,108）和位于第一和第二铁磁体之间的绝缘体（94）。第一电极电连接到微电子组件（47）的第一部分。第二电极电连接到微电子组件的第二部分。基于存储单元的电阻来确定微电子组件的第一和第二部分两端的电压。存储单元可以是磁阻随机存取存储器（MRAM）单元。在一个实施例中，存储器单元是磁性隧道结（MTJ）存储单元。

2. 发明授权

US07510883B2 Magnetic tunnel junction temperature sensors and methods 失效
标题翻译：磁隧道结温度传感器及方法
公开(公告)号：US07510883B2
公开(公告)日：2009-03-31
申请号：US11239884
申请日：2005-09-30
申请人： Young Sir Chung , Robert W. Baird , Mark A. Durlam
发明人： Young Sir Chung , Robert W. Baird , Mark A. Durlam
IPC分类号： H01L21/00 , H01L27/14
CPC分类号： H01L27/228 , G01K7/36 , Y10T428/1114
摘要： Techniques of sensing a temperature of a heat source disposed in a substrate of an integrated circuit are provided. According to one exemplary method, a Magnetic Tunnel Junction (“MTJ”) temperature sensor is provided over the heat source. The MTJ temperature sensor comprises an MTJ core configured to output a current during operation thereof. The value of the current varies based on a resistance value of the particular MTJ core. The resistance value of the MTJ core varies as a function of the temperature of the heat source. A value of the current of the MTJ core can then be associated with a corresponding temperature of the heat source.
摘要翻译：提供了感测设置在集成电路的基板中的热源的温度的技术。根据一个示例性方法，在热源上提供磁隧道结（“MTJ”）温度传感器。 MTJ温度传感器包括被配置为在其操作期间输出电流的MTJ内核。电流值根据特定MTJ磁芯的电阻值而变化。 MTJ芯的电阻值随着热源的温度而变化。然后，MTJ芯的电流的值可以与热源的相应温度相关联。

3. 发明授权

US07262069B2 3-D inductor and transformer devices in MRAM embedded integrated circuits 失效
标题翻译： 3-D电感和变压器装置在MRAM嵌入式集成电路中
公开(公告)号：US07262069B2
公开(公告)日：2007-08-28
申请号：US11147599
申请日：2005-06-07
申请人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Bradley N. Engel
发明人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Bradley N. Engel
IPC分类号： H01L21/00
CPC分类号： H01L27/222 , G11C11/16 , H01F17/0006 , H01F19/04 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and at least one inductance element formed on the same substrate using the same fabrication process technology. The inductance element, which may be an inductor or a transformer, is formed at the same metal layer (or layers) as the program lines of the MRAM architecture. Any available metal layer in addition to the program line layers can be added to the inductance element to enhance its efficiency. The concurrent fabrication of the MRAM architecture and the inductance element facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.
摘要翻译：集成电路器件包括磁性随机存取存储器（“MRAM”）结构以及使用相同的制造工艺技术在同一衬底上形成的至少一个电感元件。可以是电感器或变压器的电感元件形成在与MRAM架构的程序线相同的金属层（或多层）上。除了编程线层之外，可以将任何可用的金属层添加到电感元件以增强其效率。 MRAM架构和电感元件的并发制造有助于在衬底的有源电路块上可用的物理空间的有效和成本有效的使用，从而导致三维集成。

4. 发明授权

US07511990B2 Magnetic tunnel junction temperature sensors 失效
标题翻译：磁隧道结温度传感器
公开(公告)号：US07511990B2
公开(公告)日：2009-03-31
申请号：US11240514
申请日：2005-09-30
申请人： Young Sir Chung , Robert W. Baird , Mark A. Durlam
发明人： Young Sir Chung , Robert W. Baird , Mark A. Durlam
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G01K7/01 , G11C29/50 , G11C29/50008 , G11C2029/5002
摘要： An integrated circuit device is provided which includes a heat source disposed in a substrate, and a Magnetic Tunnel Junction (“MTJ”) temperature sensor disposed over the heat source.
摘要翻译：提供一种集成电路装置，其包括设置在基板中的热源和设置在热源上方的磁隧道结（“MTJ”）温度传感器。

5. 发明授权

US07264985B2 Passive elements in MRAM embedded integrated circuits 有权
标题翻译： MRAM嵌入式集成电路中的被动元件
公开(公告)号：US07264985B2
公开(公告)日：2007-09-04
申请号：US11217146
申请日：2005-08-31
申请人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Gregory W. Grynkewich , Eric J. Salter
发明人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Gregory W. Grynkewich , Eric J. Salter
IPC分类号： H01L21/00
CPC分类号： H01L27/228
摘要： An integrated circuit device (300) comprises a substrate (301) and MRAM architecture (314) formed on the substrate (308). The MRAM architecture (314) includes a MRAM circuit (318) formed on the substrate (301); and a MRAM cell (316) coupled to and formed above the MRAM circuit (318). Additionally a passive device (320) is formed in conjunction with the MRAM cell (316). The passive device (320) can be one or more resistors and one or more capacitor. The concurrent fabrication of the MRAM architecture (314) and the passive device (320) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate (404, 504), resulting in three-dimensional integration.
摘要翻译：集成电路器件（300）包括形成在衬底（308）上的衬底（301）和MRAM架构（314）。 MRAM架构（314）包括形成在基板（301）上的MRAM电路（318）。和耦合到并形成在MRAM电路（318）上方的MRAM单元（316）。另外，与MRAM单元（316）结合形成无源器件（320）。无源器件（320）可以是一个或多个电阻器和一个或多个电容器。 MRAM架构（314）和无源器件（320）的并发制造有助于在衬底（404,504）的有源电路块上可用的物理空间的有效和成本有效的使用，导致三维集成。

6. 发明授权

US07239543B2 Magnetic tunnel junction current sensors 有权
标题翻译：磁隧道结电流传感器
公开(公告)号：US07239543B2
公开(公告)日：2007-07-03
申请号：US11262053
申请日：2005-10-28
申请人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Gregory W. Grynkewich , Eric J. Salter , Jiang-Kai Zuo
发明人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Gregory W. Grynkewich , Eric J. Salter , Jiang-Kai Zuo
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1659 , G11C11/1673
摘要： An integrated circuit device includes an active circuit component and a current sensor. The active circuit component may be coupled between a first conductive layer and a second conductive layer, and is configured to produce a first current. The current sensor is disposed over the active circuit component. The current sensor may includes a Magnetic Tunnel Junction (“MTJ”) core disposed between the first conductive layer and the second conductive layer. The MTJ core is configured to sense the first current and produce a second current based on the first current sensed at the MTJ core.
摘要翻译：集成电路装置包括有源电路部件和电流传感器。有源电路组件可以耦合在第一导电层和第二导电层之间，并且被配置为产生第一电流。电流传感器设置在有源电路部件上。电流传感器可以包括设置在第一导电层和第二导电层之间的磁隧道结（“MTJ”）芯。 MTJ内核被配置为基于在MTJ核心处感测到的第一电流来感测第一电流并产生第二电流。

7. 发明授权

US07324369B2 MRAM embedded smart power integrated circuits 有权
标题翻译： MRAM嵌入式智能电源集成电路
公开(公告)号：US07324369B2
公开(公告)日：2008-01-29
申请号：US11170874
申请日：2005-06-30
申请人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Gregory W. Grynkewich , Eric J. Salter
发明人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Gregory W. Grynkewich , Eric J. Salter
IPC分类号： G11C11/00
CPC分类号： G11C11/1659 , H01F10/3254
摘要： An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and a smart power integrated circuit architecture formed on the same substrate using the same fabrication process technology. The fabrication process technology is a modular process having a front end process and a back end process. In the example embodiment, the smart power architecture includes a power circuit component, a digital logic component, and an analog control component formed by the front end process, and a sensor architecture formed by the back end process. The MRAM architecture includes an MRAM circuit component formed by the front end process and an MRAM cell array formed by the back end process. In one practical embodiment, the sensor architecture includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array. The concurrent fabrication of the MRAM architecture and the smart power architecture facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.
摘要翻译：集成电路装置包括使用相同的制造工艺技术在同一衬底上形成的磁性随机存取存储器（“MRAM”）架构和智能电力集成电路架构。制造工艺技术是具有前端工艺和后端工艺的模块化工艺。在该示例性实施例中，智能功率架构包括由前端处理形成的电源电路部件，数字逻辑部件和模拟控制部件以及由后端处理形成的传感器架构。 MRAM架构包括由前端处理形成的MRAM电路部件和由后端处理形成的MRAM单元阵列。在一个实际实施例中，传感器架构包括由MRAM单元阵列使用的相同的磁性隧道结芯体材料形成的传感器部件。 MRAM架构和智能电源架构的并行制造有助于在衬底的有源电路块上可用的物理空间的有效和成本有效的使用，导致三维集成。

8. 发明授权

US07271011B2 Methods of implementing magnetic tunnel junction current sensors 有权
标题翻译：实现磁隧道结电流传感器的方法
公开(公告)号：US07271011B2
公开(公告)日：2007-09-18
申请号：US11262054
申请日：2005-10-28
申请人： Young Sir Chung , Robert W. Baird , Mark A. Durlam
发明人： Young Sir Chung , Robert W. Baird , Mark A. Durlam
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , H01L27/228
摘要： Techniques are provided for sensing a first current produced by an active circuit component. According to these techniques, a current sensor is disposed over the active circuit component. The current sensor includes a Magnetic Tunnel Junction (“MTJ”) core disposed between a first conductive layer and a second conductive layer. The MTJ core can be used to sense the first current and produce a second current based on the first current sensed at the MTJ core.
摘要翻译：提供了用于感测由有源电路部件产生的第一电流的技术。根据这些技术，电流传感器设置在有源电路部件上。电流传感器包括设置在第一导电层和第二导电层之间的磁隧道结（“MTJ”）芯。可以使用MTJ核心来感测第一电流并且基于在MTJ核心处感测到的第一电流产生第二电流。

9. 发明授权

US07169622B2 Magnetoresistive random access memory devices and methods for fabricating the same 有权
标题翻译：磁阻随机存取存储器件及其制造方法
公开(公告)号：US07169622B2
公开(公告)日：2007-01-30
申请号：US10912979
申请日：2004-08-05
申请人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Clarence J. Tracy
发明人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Clarence J. Tracy
IPC分类号： H01L21/00
CPC分类号： G11C11/16 , B82Y10/00 , H01L27/228
摘要： Fabricating a magnetoresistive random access memory cell and a structure for a magnetoresistive random access memory cell begins by providing a substrate having a transistor formed therein. A contact element is formed electrically coupled to the transistor and a dielectric material is deposited within an area partially bounded by the contact element. A digit line is formed within the dielectric material, the digit line overlying a portion of the contact element. A conductive layer is formed overlying the digit line and in electrical communication with the contact element.
摘要翻译：制造磁阻随机存取存储器单元和用于磁阻随机存取存储单元的结构开始于提供其中形成有晶体管的衬底。形成电耦合到晶体管的接触元件，并且电介质材料沉积在由接触元件部分界定的区域内。在电介质材料内形成数字线，数字线覆盖接触元件的一部分。导电层形成在数字线上方并与接触元件电连通。

10. 发明授权

US06909631B2 MRAM and methods for reading the MRAM 有权
标题翻译： MRAM和读取MRAM的方法
公开(公告)号：US06909631B2
公开(公告)日：2005-06-21
申请号：US10679134
申请日：2003-10-02
申请人： Mark A. Durlam , Thomas W. Andre , Mark F. DeHerrera , Bradley N. Engel , Bradley J. Garni , Joseph J. Nahas , Nicholas D. Rizzo , Saied Tehrani
发明人： Mark A. Durlam , Thomas W. Andre , Mark F. DeHerrera , Bradley N. Engel , Bradley J. Garni , Joseph J. Nahas , Nicholas D. Rizzo , Saied Tehrani
IPC分类号： G11C11/15 , G11C11/16 , G11C11/14
CPC分类号： G11C11/16 , G11C11/15
摘要： An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.
摘要翻译：提供了一种MRAM，其通过利用每个存储单元中的隔离或选择装置来最小化MRAM密度的限制。另外，提供了用于读取MRAM的联动存储单元中的MTJ的方法。该方法包括确定至少部分地与MRAM的联动存储器单元的电阻相关联的电气值。切换联合存储器单元中的MTJ，并且在切换MTJ之后确定至少部分地与组合存储器单元的电阻相关联的第二电值。一旦确定了切换之前和切换之后的电气值，则分析两个电气值之间的差异，以确定MTJ的值。

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