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    • 7. 发明授权
    • Delay locked loop
    • 延迟锁定环路
    • US07061287B2
    • 2006-06-13
    • US10883413
    • 2004-06-30
    • Young Jin Jeon
    • Young Jin Jeon
    • H03L7/06
    • H03L7/0814H03L7/089H03L7/10
    • Provided is a delay locked loop comprising: a delay unit for delaying a clock supplied from an external chipset by a predetermined delay amount; a replica for delaying the clock delayed in the delay unit by a delay amount of a clock path and a data path; and a phase detector for generating a signal for controlling the delay amount of the delay unit comparing the clock supplied from the external chipset with a phase of an output of the replica, and generating a reset signal through detection of a change of a clock frequency supplied from the external chipset.
    • 提供了一种延迟锁定环路,包括:延迟单元,用于将从外部芯片组提供的时钟延迟预定延迟量; 用于将延迟单元延迟的时钟延迟时钟路径和数据路径的延迟量的副本; 以及相位检测器,用于产生用于控制延迟单元的延迟量的信号,所述延迟单元将从外部芯片组提供的时钟与复制品的输出的相位进行比较,并且通过检测所提供的时钟频率的变化来产生复位信号 从外部芯片组。