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1. 发明申请

US20070069254A1 Multiple-gate MOS transistor using Si substrate and method of manufacturing the same 有权
标题翻译：使用Si衬底的多栅极MOS晶体管及其制造方法
公开(公告)号：US20070069254A1
公开(公告)日：2007-03-29
申请号：US11447786
申请日：2006-06-06
申请人： Young Cho , Tae Roh , Jong Kim
发明人： Young Cho , Tae Roh , Jong Kim
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/7851
摘要： Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (∩) obtained by patterning an upper portion of a bulk silicon substrate with an embossed pattern, and having a thicker and wider area than the channel region; a nitride layer formed at both side surfaces of the single crystalline active region to expose an upper portion of the single crystalline active region at a predetermined height; and a gate electrode formed to be overlaid with the exposed upper portion of the single crystalline active region of the channel region.
摘要翻译：提供一种多栅极MOS（金属氧化物半导体）晶体管及其制造方法。晶体管包括具有通道区域的单晶有源区域，沟道区域具有通过用压花图案图案化体硅衬底的上部并且具有比沟道区域更厚和更宽的面积而获得的流线型形状（∩）的上部 ; 形成在所述单晶有源区的两个侧表面处的氮化物层，以在预定高度暴露所述单晶有源区的上部; 以及形成为与通道区域的单晶有源区域的暴露的上部分重叠的栅电极。

2. 发明申请

US20050263821A1 Multiple-gate MOS transistor and a method of manufacturing the same 有权
标题翻译：多门MOS晶体管及其制造方法
公开(公告)号：US20050263821A1
公开(公告)日：2005-12-01
申请号：US10989006
申请日：2004-11-16
申请人： Young Cho , Sung Kwon , Tae Roh , Dae Lee , Jong Kim
发明人： Young Cho , Sung Kwon , Tae Roh , Dae Lee , Jong Kim
IPC分类号： H01L21/336 , H01L27/12 , H01L29/786
CPC分类号： H01L29/785 , H01L29/66818
摘要： Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a difference of a thermal oxidation rate depending on a crystal orientation of silicon and a geographical shape of the single-crystal silicon pattern. As the channel is formed in a streamline shape, it is possible to prevent the degradation of reliability due to concentration of an electric field and current driving capability by the gate voltage is improved because the upper portion and both sides of the channel are surrounded by the gate electrodes. In addition, a current crowding effect is prevented due to the expansion region increased in size and source and drain series resistance is reduced by elevated source and drain structures, thereby increasing the current driving capability.
摘要翻译：提供一种多栅极金属氧化物半导体（MOS）晶体管及其制造方法，其中以流线形状实现沟道，扩展区域以逐渐增加的形式实现，并且实现源极和漏极区域通过使用取决于硅的晶体取向的热氧化速率的差异和单晶硅图案的地理形状，在升高的结构中。由于通道形成为流线形状，所以可以防止由于电场集中引起的可靠性的劣化，由于栅极电压的电流驱动能力得到改善，因为通道的上部和两侧被栅电极。此外，由于扩大区域的尺寸增加，阻止了电流拥挤效应，并且通过升高的源极和漏极结构降低了源极和漏极串联电阻，从而增加了电流驱动能力。

3. 发明申请

US20070190709A1 Multiple-gate MOS transistor and a method of manufacturing the same 有权
标题翻译：多门MOS晶体管及其制造方法
公开(公告)号：US20070190709A1
公开(公告)日：2007-08-16
申请号：US11727268
申请日：2007-03-26
申请人： Young Cho , Sung Kwon , Tae Roh , Dae Lee , Jong Kim
发明人： Young Cho , Sung Kwon , Tae Roh , Dae Lee , Jong Kim
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L29/66818
摘要： Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a difference of a thermal oxidation rate depending on a crystal orientation of silicon and a geographical shape of the single-crystal silicon pattern. As the channel is formed in a streamline shape, it is possible to prevent the degradation of reliability due to concentration of an electric field and current driving capability by the gate voltage is improved because the upper portion and both sides of the channel are surrounded by the gate electrodes. In addition, a current crowding effect is prevented due to the expansion region increased in size and source and drain series resistance is reduced by elevated source and drain structures, thereby increasing the current driving capability.
摘要翻译：提供一种多栅极金属氧化物半导体（MOS）晶体管及其制造方法，其中以流线形状实现沟道，扩展区域以逐渐增加的形式实现，并且实现源极和漏极区域通过使用取决于硅的晶体取向的热氧化速率的差异和单晶硅图案的地理形状，在升高的结构中。由于通道形成为流线形状，所以可以防止由于电场集中引起的可靠性的劣化，由于栅极电压的电流驱动能力得到改善，因为通道的上部和两侧被栅电极。此外，由于扩大区域的尺寸增加，阻止了电流拥挤效应，并且通过升高的源极和漏极结构降低了源极和漏极串联电阻，从而增加了电流驱动能力。

4. 发明申请

US20050224880A1 Multi-gate MOS transistor and method of manufacturing the same 有权
标题翻译：多栅极MOS晶体管及其制造方法
公开(公告)号：US20050224880A1
公开(公告)日：2005-10-13
申请号：US11012695
申请日：2004-12-16
申请人： Dae Lee , Tae Roh , Sung Kwon , Il Park , Yil Yang , Byoung Yu , Jong Kim
发明人： Dae Lee , Tae Roh , Sung Kwon , Il Park , Yil Yang , Byoung Yu , Jong Kim
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78 , H01L29/786
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/42392 , H01L29/66795 , H01L29/78645
摘要： Provided are a multi-gate MOS transistor and a method of manufacturing the same. Two silicon fins are vertically stacked on a silicon on insulator (SOI) substrate, and four side surfaces of an upper silicon fin and three side surfaces of a lower silicon fin are used as a channel. Therefore, a channel width is increased, so that current driving capability of a device is improved, and high performance nano-level semiconductor IC and highly integrated memory IC can be manufactured through the optimization and stability of a process.
摘要翻译：提供一种多栅极MOS晶体管及其制造方法。垂直堆叠在硅绝缘体（SOI）基板上的两个硅散热片，上硅片的四个侧表面和下硅片的三个侧表面用作通道。因此，通道宽度增加，从而提高了器件的电流驱动能力，并且可以通过工艺的优化和稳定性来制造高性能纳米级半导体IC和高度集成的存储器IC。

5. 发明申请

US20050140595A1 Sources driver circuit for active matrix electroluminescent display and driving method thereof 有权
标题翻译：用于有源矩阵电致发光显示器的源极驱动电路及其驱动方法
公开(公告)号：US20050140595A1
公开(公告)日：2005-06-30
申请号：US10817838
申请日：2004-04-06
申请人： Yil Yang , Jong Kim , Dae Lee , Tae Roh , Il Park , Sung Kwon , Byoung Yu
发明人： Yil Yang , Jong Kim , Dae Lee , Tae Roh , Il Park , Sung Kwon , Byoung Yu
IPC分类号： G09G3/30
CPC分类号： G09G3/30 , G09G2310/027 , G09G2320/0276
摘要： Provided is a source driver circuit for an active matrix electroluminescent (EL) display including a digital-to-analog converter/ramp circuit for converting a digital signal into an analog signal, and generating a ramp signal in this process, simultaneously, whereby high degree of integration would be possible since a conventional complicated circuit is not required and gray scale with the high characteristic can be implanted, regardless of a change of a temperature or a threshold voltage.
摘要翻译：提供了一种用于有源矩阵电致发光（EL）显示器的源极驱动电路，其包括用于将数字信号转换为模拟信号的数模转换器/斜坡电路，并且在该过程中同时产生斜坡信号，由此高度的集成是可能的，因为不需要常规的复杂电路，而不管温度或阈值电压的变化，都可以植入具有高特性的灰度级。

6. 发明申请

US20070132495A1 Latch circuit and flip-flop 有权
标题翻译：锁存电路和触发器
公开(公告)号：US20070132495A1
公开(公告)日：2007-06-14
申请号：US11520165
申请日：2006-09-13
申请人： Yil Yang , Jong Kim , Tae Roh , Dae Lee
发明人： Yil Yang , Jong Kim , Tae Roh , Dae Lee
IPC分类号： H03K3/00
CPC分类号： H03K19/0013 , H03K3/356156 , H03K3/356182
摘要： A high-reliability, multi-threshold complementary metal oxide semiconductor (CMOS) latch circuit having low sub-threshold leakage current is provided. More particularly, a latch circuit and flip-flop that can be applied in the deep sub-micron era and that are entirely configured of only CMOS using a combination of a high threshold device and a low threshold device and a low-threshold-voltage stack structure, without using a power gating technique such as multi-threshold CMOS (MTCMOS) and a back bias voltage control technique such as variable threshold CMOS (VTCMOS), are provided. The multi-threshold latch circuit includes: a forward clock inverter including a low threshold transistor only and inverting an input-terminal logic state and applying the inverted logic state to an output-terminal logic state when a clock is in a first logic state; and a backward clock inverter including a high threshold transistor, forming a circular latch structure together with the forward clock inverter, and inverting an input-terminal logic state and applying the inverted logic state to an output logic state when the clock is in a second logic state.
摘要翻译：提供了具有低亚阈值泄漏电流的高可靠性，多阈值互补金属氧化物半导体（CMOS）锁存电路。更具体地，可以应用于深亚微米时代的锁存电路和触发器，并且仅使用高阈值器件和低阈值器件和低阈值电压堆叠的组合的CMOS构成结构，而不使用诸如多阈值CMOS（MTCMOS）的功率门控技术和诸如可变阈值CMOS（VTCMOS）的背偏压控制技术。多阈值锁存电路包括：正时时钟反相器，其仅在低阈值晶体管和反相输入端逻辑状态下进行反相，并且当时钟处于第一逻辑状态时将反相逻辑状态应用于输出端逻辑状态; 以及包括高阈值晶体管的反向时钟反相器，与正向时钟反相器一起形成圆形锁存结构，并且当时钟处于第二逻辑时反相输入端逻辑状态并将反相逻辑状态应用于输出逻辑状态州。

7. 发明申请

US20060112258A1 Parallel data path architecture for high energy efficiency 有权
标题翻译：并行数据路径架构，实现高能效
公开(公告)号：US20060112258A1
公开(公告)日：2006-05-25
申请号：US11144703
申请日：2005-06-06
申请人： Yil Yang , Tae Roh , Dae Lee , Sang Lee , Jong Kim
发明人： Yil Yang , Tae Roh , Dae Lee , Sang Lee , Jong Kim
IPC分类号： G06F15/00
CPC分类号： G06F9/3885 , G06F1/32 , G06F1/3287 , G06F9/30141 , G06F9/30156 , G06F9/3822 , G06F9/3824 , Y02D10/171
摘要： Provided is a parallel data path architecture for high energy efficiency. In this architecture, a plurality of parallel process units and a plurality of function units of the process units are controlled by instructions and processed in parallel to improve performance. Also, since only necessary process units and function units are enabled, power dissipation is reduced to enhance energy efficiency. Further, by use of a simple instruction format, hardware can be programmed as the parallel data path architecture for high energy efficiency, which satisfies both excellent performance and low power dissipation, thus elevating hardware flexibility.
摘要翻译：提供了一种用于高能效的并行数据路径架构。在该架构中，处理单元的多个并行处理单元和多个功能单元由指令控制并且并行处理以提高性能。此外，由于只需要必要的处理单元和功能单元，所以功耗降低以提高能量效率。此外，通过使用简单的指令格式，可以将硬件编程为用于高能量效率的并行数据路径体系结构，其既能满足优异性能又具有低功耗，从而提高硬件灵活性。

8. 发明申请

US20050105030A1 Multi-domain liquid crystal display device 有权
标题翻译：多域液晶显示装置
公开(公告)号：US20050105030A1
公开(公告)日：2005-05-19
申请号：US10938854
申请日：2004-09-13
申请人： Jeom Kim , Doo Ko , Joun Lee , Jong Kim , Jong Kim , Young Cho , Mi Chu
发明人： Jeom Kim , Doo Ko , Joun Lee , Jong Kim , Jong Kim , Young Cho , Mi Chu
IPC分类号： G02F1/1362 , G02F1/1337
CPC分类号： G02F1/136213 , G02F1/136286 , G02F2001/136218
摘要： A multi-domain liquid crystal display device comprises first and second substrates facing each other; a liquid crystal layer between the first and second substrates; a plurality of gate bus lines arranged in a first direction on the first substrate and a plurality of data bus lines arranged in a second direction on the first substrate to define a plurality of pixel region; a thin film transistor positioned at a crossing area of the data bus line and the gate bus line, the thin film transistor comprising a gate electrode, a semiconductor layer, and source/drain electrodes; a common-auxiliary electrode comprising at least one electrode in the each pixel region; a plurality of pixel electrodes electrically charged through the thin film transistor; and an alignment layer on at least one substrate between the first and second substrates.
摘要翻译：多域液晶显示装置包括彼此面对的第一和第二基板; 第一和第二基板之间的液晶层; 在第一基板上沿第一方向排列的多个栅极总线和在第一基板上沿第二方向布置的多个数据总线，以限定多个像素区域; 位于数据总线和栅极总线的交叉区域的薄膜晶体管，薄膜晶体管包括栅极，半导体层和源极/漏极; 在每个像素区域中包括至少一个电极的公共辅助电极; 通过薄膜晶体管充电的多个像素电极; 以及在所述第一和第二基板之间的至少一个基板上的取向层。

9. 发明申请

US20060289383A1 Composition for removing conductive materials and manufacturing method of array substrate using the same 有权
标题翻译：用于除去导电材料的组合物及使用其的阵列基板的制造方法
公开(公告)号：US20060289383A1
公开(公告)日：2006-12-28
申请号：US11452387
申请日：2006-06-14
申请人： Kye-Chan Song , Jong Kim , Kyoung-Mook Lee , Sam-Young Cho , Hyun-Cheol Kim , Nam-Seo Kim
发明人： Kye-Chan Song , Jong Kim , Kyoung-Mook Lee , Sam-Young Cho , Hyun-Cheol Kim , Nam-Seo Kim
IPC分类号： C30B33/00 , C09K13/06 , C09K13/00 , B44C1/22
CPC分类号： C23F1/16 , C09K13/06 , C23F1/20 , C23F1/26 , G02F1/13439 , G02F2001/136295
摘要： A composition for removing a conductive material and a manufacturing method of an array substrate using the composition, wherein the composition may include a nitric acid of about 3 to 15 wt %, a phosphoric acid of about 40 to 70 wt %, an acetic acid of about 5 to 35 wt %. The composition may further include a chlorine compound of about 0.05 to 5 wt %, a chlorine stabilizer of about 0.01 to 5 wt %, a pH stabilizer of about 0.01 to 5 wt %, and water of residual quantity.
摘要翻译：用于除去导电材料的组合物和使用该组合物的阵列基板的制造方法，其中所述组合物可以包括约3至15重量％的硝酸，约40至70重量％的磷酸，约5〜35重量％。该组合物可以进一步包括约0.05-5重量％的氯化合物，约0.01至5重量％的氯稳定剂，约0.01至5重量％的pH稳定剂和残留量的水。

10. 发明申请

US20050195560A1 Portable computer and method for mounting a flat panel display device thereon 有权
标题翻译：便携式计算机及其上安装平板显示装置的方法
公开(公告)号：US20050195560A1
公开(公告)日：2005-09-08
申请号：US11096080
申请日：2005-04-01
申请人： Jong Kim , Young Cho
发明人： Jong Kim , Young Cho
IPC分类号： G02F1/13 , G06F1/16 , G09F9/00
CPC分类号： G06F1/1637 , G02F1/133308 , G02F2001/133314 , G02F2001/133317 , G02F2001/13332 , G02F2201/46 , G02F2201/465 , G06F1/1616 , Y10S248/917 , Y10T16/554
摘要： A portable computer including a housing having first and second sections, the first section having an information input device and the second section having a case having a first fastening element; a display panel including a second fastening element at a rear surface of the panel, the case and the display panel being attached through the first and second fastening elements; a hinge coupling the first and the second sections to each other; and a display panel support member having a third fastening element, the display panel support member being attached to the display panel through the third fastening element.
摘要翻译：一种便携式计算机，包括具有第一和第二部分的壳体，所述第一部分具有信息输入装置，所述第二部分具有壳体，所述壳体具有第一紧固元件; 显示面板，其包括在所述面板的后表面处的第二紧固元件，所述壳体和所述显示面板通过所述第一和第二紧固元件附接; 将第一和第二部分彼此联接的铰链; 以及具有第三紧固元件的显示面板支撑构件，所述显示面板支撑构件通过所述第三紧固元件附接到所述显示面板。

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