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1. 发明授权

US07975253B2 Power supply noise analysis model generating method and power supply noise analysis model generating apparatus 有权
标题翻译：电源噪声分析模型生成方法和电源噪声分析模型生成装置
公开(公告)号：US07975253B2
公开(公告)日：2011-07-05
申请号：US11864122
申请日：2007-09-28
申请人： Yoshiyuki Iwakura , Shogo Fujimori , Tendou Hirai , Hitoshi Chida , Kazuyoshi Kanei , Koutarou Nimura
发明人： Yoshiyuki Iwakura , Shogo Fujimori , Tendou Hirai , Hitoshi Chida , Kazuyoshi Kanei , Koutarou Nimura
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78 , H05K1/0216 , H05K3/0005
摘要： An object is to simplify a power supply noise analysis model of a circuit board. CAD data of the circuit board is obtained from a CAD apparatus, and overlapping power supply islands among power supply islands existing in different layers of the circuit board are extracted as a power supply pair. Nodes are arranged in the extracted power supply pair, and the nodes of the power supply pair are projected on the power supply islands to which the power supply pair belongs. A mesh region which encloses each node is determined for each power supply island, and impedance (L, R, C) between nodes is calculated. Then, a power supply noise analysis model is created based on the impedance between nodes in each layer, and a capacitance between layers.
摘要翻译：目的是简化电路板的电源噪声分析模型。从CAD装置获得电路板的CAD数据，并且提取存在于电路板的不同层中的电源岛之间的重叠电源岛作为电源对。节点布置在提取的电源对中，并且电源对的节点投影在电源对所属的电源岛上。为每个电源岛确定封闭每个节点的网格区域，并计算节点之间的阻抗（L，R，C）。然后，基于每层中的节点之间的阻抗以及层之间的电容来创建电源噪声分析模型。

2. 发明申请

US20080163138A1 POWER SUPPLY NOISE ANALYSIS MODEL GENERATING METHOD AND POWER SUPPLY NOISE ANALYSIS MODEL GENERATING APPARATUS 有权
标题翻译：电源噪声分析模型生成方法和电源噪声分析模型生成装置
公开(公告)号：US20080163138A1
公开(公告)日：2008-07-03
申请号：US11864122
申请日：2007-09-28
申请人： Yoshiyuki Iwakura , Shogo Fujimori , Tendou Hirai , Hitoshi Chida , Kazuyoshi Kanei , Koutarou Nimura
发明人： Yoshiyuki Iwakura , Shogo Fujimori , Tendou Hirai , Hitoshi Chida , Kazuyoshi Kanei , Koutarou Nimura
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78 , H05K1/0216 , H05K3/0005
摘要： An object is to simplify a power supply noise analysis model of a circuit board. CAD data of the circuit board is obtained from a CAD apparatus, and overlapping power supply islands among power supply islands existing in different layers of the circuit board are extracted as a power supply pair. Nodes are arranged in the extracted power supply pair, and the nodes of the power supply pair are projected on the power supply islands to which the power supply pair belongs. A mesh region which encloses each node is determined for each power supply island, and impedance (L, R, C) between nodes is calculated. Then, a power supply noise analysis model is created based on the impedance between nodes in each layer, and a capacitance between layers.
摘要翻译：目的是简化电路板的电源噪声分析模型。从CAD装置获得电路板的CAD数据，并且提取存在于电路板的不同层中的电源岛之间的重叠电源岛作为电源对。节点布置在提取的电源对中，并且电源对的节点投影在电源对所属的电源岛上。为每个电源岛确定封闭每个节点的网格区域，并计算节点之间的阻抗（L，R，C）。然后，基于每层中的节点之间的阻抗以及层之间的电容来创建电源噪声分析模型。

3. 发明授权

US06915249B1 Noise checking method and apparatus 失效
标题翻译：噪声检查方法和装置
公开(公告)号：US06915249B1
公开(公告)日：2005-07-05
申请号：US09708470
申请日：2000-11-09
申请人： Toshiro Sato , Yuji Suwa , Yoshiyuki Iwakura , Kazunari Gotou , Toshiaki Sato , Kazuyoshi Kanei , Masaki Tosaka , Yasuhiro Yamashita
发明人： Toshiro Sato , Yuji Suwa , Yoshiyuki Iwakura , Kazunari Gotou , Toshiaki Sato , Kazuyoshi Kanei , Masaki Tosaka , Yasuhiro Yamashita
IPC分类号： G06F15/18 , G06F17/50 , G06G7/00 , G06G7/62 , H04M11/04
CPC分类号： G06F17/5036
摘要： In order to achieve augmentation of the accuracy in calculation of noise and augmentation of the accuracy in a noise check which is performed, for example, when an electronic circuit is designed and further realize significant reduction of the time required for a noise check and augmentation of the operation efficiency by reduction of the man-hours of a designer in a noise analysis, a noise checking apparatus includes a model production section (3) for producing a simulation model of a circuit portion relating to a noticed wiring line, a simulation section (4) for performing a simulation using the simulation model to calculate a signal waveform which propagates in the noticed wiring line and calculate a noise waveform superposed on the signal waveform for each kind of noise, a noise waveform synthesis section (5) for synthesizing the signal waveform and the noise waveforms with generation timings of the noise waveforms taken into consideration to obtain a noise composite waveform, and a noise checking section (6) for performing noise checking based on the noise composite waveform.
摘要翻译：为了实现噪声检查的精度的提高和进行噪声检查的精度的提高，例如，当设计电子电路时，进一步实现噪声检查和增加所需的时间的显着减少通过降低设计者在噪声分析中的工时的操作效率，噪声检查装置包括用于产生与注意的布线相关的电路部分的仿真模型的模型生成部（3），模拟部（ 4），用于使用所述模拟模型进行模拟，以计算在注意的布线中传播的信号波形，并计算叠加在每种噪声的信号波形上的噪声波形，用于合成信号的噪声波形合成部分（5）波形和噪声波形，并考虑噪声波形的产生定时，以获得噪声复合波形，以及用于基于噪声复合波形进行噪声检查的噪声检查部（6）。

4. 发明授权

US06662132B2 Noise analyzing method and apparatus and storage medium 有权
公开(公告)号：US06662132B2
公开(公告)日：2003-12-09
申请号：US09733076
申请日：2000-12-11
申请人： Yasuhiro Yamashita , Shogo Fujimori , Ryoji Yamada , Kazuhiko Tokuda , Makoto Suwada , Masaki Tosaka , Jiro Yoneda , Yoshiyuki Iwakura , Kazunari Gotou
发明人： Yasuhiro Yamashita , Shogo Fujimori , Ryoji Yamada , Kazuhiko Tokuda , Makoto Suwada , Masaki Tosaka , Jiro Yoneda , Yoshiyuki Iwakura , Kazunari Gotou
IPC分类号： G06F1750
CPC分类号： G01R31/30
摘要： A noise analyzing method analyzes a crosstalk noise based on circuit data in which buses having the same signal transmitting direction and buses having opposite signal transmitting directions are distinguished from each other, by analyzing the crosstalk noise only for the same signal transmitting direction with respect to the buses having the same signal transmitting direction.

5. 发明授权

US6117183A Interactive CAD apparatus for designing packaging of logic circuit design 失效
标题翻译：用于设计逻辑电路设计封装的交互式CAD设备
公开(公告)号：US6117183A
公开(公告)日：2000-09-12
申请号：US894695
申请日：1997-08-26
申请人： Mieko Teranishi , Yoshiyuki Iwakura , Masaharu Nishimura , Akira Katsumata , Masato Ariyama
发明人： Mieko Teranishi , Yoshiyuki Iwakura , Masaharu Nishimura , Akira Katsumata , Masato Ariyama
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5068
摘要： Disclosed is an interactive CAD apparatus for logic circuit packaging design, wherein provisions are made to display delay times in real time when a component is being moved, so that error-contributing components and interconnections can be easily identified and the optimum position can be easily determined. The apparatus includes: a component moving unit, responsive to an operator's instruction, for moving a component on a display screen where a component placement diagram is displayed; an associated path extraction unit for extracting a signal path associated with the component being moved by the component moving unit; a temporary position calculation unit for calculating temporary position data representing a placement position corresponding to the position of the component on the display screen at prescribed intervals of time when the component is being moved by the component moving unit; an associated path delay calculation unit for successively calculating delay values for the signal path extracted by the associated path extraction unit, based on the temporary position data calculated by the temporary position calculation unit; and an associated path delay display unit for successively displaying the delay values calculated by the associated path delay calculation unit.
摘要翻译： PCT No.PCT / JP97 / 00015 Sec。 371日期：1997年8月26日 102（e）日期1997年8月26日PCT 1997年1月8日PCT公布。公开号WO97 / 25681 日期1997年7月17日公开是一种用于逻辑电路封装设计的交互式CAD设备，其中规定了在组件移动时实时显示延迟时间，从而可以容易地识别出错误的组件和互连，并且最优位置可以很容易地确定。该装置包括：组件移动单元，响应于操作者的指示，用于移动显示屏幕上的组件，其中显示组件放置图; 相关联的路径提取单元，用于提取与由所述分量移动单元移动的分量相关联的信号路径; 临时位置计算单元，用于当由所述分量移动单元移动所述分量时，以规定的时间间隔计算表示与所述分量在所述显示屏幕上的位置相对应的放置位置的临时位置数据; 相关联的路径延迟计算单元，用于基于由临时位置计算单元计算的临时位置数据连续地计算由相关联的路径提取单元提取的信号路径的延迟值; 以及相关联的路径延迟显示单元，用于连续显示由相关联的路径延迟计算单元计算的延迟值。

6. 发明授权

US5898870A Load balancing for a parallel computer system by employing resource utilization target values and states 失效
标题翻译：通过采用资源利用目标值和状态，并行计算机系统的负载平衡
公开(公告)号：US5898870A
公开(公告)日：1999-04-27
申请号：US766853
申请日：1996-12-13
申请人： Tooru Okuda , Yoshiyuki Iwakura , Hirofumi Nagasuka
发明人： Tooru Okuda , Yoshiyuki Iwakura , Hirofumi Nagasuka
IPC分类号： G06F15/16 , G06F9/50 , G06F15/177 , G06F15/00
CPC分类号： G06F9/505
摘要： A load sharing method for a parallel computer system having a computer group including a plurality of computers and an operation management mechanism which is a computer for managing the operation of the computer group. The method shares a load for executing a plurality of kinds of work processes to the plurality of computers in the computer group, and includes the steps of setting resource utilization target values by work for the plurality of computers in the computer group; collecting resource utilization states by work for the plurality of computers in the computer group to thereby inform the operation management mechanism of the resource utilization states; selecting a computer to execute a newly requested work process from the plurality of computers in the computer group on the basis of the differences between resource utilization target parameter values by work in the plurality of computers in the computer group and current values of a parameter indicating the reporting resource utilization states by work; and executing, in the selected computer, the newly requested work process
摘要翻译：一种具有包括多个计算机的计算机组的并行计算机系统的负载共享方法和作为用于管理计算机组的操作的计算机的操作管理机构。该方法向计算机组中的多个计算机共享用于执行多种工作处理的负载，并且包括以下步骤：通过工作为计算机组中的多个计算机设置资源利用目标值; 通过工作为计算机组中的多个计算机收集资源利用状态，从而向资源利用状态的操作管理机制通知; 基于计算机组中的多个计算机中的工作的资源利用目标参数值之间的差异，选择计算机来执行来自计算机组中的多个计算机的新请求的工作处理，以及指示计算机组的参数的当前值按工作报告资源利用状况; 并且在所选择的计算机中执行新请求的工作过程

7. 发明授权

US5600568A Analysis system for the delay time in logic equipment 失效
标题翻译：逻辑设备延时时间分析系统
公开(公告)号：US5600568A
公开(公告)日：1997-02-04
申请号：US277742
申请日：1994-07-20
申请人： Yoshiyuki Iwakura , Atsushi Kimura
发明人： Yoshiyuki Iwakura , Atsushi Kimura
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： The logic equipment delay time analysis system provides not only a number of parallel dedicated delay time processors which perform calculation of the delay time, but also a processor-to-processor communications device which is connected to each of the delay time processors and performs communications between these delay time processors. The circuit model of the logic equipment is divided by a circuit model division section into a number of small logic circuits, Data with regard to each of the divided circuit models is assigned to the individual delay time processors and initial values are set into each of the delay time processors, so that the delay times for all paths from each pin at which a signal is input to circuits at which output signals are generated are calculated.
摘要翻译：逻辑设备延迟时间分析系统不仅提供了执行延迟时间的计算的多个并行专用延迟时间处理器，而且还提供了一个处理器到处理器的通信设备，其连接到每个延迟时间处理器并执行这些延迟时间处理器。逻辑设备的电路模型由电路模型划分部分划分成多个小逻辑电路，关于每个分割电路模型的数据被分配给各个延迟时间处理器，初始值被设置为延迟时间处理器，从而计算从信号输入的每个引脚到产生输出信号的电路的所有路径的延迟时间。

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