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1. 发明授权

US4707718A Read-only memory 失效
标题翻译：只读存储器
公开(公告)号：US4707718A
公开(公告)日：1987-11-17
申请号：US635401
申请日：1984-07-30
申请人： Yoshio Sakai , Ryo Nagai , Shuichi Yamamoto , Hideo Nakamura , Kouki Noguchi
发明人： Yoshio Sakai , Ryo Nagai , Shuichi Yamamoto , Hideo Nakamura , Kouki Noguchi
IPC分类号： G11C17/00 , G11C17/08 , H01L21/8246 , H01L23/528 , H01L27/10 , H01L27/112 , H01L29/78
CPC分类号： H01L27/112 , H01L23/528 , H01L2924/0002 , Y10S257/927
摘要： A read-only memory which features a high operation speed and a high degree of integration. A first layer works as ground lines and word lines, and a second layer works as data lines. The word lines and the data lines are arranged linearly to reduce parasitic capacitance and parasitic resistance, and hence to achieve high-speed operation. The invention is adapted where data of large quantities are to be treated, without effecting the rewriting.
摘要翻译：具有高操作速度和高集成度的只读存储器。第一层作为地线和字线工作，第二层作为数据线工作。字线和数据线被线性布置以减小寄生电容和寄生电阻，从而实现高速操作。本发明适用于在不影响重写的情况下处理大量数据的情况。

2. 发明授权

US5832248A Semiconductor integrated circuit having CPU and multiplier 失效
标题翻译：具有CPU和乘法器的半导体集成电路
公开(公告)号：US5832248A
公开(公告)日：1998-11-03
申请号：US555262
申请日：1995-11-08
申请人： Kazumasa Kishi , Shigeki Masumura , Hideo Nakamura , Kouki Noguchi , Shumpei Kawasaki , Yasushi Akao
发明人： Kazumasa Kishi , Shigeki Masumura , Hideo Nakamura , Kouki Noguchi , Shumpei Kawasaki , Yasushi Akao
IPC分类号： G06F7/52 , G06F7/506 , G06F7/523 , G06F9/302 , G06F9/32 , G06F9/38 , G06F15/78 , G06F12/00
CPC分类号： G06F9/3001 , G06F15/7864 , G06F9/325 , G06F9/3885
摘要： A logic LSI chip includes a CPU, a bus, a memory, and a multiplier. In addition, the logic LSI chip includes a command signal line for transferring, from the CPU to the multiplier, a command regarding a multiplication instruction relating to data read out, while the data is being read out from the memory, so that the multiplier can fetch the data directly from the bus. While the CPU is reading data from the memory, therefore, a command of a multiplication instruction relating to data read out is transferred from the CPU to the multiplier. A bus cycle control circuit receives a state signal from the multiplier when the multiplier is executing a repetitional operation and the bus cycle control circuit responds to the state signal by signalling the CPU to delay issuance of a succeeding command to the multiplier.
摘要翻译：逻辑LSI芯片包括CPU，总线，存储器和乘法器。此外，逻辑LSI芯片包括用于在从存储器读出数据的同时从CPU向乘法器传送关于与读出的数据相关的乘法指令的命令的命令信号线，使得乘法器从总线直接获取数据。因此，当CPU从存储器读取数据时，与读出的数据相关的乘法指令的命令从CPU传送到乘法器。当乘法器执行重复操作时，总线周期控制电路接收来自乘法器的状态信号，并且总线周期控制电路通过发信号通知CPU来延迟向乘法器发出后续命令来响应状态信号。

3. 发明授权

US5321845A Single-chip microcomputer including non-volatile memory elements 失效
标题翻译：单片机包括非易失性存储元件
公开(公告)号：US5321845A
公开(公告)日：1994-06-14
申请号：US94920
申请日：1993-07-22
申请人： Terumi Sawase , Kouki Noguchi , Hideo Nakamura , Yasushi Akao , Shiro Baba , Yoshimune Hagiwara
发明人： Terumi Sawase , Kouki Noguchi , Hideo Nakamura , Yasushi Akao , Shiro Baba , Yoshimune Hagiwara
IPC分类号： G06F9/24 , G06F15/78 , G06F9/06
CPC分类号： G06F9/24 , G06F15/7814
摘要： A logic circuit built in a single-chip microprocessor is configured of electrically-programmable memory elements, and information is written into the memory elements from outside, whereby the logic circuit having any desired logical functions can be constructed. The writing operation of the memory elements can be executed in a short time, and a user can obtain the single-chip microprocessor having hardware of peculiar prescribed specifications, in a short period.
摘要翻译：内置在单芯片微处理器中的逻辑电路由电可编程存储器元件构成，并且信息从外部写入存储器元件，由此可以构建具有任何期望的逻辑功能的逻辑电路。可以在短时间内执行存储元件的写入操作，并且用户可以在短时间内获得具有特定规定规格的硬件的单片微处理器。

4. 发明授权

US5117488A Microprogram controlled microprocessor having a selectively expandable instruction code length including independent description of operand addressing and a type of operation for an operand by single instruction in a common coding scheme 失效
标题翻译：具有可选择的可扩展指令码长度的微控制微控制器，其中包括独立的操作说明和通用编程方案中的单个操作的操作类型
公开(公告)号：US5117488A
公开(公告)日：1992-05-26
申请号：US265539
申请日：1988-11-01
申请人： Kouki Noguchi , Fumio Tsuchiya , Takashi Tsukamoto , Shigeki Masumura , Hideo Nakamura , Shiro Baba , Yoshimune Hagiwara
发明人： Kouki Noguchi , Fumio Tsuchiya , Takashi Tsukamoto , Shigeki Masumura , Hideo Nakamura , Shiro Baba , Yoshimune Hagiwara
IPC分类号： G06F9/22 , G06F9/26 , G06F9/30
CPC分类号： G06F9/30178 , G06F9/261 , G06F9/30145 , G06F9/30156
摘要： In a microprocessor, a minimum instruction code length is set to a predetermined number of bits (e.g. one byte) length. One feature of the invention is that an instruction set which can selectively expand the instruction code length at a unit of the predetermined number of bits is used. Another feature is that an operand addressing mode and a type of operation for an operand are designated by separate predetermined number of code bits which are coded in a common coding scheme so that an instruction decoder is shared by those codes.

5. 发明授权

US4494195A Microinstruction controlled data processor 失效
标题翻译：微指令控制数据处理器
公开(公告)号：US4494195A
公开(公告)日：1985-01-15
申请号：US444711
申请日：1982-11-26
申请人： Kouki Noguchi , Takashi Tsunehiro , Hideo Nakamura
发明人： Kouki Noguchi , Takashi Tsunehiro , Hideo Nakamura
IPC分类号： G06F9/22 , G06F9/26 , G06F9/28 , G06F9/38
CPC分类号： G06F9/267
摘要： Herein disclosed is a microinstruction controlled data processor in which a microinstruction memory (i.e., an ROM) is driven in each predetermined cycle thereby to generate a plurality of microinstructions in accordance with a page address it receives and in which a general microinstruction contains the page address and the displacement address of the plural preceding microinstructions. One of the plural instructions read out of the ROM is selected upon each read-out operation. The page and displacement addresses in the microinstruction thus selected are set in an address register at the timings for reading out the plural microinstructions. Moreover, a displacement address generator for selecting the plural microinstructions read out of the ROM generates the displacement addresses which are different in dependence upon whether a branch instruction exists in the instructions selected during the same number of cycles as that of the plurality or not and whether the branching operation succeeds or not in case the branch instruction exists.
摘要翻译：这里公开了一种微指令控制数据处理器，其中在每个预定周期中驱动微指令存储器（即，ROM），从而根据其接收的页地址生成多个微指令，并且其中一般微指令包含页面地址以及多个前面的微指令的位移地址。在每次读出操作时选择从ROM读出的多个指令之一。如此选择的微指令中的页面和位移地址在用于读出多个微指令的定时处被设置在地址寄存器中。此外，用于选择从ROM中读出的多个微指令的位移地址发生器产生根据在与多个循环相同的周期期间选择的指令中是否存在分支指令而不同的位移地址，以及是否在分支指令存在的情况下，分支操作成功或不成功。

6. 发明授权

US5428808A Single-chip microcomputer 失效
标题翻译：单片机
公开(公告)号：US5428808A
公开(公告)日：1995-06-27
申请号：US217826
申请日：1994-03-25
申请人： Terumi Sawase , Kouki Noguchi , Hideo Nakamura , Yasushi Akao , Shiro Baba , Yoshimune Hagiwara
发明人： Terumi Sawase , Kouki Noguchi , Hideo Nakamura , Yasushi Akao , Shiro Baba , Yoshimune Hagiwara
IPC分类号： G06F9/24 , G06F15/78 , G06F9/06
CPC分类号： G06F9/24 , G06F15/7814
摘要： A logic circuit built in a single-chip microprocessor is configured of electrically-programmable memory elements, and information is written into the memory elements from outside, whereby the logic circuit having any desired logical functions can be constructed. The writing operation of the memory elements can be executed in a short time, and a user can obtain the single-chip microprocessor having hardware of peculiar prescribed specifications, in a short period.
摘要翻译：内置在单芯片微处理器中的逻辑电路由电可编程存储器元件构成，并且信息从外部写入存储器元件，由此可以构建具有任何期望的逻辑功能的逻辑电路。可以在短时间内执行存储元件的写入操作，并且用户可以在短时间内获得具有特定规定规格的硬件的单片微处理器。

7. 发明授权

US5165086A Microprocessor chip using two-level metal lines technology 失效
标题翻译：微处理器芯片采用二级金属线技术
公开(公告)号：US5165086A
公开(公告)日：1992-11-17
申请号：US527866
申请日：1990-05-24
申请人： Shigehiro Kamejima , Yoshimune Hagiwara , Kouki Noguchi , Minoru Ishii , Tadahiko Nishimukai , Hideo Nakamura , Haruo Koizumi , Hiroyuki Masuda
发明人： Shigehiro Kamejima , Yoshimune Hagiwara , Kouki Noguchi , Minoru Ishii , Tadahiko Nishimukai , Hideo Nakamura , Haruo Koizumi , Hiroyuki Masuda
IPC分类号： H01L27/02
CPC分类号： H01L27/0207
摘要： A microprocessor chip including a ROM portion for storing a microprogram, an execution unit portion for executing an arithmetic operation and random logic circuits disposed between the ROM portion and the execution unit portion. Two-level metal lines technology is used for supplying power for grounding and for providing input/output interconnect lines for the random logic circuits.
摘要翻译：一种微处理器芯片，包括用于存储微程序的ROM部分，用于执行算术运算的执行单元部分和布置在ROM部分和执行单元部分之间的随机逻辑电路。两级金属线技术用于为接地提供电源，并为随机逻辑电路提供输入/输出互连线。

8. 发明授权

US5608881A Microcomputer system for accessing hierarchical buses 失效
标题翻译：用于访问分层总线的微机系统
公开(公告)号：US5608881A
公开(公告)日：1997-03-04
申请号：US143142
申请日：1993-10-29
申请人： Shigeki Masumura , Hideo Nakamura , Kouki Noguchi , Shumpei Kawasaki , Kaoru Fukada , Yasushi Akao
发明人： Shigeki Masumura , Hideo Nakamura , Kouki Noguchi , Shumpei Kawasaki , Kaoru Fukada , Yasushi Akao
IPC分类号： G06F3/06 , G06F13/36 , G06F13/362 , G06F13/00
CPC分类号： G06F13/362
摘要： In a microcomputer system, an access operation is executed in a pipeline mode via buses to which bus masters are connected, and a control of the pipeline execution is performed by a bus controller. Furthermore, an access for delaying this pipeline operation is carried out by low-level of hierarchical buses connected by a buffer and a low-level bus controller.
摘要翻译：在微计算机系统中，通过总线主机连接的总线以管道模式执行访问操作，并且由总线控制器执行流水线执行的控制。此外，用于延迟该流水线操作的访问由通过缓冲器和低级总线控制器连接的低级分层总线来执行。

9. 发明授权

US5784637A Single-chip semiconductor integrated circuit device and microcomputer integrated on a semiconductor chip 失效
标题翻译：集成在半导体芯片上的单片半导体集成电路器件和微计算机
公开(公告)号：US5784637A
公开(公告)日：1998-07-21
申请号：US414157
申请日：1995-03-31
申请人： Terumi Sawase , Kouki Noguchi , Hideo Nakamura , Yasushi Akao , Shiro Baba , Yoshimune Hagiwara
发明人： Terumi Sawase , Kouki Noguchi , Hideo Nakamura , Yasushi Akao , Shiro Baba , Yoshimune Hagiwara
IPC分类号： G06F9/24 , G06F15/78
CPC分类号： G06F9/24 , G06F15/7814
摘要： A semiconductor integrated circuit device formed on a single chip or a microcomputer integrated on a semiconductor chip includes a central processing unit (CPU), an interface circuit (or an input/output port), a bus coupled to the CPU and the interface circuit (or the input/output port) and a variable logic circuit (or a subprocessor). The variable logic circuit (or the subprocessor) includes non-volatile memory elements storing instructions, a control circuit generating control signals in accordance with the stored instructions, and an arithmetic logic unit controlled by the generated control signals. Information can be written into the non-volatile memory elements from outside to construct the variable logic circuit or the subprocessor with any desired logical functions. The wiring operation of the memory elements can be executed in a short time, and a user can thus quickly obtain a single-chip microprocessor or a single-chip semiconductor integrated circuit device having hardware of peculiar prescribed specifications.
摘要翻译：形成在集成在半导体芯片上的单个芯片或微计算机上的半导体集成电路装置包括中央处理单元（CPU），接口电路（或输入/输出端口），耦合到CPU和接口电路的总线或输入/输出端口）和可变逻辑电路（或子处理器）。可变逻辑电路（或子处理器）包括存储指令的非易失性存储器元件，根据存储的指令产生控制信号的控制电路以及由所生成的控制信号控制的算术逻辑单元。可以从外部将信息写入非易失性存储器元件，以任何期望的逻辑功能构建可变逻辑电路或子处理器。存储元件的布线操作可以在短时间内执行，因此用户可以快速获得具有特定规定规格的硬件的单芯片微处理器或单芯片半导体集成电路器件。

10. 发明授权

US4419684A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US4419684A
公开(公告)日：1983-12-06
申请号：US224946
申请日：1981-01-14
申请人： Yoshio Sakai , Hideo Nakamura
发明人： Yoshio Sakai , Hideo Nakamura
IPC分类号： H01L21/822 , H01L21/765 , H01L21/768 , H01L23/522 , H01L27/04 , H01L27/06 , H01L27/088
CPC分类号： H01L27/088 , H01L21/765 , H01L23/5222 , H01L2924/0002
摘要： Well regions of p-type are disposed in a surface region of an n-type Si substrate of a semiconductor integrated circuit. The p-type well regions are arranged in the shape of islands, and various semiconductor elements are formed in the p-type well islands. The substrate surface region between the p-type well islands is filled with a depletion layer, and an interconnection layer is disposed on an insulating film over that body region contained within the depletion layer.
摘要翻译： p型阱区设置在半导体集成电路的n型Si衬底的表面区域中。 p型阱区域形成为岛状，并且在p型阱岛中形成各种半导体元件。 p型阱岛之间的衬底表面区填充有耗尽层，并且在包含在耗尽层内的身体区域上的绝缘膜上布置有互连层。

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