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1. 发明申请

US20110183464A1 DUAL CARRIER FOR JOINING IC DIE OR WAFERS TO TSV WAFERS 有权
标题翻译：双向承载器将晶圆或晶圆加入TSV波形
公开(公告)号：US20110183464A1
公开(公告)日：2011-07-28
申请号：US12694012
申请日：2010-01-26
申请人： Yoshimi Takahashi , Masood Murtuza , Rajiv Dunne , Satyendra Singh Chauhan
发明人： Yoshimi Takahashi , Masood Murtuza , Rajiv Dunne , Satyendra Singh Chauhan
IPC分类号： H01L21/60
CPC分类号： H01L21/6836 , C09J5/06 , C09J2203/326 , C09J2205/302 , H01L21/561 , H01L21/565 , H01L21/76898 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/6834 , H01L2221/68381 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/81001 , H01L2224/81191 , H01L2224/81203 , H01L2224/81801 , H01L2224/83191 , H01L2224/83192 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01043 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/19041 , H01L2924/20105 , H01L2224/81 , H01L2924/00 , H01L2224/05552
摘要： A method of forming stacked electronic articles using a through substrate via (TSV) wafer includes mounting a first carrier wafer to a top side of the TSV wafer using a first adhesive material that has a first debonding temperature. The TSV wafer is thinned from a bottom side of the TSV wafer to form a thinned TSV wafer. A second carrier wafer is mounted to the bottom side of the TSV wafer using a second adhesive material that has a second debonding temperature that is higher as compared to the first debonding temperature. The thinned TSV wafer is heated to a temperature above the first debonding temperature to remove the first carrier wafer from the thinned TSV wafer. At least one singulated IC die is bonded to TSV die formed on the top surface of the thinned TSV wafer to form the stacked electronic article.
摘要翻译：使用贯通基板通孔（TSV）晶片形成堆叠的电子产品的方法包括使用具有第一剥离温度的第一粘合材料将第一载体晶片安装到TSV晶片的顶侧。 TSV晶片从TSV晶片的底侧变薄以形成薄的TSV晶片。使用第二粘合剂材料将第二载体晶片安装到TSV晶片的底侧，第二粘合材料具有与第一脱粘温度相比更高的第二剥离温度。将薄化的TSV晶片加热到高于第一脱粘温度的温度，以从稀薄的TSV晶片去除第一载体晶片。至少一个单片IC芯片被结合到形成在薄化的TSV晶片的顶表面上的TSV模具，以形成堆叠的电子制品。

2. 发明授权

US08017439B2 Dual carrier for joining IC die or wafers to TSV wafers 有权
标题翻译：用于将IC芯片或晶片连接到TSV晶片的双载体
公开(公告)号：US08017439B2
公开(公告)日：2011-09-13
申请号：US12694012
申请日：2010-01-26
申请人： Yoshimi Takahashi , Masood Murtuza , Rajiv Dunne , Satyendra Singh Chauhan
发明人： Yoshimi Takahashi , Masood Murtuza , Rajiv Dunne , Satyendra Singh Chauhan
IPC分类号： H01L21/44
CPC分类号： H01L21/6836 , C09J5/06 , C09J2203/326 , C09J2205/302 , H01L21/561 , H01L21/565 , H01L21/76898 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/6834 , H01L2221/68381 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/81001 , H01L2224/81191 , H01L2224/81203 , H01L2224/81801 , H01L2224/83191 , H01L2224/83192 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01043 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/19041 , H01L2924/20105 , H01L2224/81 , H01L2924/00 , H01L2224/05552
摘要： A method of forming stacked electronic articles using a through substrate via (TSV) wafer includes mounting a first carrier wafer to a top side of the TSV wafer using a first adhesive material that has a first debonding temperature. The TSV wafer is thinned from a bottom side of the TSV wafer to form a thinned TSV wafer. A second carrier wafer is mounted to the bottom side of the TSV wafer using a second adhesive material that has a second debonding temperature that is higher as compared to the first debonding temperature. The thinned TSV wafer is heated to a temperature above the first debonding temperature to remove the first carrier wafer from the thinned TSV wafer. At least one singulated IC die is bonded to TSV die formed on the top surface of the thinned TSV wafer to form the stacked electronic article.
摘要翻译：使用贯通基板通孔（TSV）晶片形成堆叠的电子产品的方法包括使用具有第一剥离温度的第一粘合材料将第一载体晶片安装到TSV晶片的顶侧。 TSV晶片从TSV晶片的底侧变薄以形成薄的TSV晶片。使用第二粘合剂材料将第二载体晶片安装到TSV晶片的底侧，第二粘合材料具有与第一脱粘温度相比更高的第二剥离温度。将薄化的TSV晶片加热到高于第一脱粘温度的温度，以从稀薄的TSV晶片去除第一载体晶片。至少一个单片IC芯片被结合到形成在薄化的TSV晶片的顶表面上的TSV模具，以形成堆叠的电子制品。

3. 发明授权

US07915080B2 Bonding IC die to TSV wafers 有权
标题翻译：将IC芯片连接到TSV晶片
公开(公告)号：US07915080B2
公开(公告)日：2011-03-29
申请号：US12575522
申请日：2009-10-08
申请人： Yoshimi Takahashi , Masood Murtuza , Rajiv Dunne , Satyendra Chauhan
发明人： Yoshimi Takahashi , Masood Murtuza , Rajiv Dunne , Satyendra Chauhan
IPC分类号： H01L21/98
CPC分类号： H01L21/76898 , H01L21/56 , H01L21/6835 , H01L23/3107 , H01L24/02 , H01L24/12 , H01L24/16 , H01L24/27 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L25/50 , H01L2224/0401 , H01L2224/11002 , H01L2224/13009 , H01L2224/13099 , H01L2224/274 , H01L2224/73104 , H01L2224/81203 , H01L2224/81801 , H01L2224/81894 , H01L2224/83191 , H01L2224/94 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/19041 , H01L2924/00 , H01L2224/81
摘要： A method for bonding IC die to TSV wafers includes bonding at least one singulated IC die to respective ones of a plurality of IC die on a TSV wafer that includes a top semiconductor surface and TSV precursors including embedded TSV tips to form a die-wafer stack. The die-wafer stack is thinned beginning from the bottom surface of the TSV wafer to form a thinned die-wafer stack. The thinning includes exposing the embedded TSV tips to provide electrical access thereto from the bottom surface of the TSV wafer. The thinned die-wafer stack can be singulated to form a plurality of thinned die stacks.
摘要翻译：将IC芯片接合到TSV晶片的方法包括将包括顶部半导体表面的TSV晶片上的多个IC管芯中的至少一个分立IC管芯和包括嵌入式TSV引脚的TSV前体结合以形成晶片叠层。晶片堆叠从TSV晶片的底表面开始减薄以形成薄的晶片叠层。减薄包括暴露嵌入式TSV尖端以从TSV晶片的底表面提供对其的电接入。可以将薄化的晶片 - 叠片叠层形成多个薄的晶片叠层。

4. 发明授权

US08431481B2 IC device having low resistance TSV comprising ground connection 有权
标题翻译：具有低电阻TSV的IC器件包括接地连接
公开(公告)号：US08431481B2
公开(公告)日：2013-04-30
申请号：US13444545
申请日：2012-04-11
申请人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
发明人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
IPC分类号： H01L21/4763
CPC分类号： H01L23/49513 , H01L23/481 , H01L23/49575 , H01L24/16 , H01L24/30 , H01L24/33 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/0401 , H01L2224/0557 , H01L2224/05647 , H01L2224/16145 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/29339 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73204 , H01L2224/73207 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/04953 , H01L2924/078 , H01L2924/14 , H01L2924/1461 , H01L2924/30107 , H01L2924/00 , H01L2924/01083 , H01L2924/0665 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/013
摘要： A method of forming a semiconductor device includes an integrated circuit (IC) die which is provided with a substrate with surfaces. At least one through substrate via (TSV) is formed through the substrate to a protruding integral tip that includes sidewalls and a distal end. A metal layer is formed on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. Completing fabrication of at least one functional circuit including at least one ground pad on the top surface of the semiconductor, wherein the ground pad is coupled to said TSV.
摘要翻译：形成半导体器件的方法包括：集成电路（IC）管芯，其具有表面的衬底。至少一个通过衬底通孔（TSV）通过衬底形成为包括侧壁和远端的突出的整体尖端。在IC芯片的底面上形成有金属层，突出整体尖端的侧壁和远端形成。完成至少一个功能电路的制造，该至少一个功能电路包括在半导体的顶表面上的至少一个接地焊盘，其中接地焊盘耦合到所述TSV。

5. 发明申请

US20120202321A1 IC Device Having Low Resistance TSV Comprising Ground Connection 有权
标题翻译：具有低电阻TSV的IC器件包括接地连接
公开(公告)号：US20120202321A1
公开(公告)日：2012-08-09
申请号：US13444545
申请日：2012-04-11
申请人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
发明人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
IPC分类号： H01L21/60 , H01L21/58
CPC分类号： H01L23/49513 , H01L23/481 , H01L23/49575 , H01L24/16 , H01L24/30 , H01L24/33 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/0401 , H01L2224/0557 , H01L2224/05647 , H01L2224/16145 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/29339 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73204 , H01L2224/73207 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/04953 , H01L2924/078 , H01L2924/14 , H01L2924/1461 , H01L2924/30107 , H01L2924/00 , H01L2924/01083 , H01L2924/0665 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/013
摘要： A method of forming a semiconductor device includes an integrated circuit (IC) die which is provided with a substrate with surfaces. At least one through substrate via (TSV) is formed through the substrate to a protruding integral tip that includes sidewalls and a distal end. A metal layer is formed on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. Completing fabrication of at least one functional circuit including at least one ground pad on the top surface of the semiconductor, wherein the ground pad is coupled to said TSV.
摘要翻译：形成半导体器件的方法包括：集成电路（IC）管芯，其具有表面的衬底。至少一个通过衬底通孔（TSV）通过衬底形成为包括侧壁和远端的突出的整体尖端。在IC芯片的底面上形成有金属层，突出整体尖端的侧壁和远端形成。完成至少一个功能电路的制造，该至少一个功能电路包括在半导体的顶表面上的至少一个接地焊盘，其中接地焊盘耦合到所述TSV。

6. 发明授权

US08178976B2 IC device having low resistance TSV comprising ground connection 有权
标题翻译：具有低电阻TSV的IC器件包括接地连接
公开(公告)号：US08178976B2
公开(公告)日：2012-05-15
申请号：US12463086
申请日：2009-05-08
申请人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
发明人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
IPC分类号： H01L23/48
CPC分类号： H01L23/49513 , H01L23/481 , H01L23/49575 , H01L24/16 , H01L24/30 , H01L24/33 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/0401 , H01L2224/0557 , H01L2224/05647 , H01L2224/16145 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/29339 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73204 , H01L2224/73207 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/04953 , H01L2924/078 , H01L2924/14 , H01L2924/1461 , H01L2924/30107 , H01L2924/00 , H01L2924/01083 , H01L2924/0665 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/013
摘要： A semiconductor device includes an integrated circuit (IC) die including a substrate, and at least one through substrate via (TSV) that extends through the substrate to a protruding integral tip that includes sidewalls and a distal end. The protruding integral tip has a tip height between 1 and 50 μm. A metal layer is on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. A semiconductor device can include an IC die that includes TSVs and a package substrate such as a lead-frame, where the IC die includes a metal layer and an electrically conductive die attach adhesive layer, such as a solder filled polymer wherein the solder is arranged in an electrically interconnected network, between the metal layer and the die pad of the lead-frame.
摘要翻译：半导体器件包括包括衬底的集成电路（IC）裸片，以及至少一个穿过衬底延伸穿过衬底通过包括侧壁和远端的突出整体尖端的贯穿衬底通孔（TSV）。突出的整体尖端具有1至50μm的尖端高度。金属层位于IC芯片的底表面，并且突出的整体尖端的侧壁和远端。半导体器件可以包括包括TSV的IC管芯和诸如引线框架的封装衬底，其中IC管芯包括金属层和导电管芯附着粘合剂层，例如焊料填充聚合物，其中焊料布置在电互连网络中，在金属层和引线框架的管芯焊盘之间。

7. 发明授权

US08436475B2 IC device having low resistance TSV comprising ground connection 有权
标题翻译：具有低电阻TSV的IC器件包括接地连接
公开(公告)号：US08436475B2
公开(公告)日：2013-05-07
申请号：US13444508
申请日：2012-04-11
申请人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
发明人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
IPC分类号： H01L23/48
CPC分类号： H01L23/49513 , H01L23/481 , H01L23/49575 , H01L24/16 , H01L24/30 , H01L24/33 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/0401 , H01L2224/0557 , H01L2224/05647 , H01L2224/16145 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/29339 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73204 , H01L2224/73207 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/04953 , H01L2924/078 , H01L2924/14 , H01L2924/1461 , H01L2924/30107 , H01L2924/00 , H01L2924/01083 , H01L2924/0665 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/013
摘要： A semiconductor device includes an integrated circuit (IC) die including a substrate, and a plurality of through substrate via (TSV) that extends through the substrate to a protruding integral tip and which is partially covered with a dielectric liner and partially exposed from the dielectric liner. A metal layer is on the bottom surface of the IC die physically connecting the plurality of TSVs and physically and electrically connected to connecting the first metal protruding tips of TSVs.
摘要翻译：半导体器件包括：集成电路（IC）管芯，其包括衬底;以及多个通过衬底通孔（TSV），其穿过衬底延伸到突出的整体尖端，并且部分地被电介质衬垫覆盖并部分地从电介质暴露衬垫。金属层位于IC芯片的底表面上，物理地连接多个TSV，并物理和电连接到连接TSV的第一金属突出尖端。

8. 发明申请

US20120193814A1 IC Device Having Low Resistance TSV Comprising Ground Connection 有权
标题翻译：具有低电阻TSV的IC器件包括接地连接
公开(公告)号：US20120193814A1
公开(公告)日：2012-08-02
申请号：US13444508
申请日：2012-04-11
申请人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
发明人： Rajiv Dunne , Gary P. Morrison , Satyendra S. Chauhan , Masood Murtuza , Thomas D. Bonifield
IPC分类号： H01L23/48
CPC分类号： H01L23/49513 , H01L23/481 , H01L23/49575 , H01L24/16 , H01L24/30 , H01L24/33 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/0401 , H01L2224/0557 , H01L2224/05647 , H01L2224/16145 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/29339 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73204 , H01L2224/73207 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/04953 , H01L2924/078 , H01L2924/14 , H01L2924/1461 , H01L2924/30107 , H01L2924/00 , H01L2924/01083 , H01L2924/0665 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/013
摘要： A semiconductor device includes an integrated circuit (IC) die including a substrate, and a plurality of through substrate via (TSV) that extends through the substrate to a protruding integral tip and which is partially covered with a dielectric liner and partially exposed from the dielectric liner. A metal layer is on the bottom surface of the IC die die physically connecting the plurality of TSVs and physically and electrically connected to connecting the first metal protruding tips of TSVs.
摘要翻译：半导体器件包括：集成电路（IC）管芯，其包括衬底;以及多个通过衬底通孔（TSV），其穿过衬底延伸到突出的整体尖端，并且部分地被电介质衬垫覆盖并部分地从电介质暴露衬垫。金属层位于IC芯片的底表面上，物理连接多个TSV，并物理和电连接到连接TSV的第一金属突出尖端。

9. 发明授权

US08154134B2 Packaged electronic devices with face-up die having TSV connection to leads and die pad 有权
标题翻译：封装的电子设备具有面向上的裸片，TSV连接到引线和裸片焊盘
公开(公告)号：US08154134B2
公开(公告)日：2012-04-10
申请号：US12463184
申请日：2009-05-08
申请人： Thomas D. Bonifield , Gary P. Morrison , Rajiv Dunne , Satyendra S. Chauhan , Masood Murtuza
发明人： Thomas D. Bonifield , Gary P. Morrison , Rajiv Dunne , Satyendra S. Chauhan , Masood Murtuza
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/495 , H01L23/04
CPC分类号： H01L23/49575 , H01L23/481 , H01L23/49513 , H01L24/12 , H01L24/31 , H01L24/83 , H01L2224/02372 , H01L2224/0401 , H01L2224/13009 , H01L2224/13024 , H01L2224/13025 , H01L2224/13099 , H01L2224/16 , H01L2224/2518 , H01L2224/2929 , H01L2224/29339 , H01L2224/83851 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/19104 , H01L2924/00014 , H01L2924/0665 , H01L2924/00
摘要： A packaged electronic device includes a leadframe including a die pad, a first, second, and third lead pin surrounding the die pad. An IC die is assembled in a face-up configuration on the lead frame. The IC die includes a substrate having an active top surface and a bottom surface, wherein the top surface includes integrated circuitry including an input pad, an output pad, a power supply pad, and a ground pad, and a plurality of through-substrate vias (TSVs) including an electrically conductive filler material and a dielectric liner. The TSVs couple the input pad to the first lead pin, the output pad to the second lead pin, the power supply pad to a third lead pin or a portion of the die pad. A fourth TSV couples pads coupled to the ground node to the die pad or a portion of the die pad for a split die pad.
摘要翻译：封装的电子设备包括引线框架，引线框架包括管芯焊盘，围绕管芯焊盘的第一，第二和第三引脚引脚。在引线框架上以面朝上的配置组装IC芯片。 IC芯片包括具有有源顶表面和底表面的衬底，其中顶表面包括集成电路，其包括输入焊盘，输出焊盘，电源焊盘和接地焊盘，以及多个贯穿衬底通孔（TSV），其包括导电填充材料和电介质衬垫。 TSV将输入焊盘耦合到第一引脚引脚，输出焊盘连接到第二引脚引脚，电源焊盘连接到第三引脚引脚或芯片焊盘的一部分。第四TSV将耦合到接地节点的焊盘耦合到管芯焊盘或用于分离管芯焊盘的芯片焊盘的一部分。

10. 发明授权

US08174276B2 Coaxial four-point probe for low resistance measurements 有权
标题翻译：用于低电阻测量的同轴四点探头
公开(公告)号：US08174276B2
公开(公告)日：2012-05-08
申请号：US12470907
申请日：2009-05-22
申请人： Michael Anthony Lamson , Siva Prakash Gurrum , Rajiv Dunne
发明人： Michael Anthony Lamson , Siva Prakash Gurrum , Rajiv Dunne
IPC分类号： G01R31/02 , G01R1/06
CPC分类号： G01R31/2812 , G01R31/2848 , G01R31/2853
摘要： Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance.
摘要翻译：各种示例性实施例提供用于以高灵敏度测量有效电阻/电阻率的探针，系统和方法。在一个实施例中，测量系统可以包括上探针组和类似的下探针组，其具有夹在其间的样品装置。待测器件（DUT）样品可以夹在样品器件的两个导体之间。每个探针组可以具有同轴配置在电隔离外部电流源探针内部的内部电压感测探针，该探针具有与样品装置的大的接触面积。测量系统还可以包括用于存储电路模拟的计算机可读介质，包括例如用于提取主体通过平面电阻率的有限元模拟和用于DUT的有效电z电阻率的界面电阻率，在某些情况下，微欧姆电阻。

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