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1. 发明授权

US4804560A Method of selectively depositing tungsten upon a semiconductor substrate 失效
标题翻译：在半导体衬底上选择性地沉积钨的方法
公开(公告)号：US4804560A
公开(公告)日：1989-02-14
申请号：US026900
申请日：1987-03-17
申请人： Yoshimi Shioya , Yasushi Oyama , Norihisa Tsuzuki , Mamoru Maeda , Masaaki Ichikawa , Fumitake Mieno , Shin-ichi Inoue , Yasuo Uo-ochi , Akira Tabuchi , Atsuhiro Tsukune , Takuya Watanabe , Takayuki Ohba
发明人： Yoshimi Shioya , Yasushi Oyama , Norihisa Tsuzuki , Mamoru Maeda , Masaaki Ichikawa , Fumitake Mieno , Shin-ichi Inoue , Yasuo Uo-ochi , Akira Tabuchi , Atsuhiro Tsukune , Takuya Watanabe , Takayuki Ohba
IPC分类号： H01L21/205 , C23C16/04 , C23C16/14 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , B05D5/12 , C23C16/00
CPC分类号： H01L21/28562 , H01L21/32051 , H01L21/76879
摘要： A method of selectively depositing tungsten upon a silicon semiconductor substrate. A silicon substrate is coated with a masking film of PSG or SiO.sub.2 that is patterned to provide an opening for forming an electrode or wiring. On a portion of the substrate in the opening, a layer of tungsten having a thickness of approximately 2000 .ANG. is deposited by a CVD method from an atomosphere containing a gaseous mixture of WF.sub.6 and H.sub.2 . During this processing, tungsten nucleuses deposit on the surface of the masking film as well. Before such nucleuses form a film, the deposition processing is discontinued and H.sub.2 gas is fed into the CVD apparatus to produce HF, which etches the surface of the masking film, and thus tungsten nucleuses are removed. The deposition and removal steps are repeated several times until the height of the deposited tungsten and the thickness of the masking film are essentially equal to present a flat surface. Aluminum film is deposited on the flat surface and patterned by lithography. The flat aluminum deposition allows fabrication of accurate and reliable wirings and facilitates production of VLSI of sub-micron order.
摘要翻译：一种在硅半导体衬底上选择性地沉积钨的方法。硅衬底涂覆有被图案化以提供用于形成电极或布线的开口的PSG或SiO 2的掩模膜。在开口中的基板的一部分上，通过CVD法从含有WF6和H2的气体混合物的大气层沉积厚度约为2000的钨层。在该处理中，钨核沉积在掩模膜的表面上也是如此。在这种核形成膜之前，中断沉积处理，并且将H 2气体进料到CVD装置中以产生HF，其蚀刻掩模膜的表面，因此除去钨原子。沉积和去除步骤重复几次，直到沉积的钨的高度和掩模膜的厚度基本上等于呈现平坦表面。铝膜沉积在平坦表面上并通过光刻图案化。扁平铝沉积允许制造准确可靠的布线，并有助于生产亚微米级VLSI。

2. 发明授权

US5609721A Semiconductor device manufacturing apparatus and its cleaning method 失效
标题翻译：半导体装置制造装置及其清洗方法
公开(公告)号：US5609721A
公开(公告)日：1997-03-11
申请号：US367828
申请日：1995-01-03
申请人： Atsuhiro Tsukune , Kiyokatsu Suzuki , Katsuyoshi Matsuura , Fumitake Mieno , Hirokazu Yamanishi
发明人： Atsuhiro Tsukune , Kiyokatsu Suzuki , Katsuyoshi Matsuura , Fumitake Mieno , Hirokazu Yamanishi
IPC分类号： C23C16/44 , C23C16/455 , H01L21/00 , C23C16/00
CPC分类号： C23C16/45561 , C23C16/4405 , C23C16/4412 , C23C16/455 , H01L21/67028 , Y10S438/905
摘要： An apparatus and method for manufacturing a semiconductor device includes a reaction chamber adapted to exhaust gas therefrom, and a cleaning gas supplying system for introducing cleaning gas containing ClF.sub.3 into the reaction chamber, the system having a plurality of gas blowout holes formed in the flow direction of gas at least in the reaction chamber. The reaction chamber may be a tubular chamber, and the cleaning gas supplying system may be a tube extending from one end to the other end of the reaction chamber along the inner wall or the central axis of the reaction chamber, a plurality of through holes being formed in the side wall of the tube. Damages to the inner surface of the reaction chamber of the semiconductor device manufacturing apparatus can be suppressed and a film attached to the inner wall of the reaction chamber can be removed in a short time.
摘要翻译：一种用于制造半导体器件的设备和方法，包括适于从其中排出的反应室和用于将含有ClF 3的清洁气体引入反应室的清洁气体供给系统，该系统具有沿流动方向形成的多个气体吹出孔至少在反应室中。反应室可以是管状室，并且清洁气体供应系统可以是沿着反应室的内壁或中心轴线从反应室的一端延伸到另一端的管，多个通孔是形成在管的侧壁中。能够抑制对半导体装置制造装置的反应室内表面的损伤，能够在短时间内除去附着于反应室内壁的膜。

3. 发明授权

US5233163A Graphite columnar heating body for semiconductor wafer heating 失效
标题翻译：用于半导体晶圆加热的石墨柱状加热体
公开(公告)号：US5233163A
公开(公告)日：1993-08-03
申请号：US725081
申请日：1991-07-03
申请人： Fumitake Mieno , Yuji Furumura , Atsuhiro Tsukune , Hiroshi Miyata
发明人： Fumitake Mieno , Yuji Furumura , Atsuhiro Tsukune , Hiroshi Miyata
IPC分类号： H01L21/205 , C23C16/46 , C30B29/06 , H01L21/00 , H01L21/324
CPC分类号： H01L21/67103
摘要： A heating apparatus for use in heating a substrate comprises an electric heater and a power supply part. The electric heater is made up of an approximately columnar body which is made of graphite, and this columnar body has a top with a flat surface part on which the substrate is placed and a pair of legs which extend downwardly from the flat surface part. The legs are defined by an opening in the columnar body. The power supplying part is coupled to the electric heater and supplies a voltage across the legs of the columnar body so that a current flows from one leg to the other, thereby generating heat at the flat surface part to heat the substrate.
摘要翻译：用于加热基板的加热装置包括电加热器和电源部分。电加热器由石墨制成的近似柱状的主体构成，并且该柱状体具有顶部，其具有放置基板的平坦表面部分和从平坦表面部分向下延伸的一对支腿。腿由柱状体中的开口限定。供电部分耦合到电加热器并且提供横跨柱状体的腿的电压，使得电流从一个腿流向另一个腿，由此在平坦表面部分处产生热量以加热衬底。

4. 发明授权

US5518937A Semiconductor device having a region doped to a level exceeding the solubility limit 失效
标题翻译：具有掺杂到超过溶解度极限的水平的区域的半导体器件
公开(公告)号：US5518937A
公开(公告)日：1996-05-21
申请号：US407254
申请日：1995-03-20
申请人： Yuji Furumura , Fumitake Mieno , Tsutomu Nakazawa , Takashi Eshita , Mamoru Maeda , Tsunenori Yamauchi
发明人： Yuji Furumura , Fumitake Mieno , Tsutomu Nakazawa , Takashi Eshita , Mamoru Maeda , Tsunenori Yamauchi
IPC分类号： H01L29/08 , H01L29/16 , H01L29/36 , H01L29/737 , H01L21/265
CPC分类号： H01L29/0817 , H01L29/1604 , H01L29/36 , H01L29/7375
摘要： A bipolar transistor includes a base region made of silicon crystal doped with a first impurity to a first level so as to establish a first carrier concentration in the base region and an emitter region made of silicon crystal doped with a second impurity to a second level substantially larger than the first level by a predetermined factor so as to establish a second carrier concentration in the emitter region, in which the second impurity exceeds the solubility limit of the second impurity in silicon crystal. The first and second levels are chosen in such a range that a difference in the carrier concentrations between the emitter region and the base region decreases substantially with increasing impurity level in the base region.
摘要翻译：双极晶体管包括由掺杂有第一杂质的硅晶体制成的第一电平的基极区域，以便在基极区域中建立第一载流子浓度，并且将由掺杂有第二杂质的硅晶体制成的发射极区域基本上大于第一电平预定因子，以便在第二杂质超过硅晶体中的第二杂质的溶解度极限的发射极区域中建立第二载流子浓度。第一和第二电平在这样一个范围内选择，使得发射极区域和基极区域之间的载流子浓度的差异随着基极区域中的杂质水平的增加而显着降低。

5. 发明授权

US5264038A Chemical vapor deposition system 失效
标题翻译：化学气相沉积系统
公开(公告)号：US5264038A
公开(公告)日：1993-11-23
申请号：US567224
申请日：1990-08-14
申请人： Tatsushi Hara , Nobuhiro Misawa , Toshiya Suzuki , Takayuki Ohba , Fumitake Mieno , Akio Yamaguchi
发明人： Tatsushi Hara , Nobuhiro Misawa , Toshiya Suzuki , Takayuki Ohba , Fumitake Mieno , Akio Yamaguchi
IPC分类号： C23C16/44 , C23C16/04 , C23C16/448 , C23C16/455 , H01L21/205 , H01L21/28 , H01L21/285 , C23C16/46
CPC分类号： C23C16/45517 , C23C16/04 , C23C16/455 , C23C16/45591
摘要： A chemical vapor deposition (CVD) system for depositing a material selectively on a part of a substrate comprises a reaction chamber in which a CVD process is performed, a substrate holder and substrate heater provided within the reaction chamber, a gas inlet fixture provided on the reaction chamber for introducing one or more CVD source gases into the reaction chamber, and a reactant distribution fixture provided on the gas inlet fixture within the reaction chamber for controlling distribution of the reactant species in the reaction chamber, wherein the reactant distribution fixture defines a subspace surrounding the substrate within the space of the reaction chamber such that the subspace has a dimension, measured in a direction generally perpendicular to the surface of the substrate such that the dimension is at least less than one half of the mean free path of the reactant species realized inside the space of the reaction chamber during the CVD process and such that an opening is formed for communicating the subspace inside the reaction distribution means with the rest of the space of the reaction chamber for freely passing product species formed as a result of the chemical reaction at the surface of the substrate.

6. 发明授权

US5111266A Semiconductor device having a region doped to a level exceeding the solubility limit 失效
标题翻译：具有超过溶解度限制的区域的半导体器件
公开(公告)号：US5111266A
公开(公告)日：1992-05-05
申请号：US714367
申请日：1991-06-12
申请人： Yuji Furumura , Fumitake Mieno , Tsutomu Nakazawa , Takashi Eshita , Mamoru Maeda , Tsunenori Yamauchi
发明人： Yuji Furumura , Fumitake Mieno , Tsutomu Nakazawa , Takashi Eshita , Mamoru Maeda , Tsunenori Yamauchi
IPC分类号： H01L29/08 , H01L29/16 , H01L29/36 , H01L29/737
CPC分类号： H01L29/0817 , H01L29/1604 , H01L29/36 , H01L29/7375
摘要： A bipolar transistor includes a base region made of silicon crystal doped with a first impurity to a first level so as to establish a first carrier concentration in the base region and an emitter region made of silicon crystal doped with a second impurity to a second level substantially larger than the first level by a predetermined factor so as to establish a second carrier concentration in the emitter region, in which the second impurity exceeds the solubility limit of the second impurity in silicon crystal. The first and second levels are chosen in such a range that a difference in the carrier concentrations between the emitter region and the base region decreases substantially with increasing impurity level in the base region.

7. 发明授权

US5270224A Method of manufacturing a semiconductor device having a region doped to a level exceeding the solubility limit 失效
标题翻译：制造具有掺杂到超过溶解度极限的水平的区域的半导体器件的方法
公开(公告)号：US5270224A
公开(公告)日：1993-12-14
申请号：US822232
申请日：1992-01-17
申请人： Yuji Furumura , Fumitake Mieno , Tsutomu Nakazawa , Takashi Eshita , Mamoru Maeda , Tsunenori Yamauchi
发明人： Yuji Furumura , Fumitake Mieno , Tsutomu Nakazawa , Takashi Eshita , Mamoru Maeda , Tsunenori Yamauchi
IPC分类号： H01L29/08 , H01L29/16 , H01L29/36 , H01L29/737 , H01L21/265
CPC分类号： H01L29/7375 , H01L29/0817 , H01L29/1604 , H01L29/36 , Y10S148/123 , Y10S148/124 , Y10S148/155
摘要： A bipolar transistor includes a base region made of silicon crystal doped with a first impurity to a first level so as to establish a first carrier concentration in the base region and an emitter region made of silicon crystal doped with a second impurity to a second level substantially larger than the first level by a predetermined factor so as to establish a second carrier concentration in the emitter region, in which the second impurity exceeds the solubility limit of the second impurity in silicon crystal. The first and second levels are chosen in such a range that a difference in the carrier concentrations between the emitter region and the base region decreases substantially with increasing impurity level in the base region.
摘要翻译：双极晶体管包括由掺杂有第一杂质的硅晶体制成的第一电平的基极区域，以便在基极区域中建立第一载流子浓度，并且将由掺杂有第二杂质的硅晶体制成的发射极区域基本上大于第一电平预定因子，以便在第二杂质超过硅晶体中的第二杂质的溶解度极限的发射极区域中建立第二载流子浓度。第一和第二电平在这样一个范围内选择，使得发射极区域和基极区域之间的载流子浓度的差异随着基极区域中的杂质水平的增加而显着降低。

8. 发明授权

US4876219A Method of forming a heteroepitaxial semiconductor thin film using amorphous buffer layers 失效
标题翻译：使用非晶缓冲层形成异质外延半导体薄膜的方法
公开(公告)号：US4876219A
公开(公告)日：1989-10-24
申请号：US318638
申请日：1989-03-03
申请人： Takashi Eshita , Fumitake Mieno , Yuji Furumura , Takuya Watanabe
发明人： Takashi Eshita , Fumitake Mieno , Yuji Furumura , Takuya Watanabe
IPC分类号： H01L21/20 , H01L21/205
CPC分类号： H01L21/0262 , H01L21/02381 , H01L21/02433 , H01L21/02463 , H01L21/02502 , H01L21/02507 , H01L21/02546 , H01L21/02658 , Y10S148/025 , Y10S148/072 , Y10S148/097 , Y10S148/154 , Y10S148/169 , Y10S438/933
摘要： A method of forming a semiconductor thin layer on a silicon substrate comprising the steps of depositing a first amorphous layer of a compound semiconductor (e.g., GaAs) on the silicon substrate, and growing a first epitaxial layer of the compound semiconductor on the amorphous layer, characterized in that the method comprises the steps of: after the epitaxial growth step, depositing a second amorphous layer of the compound semiconductor on the first epitaxial layer, and growing a second epitaxial layer of the compound semiconductor on the second amorphous layer. The obtained GaAs/Si substrate has a reduced dislocation density.

9. 发明授权

US08513079B2 TFT SAS memory cell structures 有权
标题翻译： TFT SAS存储单元结构
公开(公告)号：US08513079B2
公开(公告)日：2013-08-20
申请号：US12259144
申请日：2008-10-27
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L29/4234 , H01L29/517 , H01L29/66757 , H01L29/66833 , H01L29/792
摘要： A device having thin-film transistor (TFT) silicon-aluminum oxide-silicon (SAS) memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P− polysilicon layer overlying the co-planar surface, an aluminum oxide layer overlying the P− polysilicon layer; and at least one control gate overlying the aluminum oxide layer. In a specific embodiment, the control gate is made of highly doped P+ polysilicon. A method for making the TFT SAS memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.
摘要翻译：提供一种具有薄膜晶体管（TFT）硅 - 氧化铝 - 硅（SAS）存储单元结构的器件。该器件包括衬底，衬底上的电介质层，以及嵌入电介质层中的一个或多个源极或漏极区域。介电层与第一表面相关联。所述一个或多个源区或漏区中的每一个包括在导电层上的扩散阻挡层上的N +多晶硅层。 N +多晶硅层具有与第一表面基本共面的第二表面。另外，该器件包括覆盖共面表面的P-多晶硅层，覆盖在P-多晶硅层上的氧化铝层; 以及覆盖氧化铝层的至少一个控制栅极。在具体实施例中，控制栅由高掺杂P +多晶硅制成。提供了用于制造TFT SAS存储单元结构的方法，并且可以重复三维地集成结构。

10. 发明授权

US08415218B2 Atomic layer deposition epitaxial silicon growth for TFT flash memory cell 有权
标题翻译：用于TFT闪存单元的原子层沉积外延硅生长
公开(公告)号：US08415218B2
公开(公告)日：2013-04-09
申请号：US12259128
申请日：2008-10-27
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： H01L21/336 , H01L21/20 , H01L21/36 , H01L21/00 , C23C16/24 , H01L29/06 , H01L47/02 , H01L29/04 , H01L29/15 , H01L31/036 , H01L29/80 , H01L29/76 , H01L29/788 , H01L21/70
CPC分类号： H01L21/02381 , H01L21/02488 , H01L21/02499 , H01L21/02532 , H01L21/0262 , H01L21/28273 , H01L27/11521 , H01L29/66825 , H01L29/78672
摘要： A method of growing an epitaxial silicon layer is provided. The method comprising providing a substrate including an oxygen-terminated silicon surface and forming a first hydrogen-terminated silicon surface on the oxygen-terminated silicon surface. Additionally, the method includes forming a second hydrogen-terminated silicon surface on the first hydrogen-terminated silicon surface through atomic-layer deposition (ALD) epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. The second hydrogen-terminated silicon surface is capable of being added one or more layer of silicon through ALD epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. In one embodiment, the method is applied for making devices with thin-film transistor (TFT) floating gate memory cell structures which is capable for three-dimensional integration.
摘要翻译：提供了生长外延硅层的方法。该方法包括提供包含氧封端的硅表面的衬底，并在氧封端的硅表面上形成第一个氢封端的硅表面。此外，该方法包括通过原子层沉积（ALD）外延从由Ar流和闪光灯退火辅助的SiH 4热裂解基团连续形成在第一氢封端硅表面上的第二氢封端硅表面。第二个氢封端的硅表面能够连续地由Ar流和闪光灯退火辅助的SiH 4热裂解基团通过ALD外延添加一层或多层硅。在一个实施例中，该方法被应用于制造具有能够进行三维集成的薄膜晶体管（TFT）浮动栅极存储单元结构的器件。

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