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1. 发明授权

US5444662A Dynamic random access memory with bit line equalizing means 失效
标题翻译：具有位线均衡装置的动态随机存取存储器
公开(公告)号：US5444662A
公开(公告)日：1995-08-22
申请号：US257450
申请日：1994-06-08
申请人： Takayuki Tanaka , Yoshimasa Sekino , Yoshihiro Murashima , Yasuhiro Tokunaga , Joji Ueno , Takeru Yonaga
发明人： Takayuki Tanaka , Yoshimasa Sekino , Yoshihiro Murashima , Yasuhiro Tokunaga , Joji Ueno , Takeru Yonaga
IPC分类号： G11C11/409 , G11C11/4094 , G11C7/00
CPC分类号： G11C11/4094
摘要： A dynamic random access memory of the complementary MOS transistor type has memory cells connected between complementary bit lines on one side of a pair of transfer gates and a sense amplifier connected to nodes on the other side of the transfer gates, so that the sense amplifier can be connected to the bit lines and memory cells through the pair of transfer gates. A sense amplifier equalizing circuit and a bit line equalizing circuit are provided on opposite sides of the transfer gates so that the potentials on the bit lines can be equalized independently of equalization of the potentials on the nodes. Accordingly, there is no delay in the equalization due to the transfer gates connecting the nodes to the bit lines. According to another aspect of the invention, the transfer gates each include a pair of MOSFET transistors connected to each other in parallel, wherein one transistor of each pair of MOSFET transistors is an n-channel MOSFET transistor and the other transistor of each pair of MOSFET transistors is a p-channel MOSFET transistor. By, for example, connecting the gate of the NMOS transistor of each transfer to the power source and connecting the gate of each PMOS transistor to the ground, it is possible to prevent erroneous operation of the DRAM from a drop in the gate potential.
摘要翻译：互补MOS晶体管类型的动态随机存取存储器具有连接在一对传输门的一侧上的互补位线和连接到传输门的另一侧上的节点的读出放大器之间的存储单元，使得读出放大器可以通过一对传输门连接到位线和存储单元。感测放大器均衡电路和位线均衡电路设置在传输门的相对侧上，使得可以独立于节点上的电位的均衡来均衡位线上的电位。因此，由于将节点连接到位线的传输门，所以均衡没有延迟。根据本发明的另一方面，传输门每个包括彼此并联连接的一对MOSFET晶体管，其中每对MOSFET晶体管中的一个晶体管是n沟道MOSFET晶体管，并且每对MOSFET的另一个晶体管晶体管是一个p沟道MOSFET晶体管。例如，通过将每个传输的NMOS晶体管的栅极连接到电源并将每个PMOS晶体管的栅极连接到地，可以防止DRAM的错误操作从栅极电位的下降。

2. 发明授权

US5148401A DRAM with split word lines 失效
标题翻译： DRAM分割字线
公开(公告)号：US5148401A
公开(公告)日：1992-09-15
申请号：US762548
申请日：1991-09-18
申请人： Yoshimasa Sekino , Yoshihiro Murashima
发明人： Yoshimasa Sekino , Yoshihiro Murashima
IPC分类号： G11C8/14 , G11C11/408
CPC分类号： G11C11/408 , G11C8/14
摘要： In a dynamic random access memory comprising first and second memory cell arrays, and a plurality of word lines, each split into two sections extending through the first and the second memory cell arrays, respectively, word line drive circuits are divided into three blocks. The first block is disposed between the inner sides of the memory cell arrays and connected to the inner ends of the alternate word line sections. The second and the third blocks are disposed adjacent to the outer sides of the memory cell arrays and are connected to the outer ends of the intervening word line sections. Because the word line drive circuits for the respective word lines are disposed on both sides of each memory cell array, alternately, the area for the word line drive circuit for each word line can extend twice the pitch of the word lines. Thus, the pitch of the word lines can be reduced, or the size of the word line drive transistors can be increased, enabling a higher degree of integration.
摘要翻译：在包括第一和第二存储单元阵列以及多个字线的动态随机存取存储器中，每个字线分别分别延伸穿过第一和第二存储单元阵列的两个部分，字线驱动电路被分成三个块。第一块布置在存储单元阵列的内侧之间并连接到备用字线段的内端。第二和第三块被布置成与存储单元阵列的外侧相邻并且连接到中间字线部分的外端。由于用于各字线的字线驱动电路设置在每个存储单元阵列的两侧，交替地，用于每个字线的字线驱动电路的区域可以延长字线间距的两倍。因此，可以减少字线的间距，或者可以增加字线驱动晶体管的尺寸，从而能够实现更高的集成度。

3. 发明授权

US5258950A Semiconductor memory device 失效
公开(公告)号：US5258950A
公开(公告)日：1993-11-02
申请号：US747660
申请日：1991-08-21
申请人： Yoshihiro Murashima , Yoshimasa Sekino
发明人： Yoshihiro Murashima , Yoshimasa Sekino
IPC分类号： G11C11/417 , G11C5/14 , G11C11/407 , G11C11/4074 , G11C11/409 , G11C11/419 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , G11C11/40
CPC分类号： G11C11/4074 , G11C5/147
摘要： In a semiconductor memory device having memory cells (21.sub.i, 21.sub.i+1) disposed at intersections of bit lines (BL, BL) and word lines (WL.sub.i, WL.sub.i+1) and operating on an internal power source voltage (V.sub.D) which is lower than an external power source voltage for the memory device, sense amplifiers (41) are activated by a voltage on a drive common node (NS), and a comparator (110) is activated by the control signal (PAS) and compares the voltage on the common node (PS) with the internal power source voltage (V.sub.D). The comparator has an output which is in a first state when the common node (PS) voltage is not higher than the reference voltage (V.sub.R) and which is in a second state when the common node (PS) voltage exceeds the reference voltage (V.sub.R). A latch circuit (120) is turned from a first state to a second state when the control signal (PAS) is turned active, thereby to activate the comparator (110) and a power source supply circuit (130, 132) which then supplies a drive voltage to the common node (PS). The latch circuit is turned from the first state to the second state when the output of the comparator (110) is turned to the second state. The latch circuit deactivates the comparator (110) when it is turned to the first state.

4. 发明授权

US5260903A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5260903A
公开(公告)日：1993-11-09
申请号：US834374
申请日：1992-02-12
申请人： Junichi Suyama , Yoshihiro Murashima
发明人： Junichi Suyama , Yoshihiro Murashima
IPC分类号： G11C11/401 , G11C7/10 , G11C11/409 , G11C7/00
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106
摘要： A semiconductor memory device provided that first data is read out from a first memory cell within a first readout period; and second data is read out from the second memory cell within a second readout period; wherein an amplifier circuit receiving the first and second data, outputting first data signals having first electric potential level corresponding to the first and second data and outputting second data signal having second electric potential level; control circuit, in response to an external control signal, generating a first control signal in each of the first and second readout periods, the first control signal indicating first logic level during an enabling period of time within each of the first and second readout periods, otherwise the first control signal indicating second logic level; a first latch circuit latching the first data signals in the respective first and second readout periods and outputting a first latched data signal at the time of the first control signal indicating the first logic level; a second latch circuit latching the second data signals in the respective first and second readout periods and outputting a second latched data signal at the time of the first control signal indicating the first logic level; and a reset circuit placing the first and second latch circuit in an initial status after the first control signal is transferred from the first logic level to the second logic level in the first readout period and before the first control signal is transferred from the second logic level to the first logic level in the second readout period.

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