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1. 发明授权

US5444662A Dynamic random access memory with bit line equalizing means 失效
标题翻译：具有位线均衡装置的动态随机存取存储器
公开(公告)号：US5444662A
公开(公告)日：1995-08-22
申请号：US257450
申请日：1994-06-08
申请人： Takayuki Tanaka , Yoshimasa Sekino , Yoshihiro Murashima , Yasuhiro Tokunaga , Joji Ueno , Takeru Yonaga
发明人： Takayuki Tanaka , Yoshimasa Sekino , Yoshihiro Murashima , Yasuhiro Tokunaga , Joji Ueno , Takeru Yonaga
IPC分类号： G11C11/409 , G11C11/4094 , G11C7/00
CPC分类号： G11C11/4094
摘要： A dynamic random access memory of the complementary MOS transistor type has memory cells connected between complementary bit lines on one side of a pair of transfer gates and a sense amplifier connected to nodes on the other side of the transfer gates, so that the sense amplifier can be connected to the bit lines and memory cells through the pair of transfer gates. A sense amplifier equalizing circuit and a bit line equalizing circuit are provided on opposite sides of the transfer gates so that the potentials on the bit lines can be equalized independently of equalization of the potentials on the nodes. Accordingly, there is no delay in the equalization due to the transfer gates connecting the nodes to the bit lines. According to another aspect of the invention, the transfer gates each include a pair of MOSFET transistors connected to each other in parallel, wherein one transistor of each pair of MOSFET transistors is an n-channel MOSFET transistor and the other transistor of each pair of MOSFET transistors is a p-channel MOSFET transistor. By, for example, connecting the gate of the NMOS transistor of each transfer to the power source and connecting the gate of each PMOS transistor to the ground, it is possible to prevent erroneous operation of the DRAM from a drop in the gate potential.
摘要翻译：互补MOS晶体管类型的动态随机存取存储器具有连接在一对传输门的一侧上的互补位线和连接到传输门的另一侧上的节点的读出放大器之间的存储单元，使得读出放大器可以通过一对传输门连接到位线和存储单元。感测放大器均衡电路和位线均衡电路设置在传输门的相对侧上，使得可以独立于节点上的电位的均衡来均衡位线上的电位。因此，由于将节点连接到位线的传输门，所以均衡没有延迟。根据本发明的另一方面，传输门每个包括彼此并联连接的一对MOSFET晶体管，其中每对MOSFET晶体管中的一个晶体管是n沟道MOSFET晶体管，并且每对MOSFET的另一个晶体管晶体管是一个p沟道MOSFET晶体管。例如，通过将每个传输的NMOS晶体管的栅极连接到电源并将每个PMOS晶体管的栅极连接到地，可以防止DRAM的错误操作从栅极电位的下降。

2. 发明授权

US5258950A Semiconductor memory device 失效
公开(公告)号：US5258950A
公开(公告)日：1993-11-02
申请号：US747660
申请日：1991-08-21
申请人： Yoshihiro Murashima , Yoshimasa Sekino
发明人： Yoshihiro Murashima , Yoshimasa Sekino
IPC分类号： G11C11/417 , G11C5/14 , G11C11/407 , G11C11/4074 , G11C11/409 , G11C11/419 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , G11C11/40
CPC分类号： G11C11/4074 , G11C5/147
摘要： In a semiconductor memory device having memory cells (21.sub.i, 21.sub.i+1) disposed at intersections of bit lines (BL, BL) and word lines (WL.sub.i, WL.sub.i+1) and operating on an internal power source voltage (V.sub.D) which is lower than an external power source voltage for the memory device, sense amplifiers (41) are activated by a voltage on a drive common node (NS), and a comparator (110) is activated by the control signal (PAS) and compares the voltage on the common node (PS) with the internal power source voltage (V.sub.D). The comparator has an output which is in a first state when the common node (PS) voltage is not higher than the reference voltage (V.sub.R) and which is in a second state when the common node (PS) voltage exceeds the reference voltage (V.sub.R). A latch circuit (120) is turned from a first state to a second state when the control signal (PAS) is turned active, thereby to activate the comparator (110) and a power source supply circuit (130, 132) which then supplies a drive voltage to the common node (PS). The latch circuit is turned from the first state to the second state when the output of the comparator (110) is turned to the second state. The latch circuit deactivates the comparator (110) when it is turned to the first state.

3. 发明授权

US5148401A DRAM with split word lines 失效
标题翻译： DRAM分割字线
公开(公告)号：US5148401A
公开(公告)日：1992-09-15
申请号：US762548
申请日：1991-09-18
申请人： Yoshimasa Sekino , Yoshihiro Murashima
发明人： Yoshimasa Sekino , Yoshihiro Murashima
IPC分类号： G11C8/14 , G11C11/408
CPC分类号： G11C11/408 , G11C8/14
摘要： In a dynamic random access memory comprising first and second memory cell arrays, and a plurality of word lines, each split into two sections extending through the first and the second memory cell arrays, respectively, word line drive circuits are divided into three blocks. The first block is disposed between the inner sides of the memory cell arrays and connected to the inner ends of the alternate word line sections. The second and the third blocks are disposed adjacent to the outer sides of the memory cell arrays and are connected to the outer ends of the intervening word line sections. Because the word line drive circuits for the respective word lines are disposed on both sides of each memory cell array, alternately, the area for the word line drive circuit for each word line can extend twice the pitch of the word lines. Thus, the pitch of the word lines can be reduced, or the size of the word line drive transistors can be increased, enabling a higher degree of integration.
摘要翻译：在包括第一和第二存储单元阵列以及多个字线的动态随机存取存储器中，每个字线分别分别延伸穿过第一和第二存储单元阵列的两个部分，字线驱动电路被分成三个块。第一块布置在存储单元阵列的内侧之间并连接到备用字线段的内端。第二和第三块被布置成与存储单元阵列的外侧相邻并且连接到中间字线部分的外端。由于用于各字线的字线驱动电路设置在每个存储单元阵列的两侧，交替地，用于每个字线的字线驱动电路的区域可以延长字线间距的两倍。因此，可以减少字线的间距，或者可以增加字线驱动晶体管的尺寸，从而能够实现更高的集成度。

4. 发明授权

US06066973A Semiconductor integrated circuit having input circuit 失效
标题翻译：具有输入电路的半导体集成电路
公开(公告)号：US06066973A
公开(公告)日：2000-05-23
申请号：US50461
申请日：1998-03-31
申请人： Yoshimasa Sekino , Katuaki Matui
发明人： Yoshimasa Sekino , Katuaki Matui
IPC分类号： H03K19/0185 , H03K5/1252 , H03K19/003 , H03K19/0175 , H03K5/00 , H03K3/01
CPC分类号： H03K5/1252 , H03K19/00361
摘要： An input circuit is made up of an external signal input portion which inputs an external signal, a voltage level converting circuit which has an input terminal for inputting a signal from the external signal input circuit and which has an output terminal for outputng the signal to the internal circuit after a voltage level was converted, a first power supply terminal which has a first potential for driving the voltage level converting circuit, a second power supply terminal which has a second potential for driving the voltage level converting circuit, and a noise control portion which couples to the input terminal of the voltage level converting circuit, which controls a noise from the first power supply terminal and/or the second power supply terminal, and which has a first capacitor. Accordingly, the input circuit could be applied the stable signal to the internal circuit.
摘要翻译：输入电路由输入外部信号的外部信号输入部分构成，电压电平转换电路具有用于输入来自外部信号输入电路的信号的输入端子，并具有输出端子，用于将信号输出到转换了电压电平后的内部电路，具有用于驱动电压电平转换电路的第一电位的第一电源端子，具有用于驱动电压电平转换电路的第二电位的第二电源端子和噪声控制部分其耦合到电压电平转换电路的输入端子，其控制来自第一电源端子和/或第二电源端子的噪声，并且具有第一电容器。因此，输入电路可以将稳定信号施加到内部电路。

5. 发明授权

US06392940B1 Semiconductor memory circuit 有权
公开(公告)号：US06392940B1
公开(公告)日：2002-05-21
申请号：US09741888
申请日：2000-12-22
申请人： Nobuyuki Endo , Yoshimasa Sekino , Hitoshi Yamada
发明人： Nobuyuki Endo , Yoshimasa Sekino , Hitoshi Yamada
IPC分类号： G11C700
摘要： A memory circuit includes a plurality of word lines connected to a plurality of memory cells, a plurality of row address decode circuits having address input terminals, a first wafer burn-in signal terminal, and a second wafer burn-in signal terminal. The row address decode circuits activate all of the word lines when the first wafer burn-in signal and the second wafer burn-in signal are in an enable state. On the other hand, the row address decode circuits activate a subset of the word lines when the second wafer burn-in signal is in the enable state.

6. 发明授权

US6134159A Semiconductor memory and redundant circuit 有权
标题翻译：半导体存储器和冗余电路
公开(公告)号：US6134159A
公开(公告)日：2000-10-17
申请号：US379721
申请日：1999-08-24
申请人： Yoshimasa Sekino
发明人： Yoshimasa Sekino
IPC分类号： G11C7/10 , G11C29/00 , G11C7/00
CPC分类号： G11C29/846 , G11C7/1006
摘要： A semiconductor memory includes a memory array; data buses connected to the memory array; a plurality of data transmission circuits connected to the data buses one by one; and a buffer circuit connected to an outside device. The memory further includes a gate circuit arranged between the data transmission circuits and the buffer circuit; and a fuse connected to the gate circuit. The data transmission circuits are selectively connected to the buffer circuit by controlling the fuse and the gate circuit, so that a defective element is replaced with a normal element.
摘要翻译：半导体存储器包括存储器阵列; 连接到存储器阵列的数据总线; 多个数据传输电路逐个连接到数据总线; 以及连接到外部装置的缓冲电路。存储器还包括布置在数据传输电路和缓冲电路之间的门电路; 以及连接到门电路的保险丝。数据传输电路通过控制熔丝和栅极电路选择性地连接到缓冲电路，从而将故障元件替换为普通元件。

7. 发明申请

US20060028253A1 Power-on reset circuit 审中-公开
公开(公告)号：US20060028253A1
公开(公告)日：2006-02-09
申请号：US11245246
申请日：2005-10-07
申请人： Yoshimasa Sekino , Shoji Kitazawa
发明人： Yoshimasa Sekino , Shoji Kitazawa
IPC分类号： H03L7/00
CPC分类号： H03K17/223
摘要： A power-on reset circuit is capable of outputting a normal reset signal despite slow rise of power supply voltage. A node is interposed between a MOS capacitor including a PMOS with its drain and source connected in common and an NMOS having its gate fixedly connected to a ground potential. The node is connected to a ground potential via the NMOS and also to a power supply line via the MOS capacitor. Therefore, even when the power supply voltage rises slowly after power is turned on, the potential of the node rises substantially at the same rate as the power supply voltage. After the power supply voltage reaches a predetermined power supply potential, the potential of the node is gradually lowered due to an off leakage current through the NMOS. The node is connected with an inverter operating according to the power supply voltage. When the potential of the node decreases below ½ of the power supply voltage, the reset signal outputted from the inverter goes to the H level.

8. 发明授权

US06982577B2 Power-on reset circuit 失效
标题翻译：上电复位电路
公开(公告)号：US06982577B2
公开(公告)日：2006-01-03
申请号：US10811836
申请日：2004-03-30
申请人： Yoshimasa Sekino , Shoji Kitazawa
发明人： Yoshimasa Sekino , Shoji Kitazawa
IPC分类号： H03L17/22
CPC分类号： H03K17/223
摘要： A power-on reset circuit is capable of outputting a normal reset signal despite slow rise of power supply voltage. A node is interposed between a MOS capacitor including a PMOS with its drain and source connected in common and an NMOS having its gate fixedly connected to a ground potential. The node is connected to a ground potential via the NMOS and also to a power supply line via the MOS capacitor. Therefore, even when the power supply voltage rises slowly after power is turned on, the potential of the node rises substantially at the same rate as the power supply voltage. After the power supply voltage reaches a predetermined power supply potential, the potential of the node is gradually lowered due to an off leakage current through the NMOS. The node is connected with an inverter operating according to the power supply voltage. When the potential of the node decreases below ½ of the power supply voltage, the reset signal outputted from the inverter goes to the H level.
摘要翻译：尽管电源电压缓慢上升，上电复位电路仍可输出正常复位信号。节点被插入在包括PMOS的MOS电容器，其漏极和源极连接在一起，并且NMOS的栅极固定地连接到地电位。节点通过NMOS连接到地电位，并通过MOS电容连接到电源线。因此，即使电源电源接通后电源电压缓慢上升，节点的电位也以与电源电压相同的速度大幅上升。在电源电压达到预定的电源电位之后，由于通过NMOS的漏电流而使节点的电位逐渐降低。节点与根据电源电压工作的逆变器连接。当节点电位降低到电源电压的1/2以下时，从变频器输出的复位信号变为H电平。

9. 发明授权

US06975164B1 Method and device for generating constant voltage 失效
标题翻译：用于产生恒定电压的方法和装置
公开(公告)号：US06975164B1
公开(公告)日：2005-12-13
申请号：US09014401
申请日：1998-01-27
申请人： Katsuaki Matsui , Yoshimasa Sekino
发明人： Katsuaki Matsui , Yoshimasa Sekino
IPC分类号： G05F1/56 , G05F1/10 , G05F1/565 , G11C5/14 , G11C11/4074 , G11C11/4099
CPC分类号： G05F1/565 , G11C5/147 , G11C11/4074 , G11C11/4099
摘要： In order to generate a constant voltage, a reference voltage is generated. Short wave noises are cut off from the reference voltage. A control signal is generated based on the reference voltage and an output voltage. The output voltage is controlled in response to the control signal to provide a constant output voltage.
摘要翻译：为了产生恒定电压，产生参考电压。短波噪声与参考电压相切。基于参考电压和输出电压产生控制信号。响应于控制信号控制输出电压以提供恒定的输出电压。

10. 发明授权

US06903956B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06903956B2
公开(公告)日：2005-06-07
申请号：US10670220
申请日：2003-09-26
申请人： Yoshimasa Sekino
发明人： Yoshimasa Sekino
IPC分类号： G11C8/12 , G11C5/06
CPC分类号： G11C8/12
摘要： One semiconductor memory device according to the invention comprises a plurality of memory blocks, signal lines respectively connected to the plurality of memory blocks, and a control circuit connected to the signal lines, and the control circuit includes selection signal generator circuits for generating selection signals for selecting one memory block of the plurality of memory blocks by externally input address signals and for outputting the selection signals to the signal lines, and the lengths of the signal lines from the selection signal generator circuits to the respective memory blocks are longer in proportion to distances from the control circuit to the memory blocks. Thereby, parasitic load capacitances of the signal lines connected to the respective memory blocks in the wiring direction can be reduced, and the semiconductor memory device that operates with lower current consumption can be provided.
摘要翻译：根据本发明的一个半导体存储器件包括多个存储块，分别连接到多个存储块的信号线和连接到信号线的控制电路，并且控制电路包括用于产生选择信号的选择信号发生器电路通过外部输入的地址信号选择多个存储块的一个存储块，并将选择信号输出到信号线，并且从选择信号发生器电路到各个存储块的信号线的长度与距离成正比从控制电路到存储器块。由此，可以减少连接到各个存储块的布线方向的信号线的寄生负载电容，并且可以提供以较低的电流消耗工作的半导体存储器件。

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