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1. 发明授权

US5260903A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5260903A
公开(公告)日：1993-11-09
申请号：US834374
申请日：1992-02-12
申请人： Junichi Suyama , Yoshihiro Murashima
发明人： Junichi Suyama , Yoshihiro Murashima
IPC分类号： G11C11/401 , G11C7/10 , G11C11/409 , G11C7/00
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106
摘要： A semiconductor memory device provided that first data is read out from a first memory cell within a first readout period; and second data is read out from the second memory cell within a second readout period; wherein an amplifier circuit receiving the first and second data, outputting first data signals having first electric potential level corresponding to the first and second data and outputting second data signal having second electric potential level; control circuit, in response to an external control signal, generating a first control signal in each of the first and second readout periods, the first control signal indicating first logic level during an enabling period of time within each of the first and second readout periods, otherwise the first control signal indicating second logic level; a first latch circuit latching the first data signals in the respective first and second readout periods and outputting a first latched data signal at the time of the first control signal indicating the first logic level; a second latch circuit latching the second data signals in the respective first and second readout periods and outputting a second latched data signal at the time of the first control signal indicating the first logic level; and a reset circuit placing the first and second latch circuit in an initial status after the first control signal is transferred from the first logic level to the second logic level in the first readout period and before the first control signal is transferred from the second logic level to the first logic level in the second readout period.

2. 发明授权

US06501303B1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US06501303B1
公开(公告)日：2002-12-31
申请号：US09659573
申请日：2000-09-11
申请人： Junichi Suyama
发明人： Junichi Suyama
IPC分类号： H03K522
CPC分类号： H03K17/302
摘要： A determining circuit comprises an input section having a P-channel type MOS transistor applied with a voltage VT set based on a reference voltage applied to a gate electrode and a voltage according to a voltage of a terminal applied to a source electrode, and an output section with a voltage level that changes according to an output from a drain electrode of a P-channel-type MOS transistor of a voltage level that changes according to a further voltage. With this configuration, the determining circuit for determining switching over to a prescribed mode can be implemented which is not influenced by fluctuations in process factors by using the voltage outputted from the output section.
摘要翻译：一个确定电路包括一个输入部分，该输入部分具有一个P沟道型MOS晶体管，该P沟道型MOS晶体管施加一个基于施加到栅电极的参考电压而设置的电压VT，以及一个根据施加到源极的端子电压的电压，其电压电平根据根据另外的电压而变化的电压电平的P沟道型MOS晶体管的漏电极的输出而变化。利用这种配置，可以实现用于确定切换到规定模式的确定电路，其不受通过使用从输出部分输出的电压的处理因素的波动的影响。

3. 发明授权

US5777492A Address transition detector circuit 失效
标题翻译：地址转换检测电路
公开(公告)号：US5777492A
公开(公告)日：1998-07-07
申请号：US664546
申请日：1996-06-17
申请人： Junichi Suyama , Kazukiyo Fukudome
发明人： Junichi Suyama , Kazukiyo Fukudome
IPC分类号： G11C11/41 , G11C8/18 , H03K5/04 , H03K5/19
CPC分类号： H03K5/04 , G11C8/18
摘要： In an ATD circuit, a pulse width amplifier circuit is provided between a first circuit means and a second circuit means. The first circuit means generates a first output signal having a first pulse width in response to a change in external address signal and generates, when the external address signal becomes a first sawtooth signal, a second sawtooth output signal having a peak value smaller than that of the first sawtooth signal. The second circuit means receives therein the signal generated by the pulse width amplifier circuit and waveform-shapes the output signal so as to provide an ATD signal therefrom. The pulse width amplifier circuit amplifies a pulse width of the signal generated by the first circuit means. Further, the pulse width amplifier circuit generates a third output signal having a second pulse width corresponding to the first pulse width when the first output signal is received thereto and generates a fourth output signal having a third pulse width when the second output signal is received thereto.
摘要翻译：在ATD电路中，在第一电路装置和第二电路装置之间提供脉宽放大器电路。第一电路装置响应于外部地址信号的变化产生具有第一脉冲宽度的第一输出信号，并且当外部地址信号变为第一锯齿波信号时，产生第二锯齿波输出信号，峰值小于第一个锯齿波信号。第二电路装置在其中接收由脉冲宽度放大器电路产生的信号，并对输出信号进行波形整形，从而提供ATD信号。脉宽放大器电路放大由第一电路装置产生的信号的脉冲宽度。此外，当接收到第一输出信号时，脉宽放大器电路产生具有对应于第一脉冲宽度的第二脉冲宽度的第三输出信号，并且当接收到第二输出信号时产生具有第三脉冲宽度的第四输出信号。

4. 发明授权

US06438061B1 Dynamic random access memory with low power consumption 有权
公开(公告)号：US06438061B1
公开(公告)日：2002-08-20
申请号：US09907449
申请日：2001-07-18
申请人： Junichi Suyama , Wataru Nagai , Akihiro Hirota , Shota Ohtsubo
发明人： Junichi Suyama , Wataru Nagai , Akihiro Hirota , Shota Ohtsubo
IPC分类号： G11C700
CPC分类号： G11C11/4074 , G11C5/147
摘要： There provides a low power consumption type dynamic random access memory (DRAM) with reduced current consumption in the DRAM by a signal from outside and without causing occurrence of malfunction at times of low current consumption. An input circuit for receiving signals, a memory array for holding data, and a peripheral circuit for controlling the memory array are driven by an internal voltage supplied by two groups of internal voltage receiving circuits while an output circuit for outputting signals is driven by an external power supply. The two groups of internal voltage receiving circuits are deactivated in response to a power supply control signal CONT inputted from outside, and the output circuit is controlled so as to be in a high impedance condition with voltage of the external power supply being applied thereto.

5. 发明授权

US5031153A MOS semiconductor memory device having sense control circuitry simplified 失效
标题翻译：具有简化的感测控制电路的MOS半导体存储器件
公开(公告)号：US5031153A
公开(公告)日：1991-07-09
申请号：US449562
申请日：1989-12-12
申请人： Junichi Suyama
发明人： Junichi Suyama
IPC分类号： G11C11/401 , G11C7/14 , G11C11/407 , G11C11/409 , G11C11/4091 , G11C11/4099
CPC分类号： G11C11/4091 , G11C11/4099 , G11C7/14
摘要： An MOS semiconductor memory device includes memory cell matrices. Each matrix is constituted with memory cells and noise cancellers. Each memory cell is connected, at an intersection between a pair of bit lines and a word line, between either one of the bit lines and the word line. The word line controls read and write operations of the memory cell. The noise canceller is connected, at an intersection between a pair of bit lines and a dummy word line, between either one of the bit lines and the dummy word line. The dummy word line enables the noise canceller. The memory cell matrices form groups of memory cells into which the cells are grouped in accordance wtih addresses. The dummy word line and the word line have substantially identical characteristics. The dummy word line possesses parasitic resistance and capacitance to delay by a first predetermined period of time a signal to enable the noise canceller. The memory device further includes sense amplifier circuits connected between the pair of bit lines of the memory cell matrices for amplifying a potential difference between the bit lines in response to an enable signal, and a sense control circuit connected to the dummy word lines and the sense amplifier circuits to be operative in a read or write operation of the memory cell for selectively enabling related sense amplifier circuits in response to a signal delayed by a dummy word line of selected ones of the memory cell matrices.
摘要翻译： MOS半导体存储器件包括存储单元矩阵。每个矩阵由存储器单元和噪声消除器构成。每个存储器单元在位线和字线中的任一个之间的一对位线和字线之间的交叉点处连接。字线控制存储单元的读写操作。噪声消除器在位线和哑字线之间的一对位线和虚拟字线之间的交叉点处连接。虚拟字线使噪声消除器。存储单元矩阵形成存储单元组，单元根据地址分组到其中。虚拟字线和字线具有基本相同的特性。虚拟字线具有寄生电阻和电容，以延迟第一预定时间段以产生噪声消除器的信号。存储装置还包括连接在存储单元矩阵的一对位线之间的读出放大器电路，用于响应于使能信号放大位线之间的电位差，以及连接到虚拟字线和感测的读出控制电路放大器电路在存储器单元的读取或写入操作中工作，用于响应于被选择的存储单元矩阵的虚拟字线延迟的信号选择性地使能相关读出放大器电路。

6. 发明授权

US06574150B2 Dynamic random access memory with low power consumption 有权
标题翻译：具有低功耗的动态随机存取存储器
公开(公告)号：US06574150B2
公开(公告)日：2003-06-03
申请号：US10175859
申请日：2002-06-21
申请人： Junichi Suyama , Wataru Nagai , Akihiro Hirota , Shota Ohtsubo
发明人： Junichi Suyama , Wataru Nagai , Akihiro Hirota , Shota Ohtsubo
IPC分类号： G11C700
CPC分类号： G11C11/4074 , G11C5/147
摘要： A low power consumption type dynamic random access memory (DRAM) operable with reduced current consumption responsive to an external signal, without causing occurrence of malfunction during low current consumption. An input circuit for receiving signals, a memory array for holding data, and a peripheral circuit for controlling the memory array are driven by an internal voltage supplied by two groups of internal voltage receiving circuits, while an output circuit for outputting signals is driven by an external power supply. The two groups of internal voltage receiving circuits are deactivated in response to an externally provided power supply control signal, and the output circuit is controlled so as to be in a high impedance condition with voltage of the external power supply being applied thereto.
摘要翻译：低功耗型动态随机存取存储器（DRAM），可以响应于外部信号而以可减小的电流消耗进行操作，而不会在低电流消耗期间发生故障。用于接收信号的输入电路，用于保持数据的存储器阵列和用于控制存储器阵列的外围电路由内部电压接收电路组提供的内部电压驱动，而用于输出信号的输出电路由外部电源。两组内部电压接收电路响应于外部提供的电源控制信号被去激活，并且输出电路被控制成在施加外部电源的电压的情况下处于高阻抗状态。

7. 发明授权

US5446694A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5446694A
公开(公告)日：1995-08-29
申请号：US225968
申请日：1994-04-08
申请人： Takayuki Tanaka , Junichi Suyama , Kazukiyo Fukudome , Yuki Hashimoto
发明人： Takayuki Tanaka , Junichi Suyama , Kazukiyo Fukudome , Yuki Hashimoto
IPC分类号： G11C11/407 , G11C5/14 , G11C11/4074 , G11C11/409 , G11C11/4091 , G11C11/34
CPC分类号： G11C5/147 , G11C11/4074 , G11C11/4091
摘要： A semiconductor memory device of the present invention comprises an internal power supplying circuit electrically connected to an external power supply having an external source potential and for supplying an internal potential lower than the external source potential, a precharging circuit for supplying a half potential of the internal potential to each of memory cells and bit lines, and a switching circuit electrically connected between each bit line and the precharging circuit and controlled based on an equalize signal output from a control circuit and having the same potential as the external source potential. The semiconductor memory device of such a type that even if a potential on each bit line increases excessively, such a potential does not exert an influence on each memory cell, can be realized owing to the above structure.
摘要翻译：本发明的半导体存储器件包括：内部供电电路，其电连接到具有外部源极电位的外部电源，并提供低于外部电位电位的内部电位;预充电电路，用于提供内部电位的半电位每个存储单元和位线的电位，以及电连接在每个位线和预充电电路之间的开关电路，并且基于从控制电路输出并具有与外部源极电位相同的电位的均衡信号来控制。这种类型的半导体存储器件，即使每个位线上的电位都过大，这种电位也不会对每个存储单元产生影响，所以可以通过上述结构实现。

8. 发明授权

US5420823A Semiconductor memory with improved power supply control circuit 失效
标题翻译：半导体存储器具有改进的电源控制电路
公开(公告)号：US5420823A
公开(公告)日：1995-05-30
申请号：US115023
申请日：1993-09-02
申请人： Takeru Yonaga , Jouji Ueno , Junichi Suyama
发明人： Takeru Yonaga , Jouji Ueno , Junichi Suyama
IPC分类号： G11C11/419 , G11C7/06 , G11C11/409 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C7/065
摘要： A semiconductor memory has sense amplifiers which are supplied with a first potential from a first supply line and a second potential from a second supply line. A switching element on the first supply line is controlled by the potential of the second supply line, its conductivity increasing as the potential of the second supply line moves toward the second potential. A similar switching element, controlled by the potential of the first supply line, can be provided on the second supply line.
摘要翻译：半导体存储器具有从第一电源线提供第一电位的读出放大器和来自第二电源线的第二电位。第一供电线上的开关元件由第二供电线的电位控制，随着第二供电线的电位向第二电位移动，其电导率增加。可以在第二供给管线上设置由第一供给管线的电位控制的类似的开关元件。

9. 发明授权

US06791894B2 DRAM power-source controller that reduces current consumption during standby 有权
标题翻译： DRAM电源控制器，可在待机期间降低电流消耗
公开(公告)号：US06791894B2
公开(公告)日：2004-09-14
申请号：US10252102
申请日：2002-09-23
申请人： Wataru Nagai , Akihiro Hirota , Junichi Suyama
发明人： Wataru Nagai , Akihiro Hirota , Junichi Suyama
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C11/4074 , G11C2207/2227
摘要： A power-source controller for reducing current consumption while a DRAM is in standby, includes a mode detection circuit inverting a disable signal having an L-level under the enable state and having an H-level under the disable state; an internal-power-source driver circuit having first and second transistors; and an internal-power-source reference circuit setting first and second driver control signals respectively to L-level and H-level when an L-level disable signal is input to turn on the first transistor and turn off the second transistor, supplying an external-power-source voltage as an internal-power-source voltage, setting the first driver control signal to H-level when an H-level disable signal is input, controlling the level of the second driver control signal to turn off the second transistor and control the first transistor, and supplying an internal power-source voltage lower than the external-power-source voltage.
摘要翻译：一种用于在DRAM处于待机状态时降低电流消耗的电源控制器，包括模式检测电路，使具有在使能状态下具有L电平并且处于禁用状态的H电平的禁用信号反相; 具有第一和第二晶体管的内部电源驱动器电路; 以及内部电源参考电路，当输入L电平禁止信号时，将第一和第二驱动器控制信号分别设置为L电平和H电平，以接通第一晶体管并关断第二晶体管，提供外部电源电压作为内部电源电压，当输入H电平禁止信号时将第一驱动器控制信号设置为H电平，控制第二驱动器控制信号的电平以关闭第二晶体管，以及控制第一晶体管，并提供低于外部电源电压的内部电源电压。

10. 发明授权

US5973982A Pulse width amplifier circuit 失效
标题翻译：脉宽放大电路
公开(公告)号：US5973982A
公开(公告)日：1999-10-26
申请号：US110202
申请日：1998-07-06
申请人： Junichi Suyama , Kazukiyo Fukudome
发明人： Junichi Suyama , Kazukiyo Fukudome
IPC分类号： G11C8/18 , H03K5/04 , G11C13/00
CPC分类号： G11C8/18 , H03K5/04
摘要： Disclosed herein is an ATD circuit of the present invention. In order to generate a stable ATD pulse, a pulse width amplifier circuit is provided between a first circuit means and a second circuit means. The first circuit means outputs a first output signal having a first pulse width in response to a change in external address signal and outputs, when the external address signal is brought to a first sawtooth signal, a second sawtooth output signal having a peak value smaller than that of the first sawtooth signal. The second circuit means inputs therein the signal outputted from the pulse width amplifier circuit and waveform-shapes the output signal so as to output an ATD signal therefrom. The pulse width amplifier circuit amplifies a pulse width of the signal outputted from the first circuit means. Further, the pulse width amplifier circuit outputs a third output signal having a second pulse width corresponding to the first pulse width when the first output signal is input thereto and outputs a fourth output signal having a third pulse width when the second output signal is input thereto.
摘要翻译：本文公开了本发明的ATD电路。为了产生稳定的ATD脉冲，在第一电路装置和第二电路装置之间提供脉宽放大器电路。第一电路装置响应于外部地址信号的改变输出具有第一脉冲宽度的第一输出信号，并且当外部地址信号被带到第一锯齿波信号时输出第二锯齿波输出信号，其峰值小于第一个锯齿波信号。第二电路是输入从脉宽放大器电路输出的信号，并对输出信号进行波形整形，从而输出ATD信号。脉冲宽度放大器电路放大从第一电路装置输出的信号的脉冲宽度。此外，当输入第一输出信号时，脉宽放大器电路输出具有与第一脉冲宽度对应的第二脉冲宽度的第三输出信号，并且当输入第二输出信号时，输出具有第三脉冲宽度的第四输出信号。

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