专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5212378A Optical receiver with critical damping resistor 失效
标题翻译：具有关键阻尼电阻的光接收器
公开(公告)号：US5212378A
公开(公告)日：1993-05-18
申请号：US790189
申请日：1991-11-08
申请人： Yoshihiro Uda
发明人： Yoshihiro Uda
IPC分类号： H03K17/78 , H04B10/2507 , H04B10/40 , H04B10/50 , H04B10/60 , H04B10/67
CPC分类号： H04B10/6911
摘要： An optical receiver includes a light-receiving element, a bias circuit, an output circuit, and a damping resistor. The light-receiving element converts an optical signal into an electrical signal. The bias circuit applies a DC bias voltage to the light-receiving element. The output circuit outputs, from an output terminal, a voltage corresponding to an optical current generated by the light-receiving element. The damping resistor is connected between the light-receiving element and the output terminal in the output circuit and has a resistance set to serve as a critical damping condition in combination with a junction capacitance and a lead inductance of the light-receiving element.

2. 发明申请

US20100020497A1 SUBSTRATE STRUCTURE 失效
标题翻译：基板结构
公开(公告)号：US20100020497A1
公开(公告)日：2010-01-28
申请号：US12065177
申请日：2006-02-20
申请人： Haruo Hayakawa , Masahiro Ono , Seiji Yamaguchi , Yoshihiro Uda , Kazuhiro Shinchi , Satoru Tomekawa , Kiyoshi Nakanishi , Kosuke Kubota , Atsushi Katagiri , Motohisa Kotani , Kazuhiro Konishi , Eiji Nishimura , Takeo Matsuki
发明人： Haruo Hayakawa , Masahiro Ono , Seiji Yamaguchi , Yoshihiro Uda , Kazuhiro Shinchi , Satoru Tomekawa , Kiyoshi Nakanishi , Kosuke Kubota , Atsushi Katagiri , Motohisa Kotani , Kazuhiro Konishi , Eiji Nishimura , Takeo Matsuki
IPC分类号： H05K7/20 , H05K7/00
CPC分类号： H05K3/284 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H05K1/0203 , H05K1/0218 , H05K1/0274 , H05K7/20463 , H05K9/0047 , H05K9/0086 , H05K2201/0209 , H05K2201/0215 , H05K2201/10128 , H05K2201/10515 , H05K2201/2054 , H05K2203/1316 , H05K2203/1322 , H01L2224/0401
摘要： It is intended to provide a substrate structure ensuring a shielding property and a heat discharge property of a resin part that collectively covers a plurality of electronic components and capable of downsizing, thinning, and a reduction in number of components. The substrate structure 20 of the first embodiment is provided with a substrate 21, a plurality of electronic components 22 mounted along the substrate 21, and a resin part 25 that covers the electronic components 22 and is in close contact with the substrate 21. In the substrate structure 20, the resin part 25 is provided with a reinforcing heat discharge layer 26 covering the electronic components 22 and having a heat conductivity and a reinforcing property and a shield layer 27 covering the reinforcing heat discharge layer 26, and a surface o28 of the shield layer 27 is formed into a predetermined shape corresponding to a surface structure of the display device 30 adjacent to the resin part 25.
摘要翻译：旨在提供确保共同覆盖多个电子部件并能够减小，减薄和减少部件数量的树脂部件的屏蔽性和散热性的基板结构。第一实施例的基板结构20设置有基板21，沿着基板21安装的多个电子部件22和覆盖电子部件22并与基板21紧密接触的树脂部25。基板结构体20中，树脂部25设置有覆盖电子部件22并具有导热性和增强性的加强放热层26和覆盖加强放热层26的屏蔽层27以及覆盖加强放热层26的表面o28 屏蔽层27形成为与显示装置30的与树脂部25相邻的表面结构对应的规定形状。

3. 发明授权

US5247652A Parallel to serial converter enabling operation at a high bit rate with slow components by latching sets of pulses following sequential delays equal to clock period 失效
标题翻译：与串行转换器并行，使得能够以等于时钟周期的顺序延迟之后的脉冲组锁存，以较慢的分量以高比特率运行
公开(公告)号：US5247652A
公开(公告)日：1993-09-21
申请号：US515862
申请日：1990-04-27
申请人： Yoshihiro Uda
发明人： Yoshihiro Uda
IPC分类号： G06F5/00 , G06F5/16 , H03M9/00
CPC分类号： H03M9/00
摘要： A parallel to serial converter for convering incoming parallel, byte sized, data supplied at a first data rate to single bit serial data includes a shift register in which several bytes of the incoming data are stored simultaneously and thereafter serially transmitted therefrom. The parallel to serial converter includes latching devices in which the incoming data bytes are stored prior to being transferred to the shift register. Since successively arriving bytes of data are stored in successively selected ones of the latching devices, the data rate (device speed) of the latches is permitted to be only a fraction of the first data rate associated with the incoming bytes of data resulting in a fast, yet inexpensive, circuit.
摘要翻译：用于将以第一数据速率提供的输入并行，字节大小的数据的并行串行转换器转换为单比特串行数据包括移位寄存器，其中输入数据的多个字节同时存储，然后从其中串行发送。并行到串行转换器包括锁存装置，其中输入数据字节在被传送到移位寄存器之前被存储。由于连续到达的数据字节被存储在连续选择的锁存装置中，所以锁存器的数据速率（设备速度）被允许只是与数据的输入字节相关联的第一数据速率的一小部分，导致快速，但价格便宜，电路。

4. 发明授权

US07969741B2 Substrate structure 失效
标题翻译：基材结构
公开(公告)号：US07969741B2
公开(公告)日：2011-06-28
申请号：US12065177
申请日：2006-02-20
申请人： Haruo Hayakawa , Masahiro Ono , Seiji Yamaguchi , Yoshihiro Uda , Kazuhiro Shinchi , Satoru Tomekawa , Kiyoshi Nakanishi , Kosuke Kubota , Atsushi Katagiri , Motohisa Kotani , Kazuhiro Konishi , Eiji Nishimura , Takeo Matsuki
发明人： Haruo Hayakawa , Masahiro Ono , Seiji Yamaguchi , Yoshihiro Uda , Kazuhiro Shinchi , Satoru Tomekawa , Kiyoshi Nakanishi , Kosuke Kubota , Atsushi Katagiri , Motohisa Kotani , Kazuhiro Konishi , Eiji Nishimura , Takeo Matsuki
IPC分类号： H05K7/20
CPC分类号： H05K3/284 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H05K1/0203 , H05K1/0218 , H05K1/0274 , H05K7/20463 , H05K9/0047 , H05K9/0086 , H05K2201/0209 , H05K2201/0215 , H05K2201/10128 , H05K2201/10515 , H05K2201/2054 , H05K2203/1316 , H05K2203/1322 , H01L2224/0401
摘要： It is intended to provide a substrate structure ensuring a shielding property and a heat discharge property of a resin part that collectively covers a plurality of electronic components and capable of downsizing, thinning, and a reduction in number of components. The substrate structure 20 of the first embodiment is provided with a substrate 21, a plurality of electronic components 22 mounted along the substrate 21, and a resin part 25 that covers the electronic components 22 and is in close contact with the substrate 21. In the substrate structure 20, the resin part 25 is provided with a reinforcing heat discharge layer 26 covering the electronic components 22 and having a heat conductivity and a reinforcing property and a shield layer 27 covering the reinforcing heat discharge layer 26, and a surface o28 of the shield layer 27 is formed into a predetermined shape corresponding to a surface structure of the display device 30 adjacent to the resin part 25.
摘要翻译：旨在提供确保共同覆盖多个电子部件并能够减小，减薄和减少部件数量的树脂部件的屏蔽性和散热性的基板结构。第一实施例的基板结构20设置有基板21，沿着基板21安装的多个电子部件22和覆盖电子部件22并与基板21紧密接触的树脂部25。基板结构体20中，树脂部25设置有覆盖电子部件22并具有导热性和增强性的加强放热层26和覆盖加强放热层26的屏蔽层27以及覆盖加强放热层26的表面o28 屏蔽层27形成为与显示装置30的与树脂部25相邻的表面结构对应的规定形状。

5. 发明授权

US4975566A First stage circuit for an optical receiver 失效
标题翻译：光接收机的第一级电路
公开(公告)号：US4975566A
公开(公告)日：1990-12-04
申请号：US430040
申请日：1989-10-31
申请人： Yoshihiro Uda
发明人： Yoshihiro Uda
IPC分类号： H01L31/10 , H04B10/2507
CPC分类号： H04B10/69 , H04B10/6973
摘要： First and second photoelectric converting circuits are provided to be connected to first and second input terminals of a differential amplifier, respectively. The first and second photoelectric converting circuits are optically coupled to a common optical fiber, so that first and second electric signals which are reverse in polarity are supplied to the first and second input terminals. Consequently, noise superposed, for instance, on a power supply line is supplied through the first and second photoelectric converting circuits to the first and second input terminals of the differential amplifier with the same phase as each other, so that the noises are cancelled in the differential amplifier.

6. 发明授权

US5197082A Digital signal regenerator 失效
标题翻译：数字信号再生器
公开(公告)号：US5197082A
公开(公告)日：1993-03-23
申请号：US349641
申请日：1989-05-10
申请人： Yoshihiro Uda , Nobuaki Takahashi
发明人： Yoshihiro Uda , Nobuaki Takahashi
IPC分类号： H04L25/40 , H04L7/027 , H04L25/24
CPC分类号： H04L25/242 , H04L7/027
摘要： Disclosed is a digital signal regenerator responsive to a data bit stream having a predetermined bit rate for generating a retimed data bit stream. The digital signal regenerator includes a transition detect and pulse generating circuit responsive to the data bit stream for detecting transition positions between two different states of the data bit stream and for generating respective width-variable pulses at the transition positions. Filtering circuitry responsive to the width-variable pulses is provided for extracting a timing wave from the data bit stream. A clock-pulse generating circuit responsive to the timing wave is provided for generating a clock pulse sequence. A discriminating circuit responsive to the clock pulse sequence is lastly provided for discriminating between levels "1" and "0" of the data bit sequence to generate the retimed data bit stream.

7. 发明授权

US4622477A Light emitting diode driver circuit 失效
标题翻译：发光二极管驱动电路
公开(公告)号：US4622477A
公开(公告)日：1986-11-11
申请号：US673451
申请日：1984-11-21
申请人： Yoshihiro Uda
发明人： Yoshihiro Uda
IPC分类号： H04B10/60 , H03K5/02 , H03K17/60 , H04B10/00 , H04B10/40 , H04B10/50 , H04B10/80 , H03K19/14 , G06G7/12 , H03K3/26
CPC分类号： H04B10/502 , H03K17/603 , H03K5/02 , H04B10/564
摘要： An LED driver circuit of a digital optical transmitter for an optical fiber data link includes a differential amplifier with emitter coupled transistors, an LED being connected to the collector of one of the emitter coupled transistors. A current source is connected to the common emitters to enable switching of the emitter coupled transistors in response to an input signal. The input signal, a first delayed input signal and a second delayed input signal, are applied to the current source through an OR circuit, to render the current source conductive in response to said input signal, the first delayed input signal or the second delayed input signal. The first delayed input signal and an inverted first delayed input signal switch the emitter coupled transistors when the current source is conductive. As the current source is conductive at the transistor switching times, high speed switching with smooth charging and discharging of the LED junction capacitance is achieved. Further, since the current source turns on and off in response to the input signal current consumption is conserved.
摘要翻译：用于光纤数据链路的数字光发射机的LED驱动器电路包括具有发射极耦合晶体管的差分放大器，LED连接到发射极耦合晶体管之一的集电极。电流源连接到公共发射器，以响应于输入信号来启动发射极耦合晶体管的切换。输入信号，第一延迟输入信号和第二延迟输入信号通过OR电路施加到电流源，以使电流源响应于所述输入信号，第一延迟输入信号或第二延迟输入信号。当电流源导通时，第一延迟输入信号和反相第一延迟输入信号切换发射极耦合晶体管。由于电流源在晶体管切换时间导通，因此实现了LED结电容平滑充放电的高速切换。此外，由于电流源响应于输入信号而导通和截止，因此电流消耗被保存。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式