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1. 发明授权

US06297675B1 Semiconductor integrated circuit and semiconductor integrated circuit system having serially interconnectable data buses 有权
标题翻译：具有串行可互连数据总线的半导体集成电路和半导体集成电路系统
公开(公告)号：US06297675B1
公开(公告)日：2001-10-02
申请号：US09478530
申请日：2000-01-06
申请人： Hironori Akamatsu , Yutaka Terada , Takashi Hirata , Yukio Arima , Satoshi Takahashi , Tadahiro Yoshida , Yoshihide Komatsu , Hiroyuki Yamauchi
发明人： Hironori Akamatsu , Yutaka Terada , Takashi Hirata , Yukio Arima , Satoshi Takahashi , Tadahiro Yoshida , Yoshihide Komatsu , Hiroyuki Yamauchi
IPC分类号： H03B100
CPC分类号： H03K19/018514 , Y10T307/549
摘要： A data line pair and a strobe line pair are provided between first and second chips to exchange data therebetween. The first chip includes an output circuit and a controller for controlling the output circuit. The second chip includes an input circuit. For example, the output circuit supplies a direct current from a power supply to one of the data lines. Then, the input circuit feeds back the received current to the output circuit through a pair of terminal resistors and the other data line. Subsequently, the output circuit supplies the fed back direct current to one of the strobe lines. In response, the input circuit feeds back the received current again to the output circuit through another pair of terminal resistors and the other strobe line. And then the fed back current is drained to the ground. Thus, compared to driving the data and strobe line pairs separately with the same amount of current supplied, the current dissipation can be halved. In this manner, the present invention is applicable to reduction of current dissipation when data should be transmitted at high speeds through multiple data bus pairs that are driven with a current supplied.
摘要翻译：在第一和第二芯片之间提供数据线对和选通线对，以在它们之间交换数据。第一芯片包括输出电路和用于控制输出电路的控制器。第二芯片包括输入电路。例如，输出电路将电流从电源提供给数据线之一。然后，输入电路通过一对端子电阻和另一条数据线将接收的电流反馈到输出电路。随后，输出电路将反馈的直流电流提供给选通线之一。作为响应，输入电路通过另一对端子电阻器和另一个选通线路将接收到的电流再次反馈到输出电路。然后将反馈电流排到地面。因此，与以相同的电流量驱动数据和选通线对相比，电流消耗可以减半。以这种方式，本发明可应用于当通过以所提供的电流驱动的多个数据总线对以高速传输数据时，减少电流消耗。

2. 发明授权

US06633588B1 Data transferring device 有权
标题翻译：数据传输设备
公开(公告)号：US06633588B1
公开(公告)日：2003-10-14
申请号：US09410764
申请日：1999-10-01
申请人： Tadahiro Yoshida , Hiroyuki Yamauchi , Hironori Akamatsu , Satoshi Takahashi , Yutaka Terada , Yukio Arima , Takashi Hirata , Yoshihide Komatsu
发明人： Tadahiro Yoshida , Hiroyuki Yamauchi , Hironori Akamatsu , Satoshi Takahashi , Yutaka Terada , Yukio Arima , Takashi Hirata , Yoshihide Komatsu
IPC分类号： G06F1516
CPC分类号： G06F13/4265 , Y02D10/14 , Y02D10/151
摘要： First and second nodes are coupled together by a bus. The first node includes a detecting circuit for detecting the maximum data transfer capability of a connected node, at least two receiving circuits for receiving data from the bus, and a controlling circuit for selecting, based on an output signal from the detecting circuit and for optimizing the configuration of a receiving unit so as to bring the other of the receiving circuits to a stop. The second node includes a transmitting circuit for transmitting data to the bus and a notifying circuit for notifying the first node of its own maximum transfer capability.
摘要翻译：第一和第二节点通过总线耦合在一起。第一节点包括用于检测连接节点的最大数据传输能力的检测电路，用于从总线接收数据的至少两个接收电路，以及用于基于来自检测电路的输出信号进行优化的控制电路接收单元的配置，以使另一个接收电路停止。第二节点包括用于向总线发送数据的发送电路和用于通知第一节点自己的最大传输能力的通知电路。

3. 发明授权

US06604201B1 Network unit with power saving mode inhibit based on interconnection relationship to neighboring nodes which is stored on the unit 有权
标题翻译：具有省电模式的网络单元基于与存储在单元上的相邻节点的互连关系而禁止
公开(公告)号：US06604201B1
公开(公告)日：2003-08-05
申请号：US09428277
申请日：1999-10-27
申请人： Satoshi Takahashi , Hiroyuki Yamauchi , Hironori Akamatsu , Tadahiro Yoshida , Yutaka Terada , Yukio Arima , Takashi Hirata , Yoshihide Komatsu
发明人： Satoshi Takahashi , Hiroyuki Yamauchi , Hironori Akamatsu , Tadahiro Yoshida , Yutaka Terada , Yukio Arima , Takashi Hirata , Yoshihide Komatsu
IPC分类号： G06F132
CPC分类号： H04L12/12 , Y02D50/20 , Y02D50/40
摘要： A power-saving network unit, which is connected to a network made up of a plurality of power-saving network units, includes: network monitoring means; network information memory; power-saving mode setting means; peripheral I/O interface; and digital processor. The network monitoring means monitors a topology of the network, or the interconnection relationship among the power-saving network units. Every time the network has been modified, the network monitoring means stores the modified network topology on the network information memory. The power-saving mode setting means receives the network information stored on the network information memory. If the power-saving network unit is a master or relay node in the network, then the power-saving mode setting means locks the peripheral I/O interface and digital processor of the power-saving network unit to the normal operation mode and prohibits these sections from entering the power-saving mode.
摘要翻译：连接到由多个省电网络单元组成的网络的节电网单元包括：网络监控装置; 网络信息记忆; 省电模式设定手段; 外设I / O接口; 和数字处理器。网络监控装置监控网络的拓扑结构，或节能网络单元之间的互连关系。每当网络被修改时，网络监控装置将修改的网络拓扑存储在网络信息存储器上。省电模式设置装置接收存储在网络信息存储器上的网络信息。如果省电网络单元是网络中的主节点或中继节点，则省电模式设置装置将节电网络单元的外围I / O接口和数字处理器锁定到正常操作模式，并禁止这些部分进入省电模式。

4. 发明授权

US06631486B1 Semiconductor integrated circuit and method for testing the same 有权
标题翻译：半导体集成电路及其测试方法
公开(公告)号：US06631486B1
公开(公告)日：2003-10-07
申请号：US09405015
申请日：1999-09-27
申请人： Yoshihide Komatsu , Tadahiro Yoshida , Yukio Arima
发明人： Yoshihide Komatsu , Tadahiro Yoshida , Yukio Arima
IPC分类号： G01R3128
CPC分类号： G01R31/31905 , G01R31/31926
摘要： A test enable signal Data_En is output from a data generator 11 in a tester 10 to a device under a test (DUT) 20. In the DUT 20, a first logic circuit 21 converts a signal pattern with an ordinary transfer rate, which has been stored on a register 28, into a high-transfer-rate signal pattern SpeedData_Tx with a high rate. And a transmitter 22 transmits the high-transfer-rate signal. During a test, the high-transfer-rate signal transmitted is received by, a receiver 23 with a switch 24 turned ON. Then, the high-transfer-rate signal received is output to a second logic circuit 26, which converts the high-transfer-rate signal into a low-transfer-rate signal Data_Rx with an ordinary rate. Finally, the low-transfer-rate signal is output to the tester 10 and compared to an expected value thereof by a comparator 12. In this manner, a semiconductor device operating at a high speed can be tested using a tester operating at a lower speed.
摘要翻译：测试使能信号Data_En从测试器10中的数据发生器11输出到被测设备（DUT）20。在DUT 20中，第一逻辑电路21以一般传输速率转换信号模式存储在寄存器28中，以高速率转换成高传输速率信号模式SpeedData_Tx。并且发射机22发送高传输速率信号。在测试期间，传输的高传输速率信号由开关24接通的接收机23接收。然后，所接收的高传输速率信号被输出到第二逻辑电路26，第二逻辑电路26将高传输速率信号以普通速率转换成低传输速率信号Data_Rx。最后，将低传输速率信号输出到测试器10，并通过比较器12与其期望值进行比较。以这种方式，可以使用以较低速度操作的测试仪来测试以高速工作的半导体器件。

5. 发明授权

US06498519B1 Voltage control circuit network device and method of detecting voltage 有权
标题翻译：电压控制电路网络装置及电压检测方法
公开(公告)号：US06498519B1
公开(公告)日：2002-12-24
申请号：US09498339
申请日：2000-02-04
申请人： Yutaka Terada , Hiroyuki Yamauchi , Hironori Akamatsu , Tadahiro Yoshida , Satoshi Takahashi , Takashi Hirata , Yukio Arima , Yoshihide Komatsu
发明人： Yutaka Terada , Hiroyuki Yamauchi , Hironori Akamatsu , Tadahiro Yoshida , Satoshi Takahashi , Takashi Hirata , Yukio Arima , Yoshihide Komatsu
IPC分类号： H03K5153
CPC分类号： G01R19/16547
摘要： A voltage control circuit for implementing, e.g., the CPS function in which a high-accuracy comparison is performed between a high external voltage and a reference voltage. A diode-connected transistor converts the external voltage to a voltage lower than the external voltage in conjunction with an external voltage dropping resistor. A comparator compares the converted voltage with a specified comparison voltage. The size of the transistor is determined such that the ratio of an increment of the converted voltage to an increment of the external voltage is sufficiently high in a comparison region in which the external voltage is close to the reference voltage. A clamping circuit clamps the converted voltage with a specified limit voltage such that the converted voltage does not exceed the withstand voltage of the circuit.
摘要翻译：一种用于实现例如在高外部电压和参考电压之间进行高精度比较的CPS功能的电压控制电路。二极管连接的晶体管将外部电压转换为低于外部电压的电压，并结合外部降压电阻。比较器将转换的电压与指定的比较电压进行比较。确定晶体管的尺寸，使得在外部电压接近参考电压的比较区域中，转换电压的增量与外部电压的增量的比率足够高。钳位电路以转换后的电压将指定的极限电压钳位，使转换后的电压不超过电路的耐压。

6. 发明授权

US06356144B1 LSI core including voltage generation circuit and system LSI including the LSI core 有权
标题翻译： LSI核心，包括具有LSI核心的电压产生电路和系统LSI
公开(公告)号：US06356144B1
公开(公告)日：2002-03-12
申请号：US09580139
申请日：2000-05-30
申请人： Hironori Akamatsu , Yutaka Terada , Takashi Hirata , Tadahiro Yoshida , Yoshihide Komatsu
发明人： Hironori Akamatsu , Yutaka Terada , Takashi Hirata , Tadahiro Yoshida , Yoshihide Komatsu
IPC分类号： H01L2500
CPC分类号： G06F13/4086 , H01L2224/05554
摘要： An LSI core includes a first terminal; a second terminal; and a voltage generation circuit for generating a voltage. The first terminal is connected to a first external line provided outside the LSI core. The second terminal is connected to the first external line and to a second external line provided outside the LSI core. The voltage generation circuit includes a voltage generation section for generating the voltage, an output section for outputting the voltage generated by the voltage generation section to the first external line through the first terminal, and an input section for receiving the voltage, output to the first external line by the output section, through the second external line and the second terminal.
摘要翻译： LSI核心包括第一终端; 第二个终端以及用于产生电压的电压产生电路。第一端子连接到设置在LSI核心外部的第一外部线路。第二端子连接到第一外部线路和连接到设置在LSI核心外部的第二外部线路。电压产生电路包括用于产生电压的电压产生部分，用于通过第一端子将由电压产生部分产生的电压输出到第一外部线路的输出部分和用于接收电压的输入部分，输出到第一外部线由输出部分，通过第二个外部线路和第二个终端。

7. 发明申请

US20120162189A1 DRIVER CIRCUIT AND VIDEO SYSTEM 审中-公开
标题翻译：驱动电路和视频系统
公开(公告)号：US20120162189A1
公开(公告)日：2012-06-28
申请号：US13412258
申请日：2012-03-05
申请人： Tsuyoshi Ebuchi , Yoshihide Komatsu , Kurumi Nakayama
发明人： Tsuyoshi Ebuchi , Yoshihide Komatsu , Kurumi Nakayama
IPC分类号： G09G5/00 , H03K3/00
CPC分类号： H03K19/018514 , H03K19/00361 , H04L25/0276
摘要： In a driver circuit in a transmission system, an output circuit outputs a differential signal based on input data signals. A current source control circuit controls a constant current source so that a common-mode potential of the differential signal becomes equal to a predetermined reference potential. An overshoot reduction circuit is connected to an input line of the common-mode potential of the current source control circuit, and reduces an overshoot of the common-mode potential based on the control signal.
摘要翻译：在传输系统的驱动电路中，输出电路基于输入数据信号输出差分信号。电流源控制电路控制恒流源，使得差分信号的共模电位变得等于预定的参考电位。过冲减少电路连接到电流源控制电路的共模电位的输入线，并且基于控制信号减小共模电位的过冲。

8. 发明申请

US20110268198A1 DRIVER CIRCUIT, RECEIVER CIRCUIT, AND METHOD OF CONTROLLING A COMMUNICATIONS SYSTEM INCLUDING THE CIRCUITS 有权
标题翻译：驱动电路，接收电路和控制包括电路的通信系统的方法
公开(公告)号：US20110268198A1
公开(公告)日：2011-11-03
申请号：US13143233
申请日：2010-11-01
申请人： Shinichiro Nishioka , Yoshihide Komatsu , Hiroshi Suenaga , Kohei Masuda
发明人： Shinichiro Nishioka , Yoshihide Komatsu , Hiroshi Suenaga , Kohei Masuda
IPC分类号： H04L25/00
CPC分类号： H04B1/1615 , H04L25/0272
摘要： In a communications system for differential signals, a driver circuit is connected to a receiver circuit by a pair of differential signal lines. When data is not being transmitted, the differential signal lines are maintained at a predetermined electric potential, and when data is to be transferred, a differential signal is output at predetermined electric potentials. The receiver circuit switches between a power-down state and a normal state when detecting states of the electric potentials of the differential signal lines.
摘要翻译：在用于差分信号的通信系统中，驱动电路通过一对差分信号线连接到接收器电路。当不发送数据时，差分信号线保持在预定电位，并且当数据要被传送时，以预定电位输出差分信号。当检测到差分信号线的电位的状态时，接收器电路在掉电状态和正常状态之间切换。

9. 发明申请

US20110241432A1 INTERFACE CIRCUIT AND INTERFACE SYSTEM 有权
标题翻译：接口电路和接口系统
公开(公告)号：US20110241432A1
公开(公告)日：2011-10-06
申请号：US13139397
申请日：2010-11-01
申请人： Shinichiro Nishioka , Yoshihide Komatsu , Hiroshi Suenaga , Kohei Masuda
发明人： Shinichiro Nishioka , Yoshihide Komatsu , Hiroshi Suenaga , Kohei Masuda
IPC分类号： H02J4/00
CPC分类号： G06F13/42 , H04L25/0272 , Y10T307/696
摘要： To aim to provide an interface circuit that supports both a single-ended method and a differential method as a transmission method, and one of pairs of input terminals for a differential signal is shared to input/output a single-ended signal.A differential signal receiving circuit that receives a differential signal input through the pair of shared terminals is activated when a differential signal is input to a pair of dedicated input terminals for a differential signal, which is different from the pair of shared terminals. After the differential signal receiving circuit is activated, the active state is maintained by a built-in controller.Accordingly, the activation of the differential signal receiving circuit that receives a differential signal input through the shared terminals is controlled by controlling the differential signal input through the pair of dedicated input terminals, and furthermore, the possibility that the differential signal receiving circuit becomes inactive at an unexpected timing is reduced to a low level.
摘要翻译：为了提供支持单端方法和差分方法两者的接口电路作为传输方法，并且用于差分信号的一对输入端子被共享以输入/输出单端信号。当将差分信号输入到与一对共享终端不同的差分信号的一对专用输入端子时，接收通过一对共享端子输入的差分信号的差分信号接收电路被激活。在差分信号接收电路被激活之后，由内置控制器维持有效状态。因此，通过控制通过一对专用输入端子输入的差分信号来控制接收通过共享端子输入的差分信号的差分信号接收电路的激活，此外，差分信号接收电路在意想不到的时间降到了低水平。

10. 发明申请

US20120008713A1 HYBRID DATA TRANSMISSION CIRCUIT 有权
标题翻译：混合数据传输电路
公开(公告)号：US20120008713A1
公开(公告)日：2012-01-12
申请号：US13242962
申请日：2011-09-23
申请人： Tsuyoshi EBUCHI , Yoshihide Komatsu
发明人： Tsuyoshi EBUCHI , Yoshihide Komatsu
IPC分类号： H04L27/00
CPC分类号： H04L25/028 , H03K3/0322 , H03K5/15093 , H03L7/081 , H03L7/0995 , H03L2207/06 , H03M9/00 , H04L7/0337 , H04L25/0272
摘要： A data transmitter having a parallel-to-serial conversion function is supplied with a clock by a PLL circuit unit. In the PLL circuit unit, a first multiphase clock supplied to a first parallel-to-serial conversion circuit is generated and output by a multiphase VCO circuit, while a second multiphase clock supplied to a second parallel-to-serial conversion circuit is generated and output by a multiphase clock generator. The multiphase clock generator generates the second multiphase clock based on the clock output from the multiphase VCO circuit.
摘要翻译：具有并行到串行转换功能的数据发射机由PLL电路单元提供时钟。在PLL电路单元中，提供给第一并行转换电路的第一多相时钟由多相VCO电路产生并输出，同时产生提供给第二并行 - 串行转换电路的第二多相时钟，由多相时钟发生器输出。多相时钟发生器基于来自多相VCO电路的时钟输出产生第二多相时钟。

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