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1. 发明授权

US6153499A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US6153499A
公开(公告)日：2000-11-28
申请号：US289946
申请日：1999-04-13
申请人： Yoshiharu Anda , Toshinobu Matsuno , Katsunori Nishii , Kaoru Inoue , Manabu Yanagihara , Mitsuru Tanabe
发明人： Yoshiharu Anda , Toshinobu Matsuno , Katsunori Nishii , Kaoru Inoue , Manabu Yanagihara , Mitsuru Tanabe
IPC分类号： H01L21/28 , H01L21/027 , H01L21/285 , H01L21/338 , H01L21/768 , H01L29/812 , H01L21/44
CPC分类号： H01L21/28581 , H01L21/0271 , H01L21/0277 , H01L21/76816 , Y10S438/949
摘要： A first resist film for EB exposure, a buffer film, and a second resist film for i-line exposure are applied sequentially onto a substrate. Thereafter, the second resist film and the buffer film are subjected to patterning for forming a first opening. Then, dry etching is performed with respect to the first resist film masked with the second resist film to transfer the pattern of the second resist film to the first resist film and thereby form a second opening in the first resist film. Subsequently, a third resist film of chemically amplified type is applied to the entire surface of the first resist film to form a mixing layer in conjunction with the first resist film. As a result, the wall faces of the second opening are covered with the mixing layer and the width of the second opening is thereby reduced.
摘要翻译：用于EB曝光的第一抗蚀剂膜，缓冲膜和用于i线曝光的第二抗蚀剂膜顺序地施加到基板上。此后，对第二抗蚀剂膜和缓冲膜进行用于形成第一开口的图案化。然后，相对于用第二抗蚀剂膜掩蔽的第一抗蚀剂膜进行干蚀刻，将第二抗蚀剂膜的图案转印到第一抗蚀剂膜上，从而在第一抗蚀剂膜中形成第二开口。随后，将化学放大型的第三抗蚀剂膜施加到第一抗蚀剂膜的整个表面上以与第一抗蚀剂膜结合形成混合层。结果，第二开口的壁面被混合层覆盖，从而减小了第二开口的宽度。

2. 发明授权

US06051454A Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06051454A
公开(公告)日：2000-04-18
申请号：US151357
申请日：1998-09-10
申请人： Yoshiharu Anda , Toshinobu Matsuno , Manabu Yanagihara , Mitsuru Tanabe , Toshiaki Matsui , Nobumitsu Hirose
发明人： Yoshiharu Anda , Toshinobu Matsuno , Manabu Yanagihara , Mitsuru Tanabe , Toshiaki Matsui , Nobumitsu Hirose
IPC分类号： H01L21/285 , H01L21/335 , H01L21/338
CPC分类号： H01L29/66462 , H01L21/28587 , Y10S438/95
摘要： A lower resist film, which is made of PMMA for EB exposure and has a thickness of about 200 nm, is applied onto a substrate, and then an upper resist film to be exposed to i-rays is applied on the lower resist film. Thereafter, a mixed layer, in which the upper and lower resist films are mixed, is formed in the interface between the upper and lower resist films. Next, the upper resist film, except for the head-forming region thereof, is exposed to i-rays and developed, thereby forming an upper-layer opening. And then the mixed layer and a leg-forming region of the lower resist film are exposed to EB and developed, thereby forming a lower-layer opening having an upper part like a taper progressively expanding upward.
摘要翻译：将用于EB曝光的PMMA制成并具有约200nm厚度的较低抗蚀剂膜施加到基板上，然后在下抗蚀剂膜上施加暴露于i射线的上抗蚀剂膜。此后，在上下抗蚀剂膜之间的界面中形成混合有上下抗蚀剂膜的混合层。接下来，将除了其头部形成区域之外的上抗蚀剂膜暴露于i射线并显影，从而形成上层开口。然后将下层抗蚀剂膜的混合层和腿部形成区域暴露于EB并显影，从而形成具有逐渐向上扩展的锥形的上部的下层开口。

3. 发明授权

US08598628B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08598628B2
公开(公告)日：2013-12-03
申请号：US13231514
申请日：2011-09-13
申请人： Masahiro Hikita , Manabu Yanagihara
发明人： Masahiro Hikita , Manabu Yanagihara
IPC分类号： H01L29/72
CPC分类号： H01L29/42316 , H01L29/1066 , H01L29/2003 , H01L29/518 , H01L29/7786
摘要： A normally off semiconductor device with a reduced off-state leakage current, which is applicable to a power switching element, includes: a substrate; an undoped GaN layer formed above the substrate; an undoped AlGaN layer formed on the undoped GaN layer; a source electrode and a drain electrode, formed on the undoped GaN layer or the undoped AlGaN layer; a P-type GaN layer formed on the undoped AlGaN layer and disposed between the source electrode and the drain electrode; and a gate electrode formed on the P-type GaN layer, wherein the undoped GaN layer includes an active region including a channel and an inactive region not including the channel, and the P-type GaN layer is disposed to surround the source electrode.
摘要翻译：具有减小的截止状态漏电流的常闭半导体器件，其适用于功率开关元件，包括：衬底; 在衬底上形成未掺杂的GaN层; 在未掺杂的GaN层上形成未掺杂的AlGaN层; 源电极和漏电极，形成在未掺杂的GaN层或未掺杂的AlGaN层上; 形成在未掺杂的AlGaN层上并设置在源电极和漏电极之间的P型GaN层; 以及形成在所述P型GaN层上的栅电极，其中所述未掺杂的GaN层包括包括沟道的有源区和不包括所述沟道的非活性区，并且所述P型GaN层设置为围绕所述源电极。

4. 发明授权

US08497553B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08497553B2
公开(公告)日：2013-07-30
申请号：US12905801
申请日：2010-10-15
申请人： Hiroto Yamagiwa , Shingo Hashizume , Ayanori Ikoshi , Manabu Yanagihara , Yasuhiro Uemoto
发明人： Hiroto Yamagiwa , Shingo Hashizume , Ayanori Ikoshi , Manabu Yanagihara , Yasuhiro Uemoto
IPC分类号： H01L23/62 , H01L29/66 , H01L31/06 , H01L21/338 , H02H3/00 , H02H9/02
CPC分类号： H01L29/7786 , H01L27/0266 , H01L27/0605 , H01L29/1066 , H01L29/2003 , H01L29/41758 , H01L29/42364 , H01L29/8124 , H01L29/861
摘要： A semiconductor device includes a first transistor formed on a first element region, and a first protecting element including a second transistor formed on a second element region. A second protecting element ohmic electrode is connected to a first gate electrode, a first protecting element ohmic electrode is connected to a first ohmic electrode, and a first protecting element gate electrode is connected to at least one of the first protecting element ohmic electrode and the second protecting element ohmic electrode. The second element region is smaller in area than the first element region.
摘要翻译：半导体器件包括形成在第一元件区上的第一晶体管和包括形成在第二元件区上的第二晶体管的第一保护元件。第二保护元件欧姆电极连接到第一栅电极，第一保护元件欧姆电极连接到第一欧姆电极，第一保护元件栅电极连接至第一保护元件欧姆电极和第二保护元件欧姆电极。第二元件区域的面积小于第一元件区域。

5. 发明授权

US08384212B2 Semiconductor equipment and method of manufacturing the same 有权
标题翻译：半导体设备及其制造方法
公开(公告)号：US08384212B2
公开(公告)日：2013-02-26
申请号：US13173647
申请日：2011-06-30
申请人： Nobuyuki Otsuka , Manabu Yanagihara , Shuichi Nagai , Daisuke Ueda
发明人： Nobuyuki Otsuka , Manabu Yanagihara , Shuichi Nagai , Daisuke Ueda
IPC分类号： H01L23/10
CPC分类号： H01L23/427 , H01L21/50 , H01L21/54 , H01L23/045 , H01L23/10 , H01L2224/45124 , H01L2224/48 , H01L2224/73265 , H01L2924/01322 , H01L2924/10253 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012
摘要： To provide a semiconductor equipment having high heat-transfer effect and breakdown voltage, and a method of manufacturing the same. The semiconductor equipment includes: a sealed container; a stem connected to the sealed container via a stem peripheral portion; and a semiconductor chip mounted on a top surface of the stem, inside the sealed container. The semiconductor chip is electrically connected to a lead provided to the stem, the stem peripheral portion, which is of a material that is different from the material of stem and the same as the material of the sealed container, is bonded along a periphery of the stem, and the sealed container is filled with a working fluid including at least one of ethanol, a perfluorocarbon, and a fluoroether.
摘要翻译：提供具有高传热效应和击穿电压的半导体设备及其制造方法。半导体设备包括：密封容器; 通过杆周边部连接到密封容器的杆; 以及安装在所述杆的顶表面上的所述密封容器内的半导体芯片。半导体芯片电连接到设置在杆上的引线，与外壳材料不同的材料的茎周边部分沿密封容器的材料粘结，并且密封容器中填充有包括乙醇，全氟化碳和氟醚中的至少一种的工作流体。

6. 发明申请

US20110305054A1 BI-DIRECTIONAL SWITCH, ALTERNATING-CURRENT TWO-WIRE SWITCH, SWITCHING POWER SOURCE CIRCUIT, AND METHOD OF DRIVING BI-DIRECTIONAL SWITCH 有权
标题翻译：双向开关，交替电流二线开关，开关电源电路以及驱动双向开关的方法
公开(公告)号：US20110305054A1
公开(公告)日：2011-12-15
申请号：US13158934
申请日：2011-06-13
申请人： Hiroto YAMAGIWA , Shingo Hashizume , Manabu Yanagihara , Ayanori Ikoshi
发明人： Hiroto YAMAGIWA , Shingo Hashizume , Manabu Yanagihara , Ayanori Ikoshi
IPC分类号： H02M7/02 , H03K17/94 , H03K17/687
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/42316 , H03K17/6871 , H03K2017/6875 , H03K2217/0009
摘要： A semiconductor device 101 in a bi-directional switch includes: a first electrode 109A, a second electrode 109B, a first gate electrode 112A, and a second gate electrode 112B. In a transition period: when the potential of the first electrode 109A is higher than the potential of the second electrode 109B, a voltage lower than the first threshold voltage is applied to the first gate electrode 112A and a voltage higher than the second threshold value voltage is applied to the second gate electrode 112B; and otherwise, a voltage higher than the first threshold value voltage is applied to the first gate electrode, and a voltage lower than the second threshold value voltage is applied to the second gate electrode.
摘要翻译：双向开关中的半导体器件101包括：第一电极109A，第二电极109B，第一栅电极112A和第二栅电极112B。在过渡期间：当第一电极109A的电位高于第二电极109B的电位时，将低于第一阈值电压的电压施加到第一栅电极112A，并且施加高于第二阈值电压施加到第二栅电极112B; 否则，将高于第一阈值电压的电压施加到第一栅电极，并且将低于第二阈值电压的电压施加到第二栅电极。

7. 发明授权

US07898002B2 Nitride semiconductor device and method for fabricating the same 有权
标题翻译：氮化物半导体器件及其制造方法
公开(公告)号：US07898002B2
公开(公告)日：2011-03-01
申请号：US11890480
申请日：2007-08-07
申请人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L21/337 , H01L21/335
CPC分类号： H01L29/7786 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/432 , H01L29/66462
摘要： A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.
摘要翻译：氮化物半导体器件包括：衬底; 形成在所述基板上的第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更大的带隙能量的第二氮化物半导体层; 形成在所述第二氮化物半导体层上并且包括具有至少单层结构的p型氮化物半导体的第三氮化物半导体层; 形成在所述第三氮化物半导体层上的栅极; 以及分别形成在位于栅电极两侧的区域中的源电极和漏电极。所述第三氮化物半导体层的厚度比所述栅极电极侧的部分的厚度大。

8. 发明申请

US20100327293A1 FIELD-EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20100327293A1
公开(公告)日：2010-12-30
申请号：US12880704
申请日：2010-09-13
申请人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L29/20
CPC分类号： H01L29/7786 , H01L29/0843 , H01L29/1066 , H01L29/2003 , H01L29/432 , H01L29/66462 , H01L29/7783
摘要： An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.
摘要翻译：依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。栅电极与重掺杂的p型GaN层形成欧姆接触。源电极和漏电极设置在未掺杂的AlGaN层上。通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。

9. 发明授权

US07612426B2 Schottky barrier diode and diode array 有权
标题翻译：肖特基势垒二极管和二极管阵列
公开(公告)号：US07612426B2
公开(公告)日：2009-11-03
申请号：US11272878
申请日：2005-11-15
申请人： Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01L29/872
CPC分类号： H01L29/872 , H01L21/26506 , H01L27/0605 , H01L27/0814 , H01L29/0692 , H01L29/417 , H01L29/66143
摘要： A Schottky barrier diode includes a first semiconductor layer and a second semiconductor layer successively formed above a semiconductor substrate with a buffer layer formed between the first and second semiconductor layers and the semiconductor substrate. A Schottky electrode and an ohmic electrode spaced from each other are formed on the second semiconductor layer, and a back face electrode is formed on the back face of the semiconductor substrate. The Schottky electrode or the ohmic electrode is electrically connected to the back face electrode through a via penetrating through at least the buffer layer.
摘要翻译：肖特基势垒二极管包括在半导体衬底上连续形成的第一半导体层和形成在第一和第二半导体层与半导体衬底之间的缓冲层的第二半导体层。在第二半导体层上形成有彼此间隔开的肖特基电极和欧姆电极，在半导体基板的背面形成背面电极。肖特基电极或欧姆电极通过贯穿至少缓冲层的通孔电连接到背面电极。

10. 发明授权

US07605441B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07605441B2
公开(公告)日：2009-10-20
申请号：US11730422
申请日：2007-04-02
申请人： Kazushi Nakazawa , Hiroaki Ueno , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Kazushi Nakazawa , Hiroaki Ueno , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L27/095 , H01L21/28 , H01L29/47
CPC分类号： H01L29/872 , H01L29/2003 , H01L29/66212
摘要： A semiconductor device includes: a semiconductor layer made of a group-III nitride semiconductor and having a first surface and a second surface opposed to the first surface; a Schottky electrode formed on the first surface of the semiconductor layer; and an ohmic electrode electrically connected to the second surface of the semiconductor layer. The semiconductor layer has, in at least the upper portion thereof, highly-resistive regions selectively formed to have a high resistance.
摘要翻译：半导体器件包括：由III族氮化物半导体制成并具有与第一表面相对的第一表面和第二表面的半导体层; 形成在半导体层的第一表面上的肖特基电极; 以及与半导体层的第二表面电连接的欧姆电极。半导体层至少在其上部具有选择性地形成为具有高电阻的高电阻区域。

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