专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050263885A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050263885A1
公开(公告)日：2005-12-01
申请号：US11137356
申请日：2005-05-26
申请人： Yoshifumi Nakamura , Junichi Ueno , Hiroyuki Imamura , Takayuki Tanaka
发明人： Yoshifumi Nakamura , Junichi Ueno , Hiroyuki Imamura , Takayuki Tanaka
IPC分类号： H01L23/485 , H01L23/495 , H01L23/498
CPC分类号： H01L24/10 , H01L23/49838 , H01L23/4985 , H01L24/13 , H01L2224/05001 , H01L2224/05026 , H01L2224/05144 , H01L2224/05147 , H01L2224/05571 , H01L2224/05572 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15173 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device in accordance with the present invention is a mounted body of a semiconductor chip with a plurality of electrode pads arranged in a plurality of stages and a tape wiring board, the average pitch of the electrode pads on the entire semiconductor chip can be reduced, while ensuring stable connectivity, by leading together to the outside of the semiconductor chip two or more wirings of the tape wiring board connected to the electrode pads on the inner side between the electrode pads arranged in a row on the outer periphery of the semiconductor chip.
摘要翻译：根据本发明的半导体器件是具有多个布置在多个级中的多个电极焊盘的半导体芯片的安装体和带状布线板，可以减少整个半导体芯片上的电极焊盘的平均间距同时确保稳定的连接性，通过将半导体芯片的外部引导到与半导体芯片的外周排列成一排的电极焊盘之间的内侧的电极焊盘连接的带状配线基板的两条或更多条布线。

2. 发明申请

US20080136025A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080136025A1
公开(公告)日：2008-06-12
申请号：US12068066
申请日：2008-02-01
申请人： Yoshifumi Nakamura , Junichi Ueno , Hiroyuki Imamura , Takayuki Tanaka
发明人： Yoshifumi Nakamura , Junichi Ueno , Hiroyuki Imamura , Takayuki Tanaka
IPC分类号： H01L23/48
CPC分类号： H01L24/10 , H01L23/49838 , H01L23/4985 , H01L24/13 , H01L2224/05001 , H01L2224/05026 , H01L2224/05144 , H01L2224/05147 , H01L2224/05571 , H01L2224/05572 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15173 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device in accordance with the present invention is a mounted body of a semiconductor chip with a plurality of electrode pads arranged in a plurality of stages and a tape wiring board, the average pitch of the electrode pads on the entire semiconductor chip can be reduced, while ensuring stable connectivity, by leading together to the outside of the semiconductor chip two or more wirings of the tape wiring board connected to the electrode pads on the inner side between the electrode pads arranged in a row on the outer periphery of the semiconductor chip.
摘要翻译：根据本发明的半导体器件是具有多个布置在多个级中的多个电极焊盘的半导体芯片的安装体和带状布线板，可以减少整个半导体芯片上的电极焊盘的平均间距同时确保稳定的连接性，通过将半导体芯片的外部引导到与半导体芯片的外周排列成一排的电极焊盘之间的内侧的电极焊盘连接的带状配线基板的两条或更多条布线。

3. 发明授权

US06956288B2 Semiconductor device with folded film substrate and display device using the same 有权
标题翻译：具有折叠薄膜基板的半导体器件和使用其的显示装置
公开(公告)号：US06956288B2
公开(公告)日：2005-10-18
申请号：US10756121
申请日：2004-01-12
申请人： Junichi Ueno , Michiharu Torii , Takayuki Tanaka
发明人： Junichi Ueno , Michiharu Torii , Takayuki Tanaka
IPC分类号： G02F1/1345 , G02F1/13 , H01L21/60 , H01L23/498 , H01L23/48
CPC分类号： G02F1/13452 , H01L23/4985 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/01078 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device to be mounted on an external electronic device includes a film substrate on which wiring electrodes are formed, the wiring electrodes being partially covered with a covering member; and a semiconductor chip mounted on the film substrate. In this semiconductor device, the film substrate is folded so that at least one edge of the film substrate is on a side opposite to a side on which the semiconductor chip is mounted, and portions of the wiring electrodes exposed from the covering member on a surface of the film substrate on which the semiconductor chip is mounted are to be connected to electrodes of an external electronic device.
摘要翻译：安装在外部电子设备上的半导体器件包括：薄膜基板，其上形成有布线电极，布线电极被覆盖部分覆盖; 以及安装在薄膜基板上的半导体芯片。在该半导体装置中，薄膜基板被折叠，使得薄膜基板的至少一个边缘在与安装半导体芯片的一侧相反的一侧，并且布线电极的一部分从覆盖部件暴露在表面上其上安装有半导体芯片的膜基片将连接到外部电子器件的电极。

4. 发明申请

US20080166952A1 Carrier For Double-Side Polishing Apparatus, Double-Side Polishing Apparatus And Double-Side Polishing Method Using The Same 审中-公开
标题翻译：双面抛光装置用双面抛光装置及其双面抛光方法
公开(公告)号：US20080166952A1
公开(公告)日：2008-07-10
申请号：US11883766
申请日：2006-02-20
申请人： Junichi Ueno
发明人： Junichi Ueno
IPC分类号： H01L21/304 , B24B37/04
CPC分类号： B24B37/28
摘要： The present invention is a carrier for a double-side polishing apparatus in which, in a double-side polishing apparatus, the carrier is set between upper and lower turn tables to which polishing pads are attached, and a holding hole to hold a wafer sandwiched between the upper and lower turn tables in polishing is formed in the carrier, wherein the carrier is made of titanium. Thereby, there is provided a carrier for a double-side polishing apparatus in which the strength of the carrier itself is high, and at the same time, contamination of a wafer such as a silicon wafer by impurities is suppressed, and sag in a peripheral portion of the wafer after being polished is suppressed.
摘要翻译：本发明是一种双面抛光装置的载体，其中在双面研磨装置中，载体设置在安装有抛光垫的上下匝台之间，夹持孔夹持晶片夹持在载体中形成在抛光中的上下转台之间，其中载体由钛制成。因此，提供了一种双面研磨装置的载体，其中载体本身的强度高，同时抑制了诸如硅晶片的晶片被杂质污染，并且在周边的下垂抛光后晶片的部分被抑制。

5. 发明申请

US20060178089A1 Wafer-retaining carrier, double-side grinding device using the same, and double-side grinding method for wafer 审中-公开
标题翻译：晶圆保持架，使用其的双面研磨装置以及晶圆的双面研磨方法
公开(公告)号：US20060178089A1
公开(公告)日：2006-08-10
申请号：US10549453
申请日：2004-03-12
申请人： Junichi Ueno
发明人： Junichi Ueno
IPC分类号： B24B7/30 , B24B7/00 , B24B1/00
CPC分类号： B24B37/28
摘要： The present invention is a wafer-holding carrier 1 wherein the carrier has polishing agent-passing holes 3, 4 for passing the polishing agent through as well as wafer-holding holes 2 for containing and holding wafers, and the total area of the polishing agent-passing holes occupies 15% or more of a main surface of the carrier. Preferably, the total area of the polishing agent-passing holes occupies 30% or less of the main surface of the carrier, and each of the polishing agent-passing holes has a circular shape of a diameter of 5 mm-30 mm, and the holes are arranged in the form of concentric circle or lattice on the carrier entirely. Thereby, there can be provided an art that even when performing polishing by using a hard polishing pad in a double-side polishing apparatus, particularly, a double-side polishing apparatus having a carrier moving circularly without rotation, it is not necessary to reform the apparatus largely, and the wafer of high flatness can be finished without a tapered shape, peripheral sag, and such.
摘要翻译：本发明是晶片保持载体1，其中载体具有用于使研磨剂通过的抛光剂通过孔3,4以及用于容纳和保持晶片的晶片保持孔2，并且抛光剂的总面积通孔占据载体主表面的15％或更多。优选地，抛光剂通过孔的总面积占载体主表面的30％或更少，并且每个抛光剂通过孔具有直径为5mm-30mm的圆形形状，并且孔完全以载体同心圆或格子的形式排列。因此，可以提供一种技术，即使在双面研磨装置中，通过使用硬质研磨垫进行研磨，特别是具有不旋转圆周移动的载体的双面研磨装置，也不需要对装置很大程度上可以在没有锥形形状，周边凹陷等的情况下完成高平坦度的晶圆。

6. 发明申请

US20060113953A1 Inverter 有权
公开(公告)号：US20060113953A1
公开(公告)日：2006-06-01
申请号：US11335434
申请日：2006-01-18
申请人： Hiroshi Shimizu , Junichi Ueno , Kimikazu Kubo , Takashi Asai , Masakazu Komatsu , Yasuyuki Tagano , Toshiyuki Ozaki
发明人： Hiroshi Shimizu , Junichi Ueno , Kimikazu Kubo , Takashi Asai , Masakazu Komatsu , Yasuyuki Tagano , Toshiyuki Ozaki
IPC分类号： H02P27/04
CPC分类号： G05B23/0235
摘要： An inverter has a measuring part that measures an operating time such as the time interval from when a command to start a specified operation by an associated system until a signal indicating the completion of the operation is received. A comparing part compares this measured operating time with a threshold value stored in a memory and an abnormal condition is reported to a host system, depending on the result of the comparison.

7. 发明授权

US08834234B2 Double-side polishing apparatus 有权
标题翻译：双面抛光装置
公开(公告)号：US08834234B2
公开(公告)日：2014-09-16
申请号：US13509696
申请日：2010-11-16
申请人： Junichi Ueno , Kazuya Sato , Syuichi Kobayashi
发明人： Junichi Ueno , Kazuya Sato , Syuichi Kobayashi
IPC分类号： B24B37/013 , B24B37/08
CPC分类号： B24B37/013 , B24B37/08
摘要： A double-side polishing apparatus including at least: upper and lower turn tables each having a polishing pad attached thereto; a carrier having a holding hole formed therein for holding a wafer between the upper and lower turn tables; a sensor for detecting a thickness of the wafer during polishing, the sensor being disposed in a through-hole provided at the upper turn table in a direction of an upper-turn-table rotation axis; and a sensor holder for holding the sensor, wherein a material of the sensor holder is quartz. As a result, there is provided a double-side polishing apparatus that can polish a wafer while the difference from the target wafer thickness is reduced by surely inhibiting deformation of the sensor holder due to the influence of heat generated during the polishing of the wafer.
摘要翻译：一种双面抛光装置，其至少包括：上下转台，每个具有附着在其上的抛光垫; 具有形成在其中用于将晶片保持在上下转台之间的保持孔的载体; 用于在抛光期间检测晶片的厚度的传感器，所述传感器设置在设置在所述上转台上的通孔中，所述通孔沿上转盘旋转轴线的方向; 以及用于保持传感器的传感器保持器，其中传感器保持器的材料是石英。结果，提供了一种双面抛光装置，其可以通过可靠地抑制由于在晶片的抛光期间产生的热的影响而可靠地抑制传感器保持器的变形，从而可以减少与目标晶片厚度之间的差异。

8. 发明授权

US07727053B2 Double-side polishing method for wafer 失效
标题翻译：晶圆双面抛光方法
公开(公告)号：US07727053B2
公开(公告)日：2010-06-01
申请号：US11988830
申请日：2006-06-28
申请人： Junichi Ueno , Syuichi Kobayashi
发明人： Junichi Ueno , Syuichi Kobayashi
IPC分类号： B24B1/00
CPC分类号： B24B37/08 , H01L21/02024
摘要： There is provided a double-side polishing method for a wafer of sandwiching a wafer held in a carrier between upper and lower turn tables each having a polishing pad attached thereto and simultaneously polishing both surfaces of the wafer while supplying a slurry to a space between the upper and lower turn tables from a plurality of slurry supply holes provided in the upper turn table, wherein a polishing amount at an outer peripheral portion of the wafer to be polished is adjusted and outer peripheral sag of the wafer is suppressed by supplying the slurry in such a manner that an amount of the slurry supplied from the slurry supply holes provided on an outer side relative to the center of rotation of the upper turn table becomes larger than an amount of the slurry supplied from the slurry supply holes provided on an inner side relative to the same at the time of polishing both the surfaces of the wafer. As a result, the double-side polishing method which can suppress occurrence of the outer peripheral sag of the wafer when the wafer is subjected to double-side polishing can be provided.
摘要翻译：提供了一种用于将保持在载具上的晶片夹持在上下转台之间的晶片的双面抛光方法，每个晶片具有附接到其上的抛光垫，同时抛光晶片的两个表面，同时将浆料供应到设置在上转台中的多个浆料供给孔的上下转盘，其中调整抛光晶片的外周部分的抛光量，并通过将浆料供给来抑制晶片的外周下垂从设置在上转台的旋转中心的外侧的浆料供给孔供给的浆料的量比从设置在内侧的浆料供给孔供给的浆料的量大相对于在抛光晶片的两个表面时相同。结果，可以提供可以抑制当晶片进行双面抛光时晶片的外周下垂的发生的双面研磨方法。

9. 发明授权

US09327382B2 Carrier for a double-side polishing apparatus, double-side polishing apparatus using this carrier, and double-side polishing method 有权
标题翻译：用于双面抛光装置的载体，使用该载体的双面抛光装置和双面抛光方法
公开(公告)号：US09327382B2
公开(公告)日：2016-05-03
申请号：US12863674
申请日：2009-02-16
申请人： Junichi Ueno , Kazuya Sato , Syuichi Kobayashi
发明人： Junichi Ueno , Kazuya Sato , Syuichi Kobayashi
IPC分类号： B24B37/04 , B24B37/08 , B24B37/28 , B24B37/32
CPC分类号： B24B37/28 , B24B37/042 , B24B37/08
摘要： A carrier for a double-side polishing apparatus comprising at least: a metallic carrier base that is arranged between upper and lower turn tables having polishing pads attached thereto and has a holding hole formed therein to hold a wafer sandwiched between the upper and lower turn tables at the time of polishing; and a ring-like resin insert that is arranged along an inner peripheral portion of the holding hole of the carrier base and is in contact with a peripheral portion of the held wafer, wherein an inner peripheral end portion of the holding hole of the carrier base has an upwardly opening tapered surface, an outer peripheral portion of the ring-like insert has a reverse tapered surface with respect to the tapered surface of the holding hole of the carrier base, and the resin insert is fitted in the holding hole of the carrier base through the tapered surface.
摘要翻译：一种用于双面抛光装置的载体，至少包括：金属载体基座，其布置在上下转台之间，具有安装在其上的抛光垫，并具有形成在其中的保持孔，以夹持夹在上下转台之间的晶片抛光时; 以及环状树脂插入件，其沿着所述承载基座的保持孔的内周部配置并与所述保持晶片的周边部分接触，其中，所述承载器基座的所述保持孔的内周端部具有向上开口的锥形表面，环形插入件的外周部分相对于承载器基座的保持孔的锥形表面具有倒锥形表面，并且树脂插入件装配在载体的保持孔中基部通过锥形表面。

10. 发明授权

US08545291B2 Polishing pad, manufacturing method thereof and polishing method 有权
标题翻译：抛光垫，其制造方法和抛光方法
公开(公告)号：US08545291B2
公开(公告)日：2013-10-01
申请号：US13379588
申请日：2010-06-22
申请人： Kohki Itoyama , Daisuke Takahashi , Junichi Ueno , Syuichi Kobayashi
发明人： Kohki Itoyama , Daisuke Takahashi , Junichi Ueno , Syuichi Kobayashi
IPC分类号： B24B37/04
CPC分类号： B24B37/24 , B24D3/32 , H01L21/02024
摘要： A polishing pad capable of improving an affinity to polishing liquid and stabilizing polishing performance is provided. A polishing pad 10 is equipped with a urethane sheet 2. The urethane sheet 2 has a polishing surface P for polishing an object to be polished. The urethane sheet 2 is formed by a dry molding method and is formed by slicing a polyurethane foamed body which is obtained by reacting and curing mixed liquid in which an isocyanate-group containing compound, water, a foam control agent and a polyamine compound are mixed. Foams 3 are dispersed approximately uniformly inside the urethane sheet 2. Opened pores 4 which are opened parts of the foams 3 are formed at the polishing surface P. Inside the urethane sheet 2, the foams 3 formed adjacently to each other are communicated by communication holes 9, and the communication holes 9 are formed at a ratio of 800 holes/cm2 or more when observed from a side of the polishing surface P. Polishing liquid moves via the communication holes 9 and the foams 3.
摘要翻译：提供了能够提高对抛光液的亲和性和稳定研磨性能的抛光垫。抛光垫10配备有聚氨酯片2.聚氨酯片2具有用于抛光待抛光物体的抛光面P. 氨基甲酸酯片2通过干式成型法形成，通过将通过使含有异氰酸酯基的化合物，水，泡沫调节剂和多胺化合物混合的混合液反应固化而得到的聚氨酯发泡体切片而形成。泡沫3大致均匀地分散在聚氨酯片材2内。在研磨面P上形成作为泡沫体3的开口部的开口孔4.在氨基甲酸酯片材2的内部，相邻形成的泡沫体3通过连通孔如图9所示，并且当从抛光表面P的侧面观察时，连通孔9以800个孔/ cm 2以上的比例形成。抛光液体经由连通孔9和泡沫3移动。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式